1 /* 2 * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_36BIT 33 #define CONFIG_PHYS_64BIT 1 34 #endif 35 36 #ifdef CONFIG_NAND 37 #define CONFIG_NAND_U_BOOT 1 38 #define CONFIG_RAMBOOT_NAND 1 39 #ifdef CONFIG_NAND_SPL 40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42 #else 43 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 44 #endif /* CONFIG_NAND_SPL */ 45 #endif 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RAMBOOT_SDCARD 1 49 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 51 #endif 52 53 #ifdef CONFIG_SPIFLASH 54 #define CONFIG_RAMBOOT_SPIFLASH 1 55 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 57 #endif 58 59 #ifndef CONFIG_SYS_TEXT_BASE 60 #define CONFIG_SYS_TEXT_BASE 0xeff80000 61 #endif 62 63 #ifndef CONFIG_RESET_VECTOR_ADDRESS 64 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 65 #endif 66 67 #ifndef CONFIG_SYS_MONITOR_BASE 68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 69 #endif 70 71 /* High Level Configuration Options */ 72 #define CONFIG_BOOKE 1 /* BOOKE */ 73 #define CONFIG_E500 1 /* BOOKE e500 family */ 74 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 75 #define CONFIG_MPC8536 1 76 #define CONFIG_MPC8536DS 1 77 78 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 79 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 80 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 81 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 82 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 83 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 84 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 85 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 86 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 87 88 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 89 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 90 91 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 92 #define CONFIG_ENV_OVERWRITE 93 94 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 95 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 96 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 97 98 /* 99 * These can be toggled for performance analysis, otherwise use default. 100 */ 101 #define CONFIG_L2_CACHE /* toggle L2 cache */ 102 #define CONFIG_BTB /* toggle branch predition */ 103 104 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 105 106 #define CONFIG_ENABLE_36BIT_PHYS 1 107 108 #ifdef CONFIG_PHYS_64BIT 109 #define CONFIG_ADDR_MAP 1 110 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 111 #endif 112 113 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 114 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 115 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 116 117 /* 118 * Config the L2 Cache as L2 SRAM 119 */ 120 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 121 #ifdef CONFIG_PHYS_64BIT 122 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 123 #else 124 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 125 #endif 126 #define CONFIG_SYS_L2_SIZE (512 << 10) 127 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 128 129 /* 130 * Base addresses -- Note these are effective addresses where the 131 * actual resources get mapped (not physical addresses) 132 */ 133 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 136 #else 137 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 138 #endif 139 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 140 141 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 142 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 143 #else 144 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 145 #endif 146 147 /* DDR Setup */ 148 #define CONFIG_VERY_BIG_RAM 149 #define CONFIG_FSL_DDR2 150 #undef CONFIG_FSL_DDR_INTERACTIVE 151 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 152 #define CONFIG_DDR_SPD 153 154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 155 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 156 157 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 159 160 #define CONFIG_NUM_DDR_CONTROLLERS 1 161 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 162 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 163 164 /* I2C addresses of SPD EEPROMs */ 165 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 166 #define CONFIG_SYS_SPD_BUS_NUM 1 167 168 /* These are used when DDR doesn't use SPD. */ 169 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 170 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 171 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 172 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 173 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 174 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 175 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 176 #define CONFIG_SYS_DDR_MODE_1 0x00480432 177 #define CONFIG_SYS_DDR_MODE_2 0x00000000 178 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 179 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 180 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 181 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 182 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 183 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 184 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 185 186 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 187 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 188 #define CONFIG_SYS_DDR_SBE 0x00010000 189 190 /* Make sure required options are set */ 191 #ifndef CONFIG_SPD_EEPROM 192 #error ("CONFIG_SPD_EEPROM is required") 193 #endif 194 195 #undef CONFIG_CLOCKS_IN_MHZ 196 197 198 /* 199 * Memory map -- xxx -this is wrong, needs updating 200 * 201 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 202 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 203 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 204 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 205 * 206 * Localbus cacheable (TBD) 207 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 208 * 209 * Localbus non-cacheable 210 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 211 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 212 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 213 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 214 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 215 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 216 */ 217 218 /* 219 * Local Bus Definitions 220 */ 221 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 222 #ifdef CONFIG_PHYS_64BIT 223 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 224 #else 225 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 226 #endif 227 228 #define CONFIG_FLASH_BR_PRELIM \ 229 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 230 | BR_PS_16 | BR_V) 231 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 232 233 #define CONFIG_SYS_BR1_PRELIM \ 234 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 235 | BR_PS_16 | BR_V) 236 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 237 238 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 239 CONFIG_SYS_FLASH_BASE_PHYS } 240 #define CONFIG_SYS_FLASH_QUIET_TEST 241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 242 243 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 245 #undef CONFIG_SYS_FLASH_CHECKSUM 246 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 249 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ 250 defined(CONFIG_RAMBOOT_SPIFLASH) 251 #define CONFIG_SYS_RAMBOOT 252 #define CONFIG_SYS_EXTRA_ENV_RELOC 253 #else 254 #undef CONFIG_SYS_RAMBOOT 255 #endif 256 257 #define CONFIG_FLASH_CFI_DRIVER 258 #define CONFIG_SYS_FLASH_CFI 259 #define CONFIG_SYS_FLASH_EMPTY_INFO 260 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 261 262 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 263 264 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 265 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 266 #ifdef CONFIG_PHYS_64BIT 267 #define PIXIS_BASE_PHYS 0xfffdf0000ull 268 #else 269 #define PIXIS_BASE_PHYS PIXIS_BASE 270 #endif 271 272 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 273 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 274 275 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 276 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 277 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 278 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 279 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 280 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 281 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 282 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 283 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 284 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 285 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 286 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 287 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 288 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 289 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 290 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 291 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 292 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 293 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 294 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 295 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 296 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 297 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 298 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 299 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 300 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 301 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 302 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 303 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 304 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 305 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 306 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 307 #define PIXIS_LED 0x25 /* LED Register */ 308 309 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 310 311 /* old pixis referenced names */ 312 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 313 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 314 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 315 316 #define CONFIG_SYS_INIT_RAM_LOCK 1 317 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 318 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 319 320 #define CONFIG_SYS_GBL_DATA_OFFSET \ 321 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 322 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 323 324 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 325 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 326 327 #ifndef CONFIG_NAND_SPL 328 #define CONFIG_SYS_NAND_BASE 0xffa00000 329 #ifdef CONFIG_PHYS_64BIT 330 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 331 #else 332 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 333 #endif 334 #else 335 #define CONFIG_SYS_NAND_BASE 0xfff00000 336 #ifdef CONFIG_PHYS_64BIT 337 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 338 #else 339 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 340 #endif 341 #endif 342 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 343 CONFIG_SYS_NAND_BASE + 0x40000, \ 344 CONFIG_SYS_NAND_BASE + 0x80000, \ 345 CONFIG_SYS_NAND_BASE + 0xC0000} 346 #define CONFIG_SYS_MAX_NAND_DEVICE 4 347 #define CONFIG_MTD_NAND_VERIFY_WRITE 348 #define CONFIG_CMD_NAND 1 349 #define CONFIG_NAND_FSL_ELBC 1 350 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 351 352 /* NAND boot: 4K NAND loader config */ 353 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 354 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 355 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 356 #define CONFIG_SYS_NAND_U_BOOT_START \ 357 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 358 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 359 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 360 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 361 362 /* NAND flash config */ 363 #define CONFIG_NAND_BR_PRELIM \ 364 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 365 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 366 | BR_PS_8 /* Port Size = 8 bit */ \ 367 | BR_MS_FCM /* MSEL = FCM */ \ 368 | BR_V) /* valid */ 369 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 370 | OR_FCM_PGS /* Large Page*/ \ 371 | OR_FCM_CSCT \ 372 | OR_FCM_CST \ 373 | OR_FCM_CHT \ 374 | OR_FCM_SCY_1 \ 375 | OR_FCM_TRLX \ 376 | OR_FCM_EHTR) 377 378 #ifdef CONFIG_RAMBOOT_NAND 379 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 380 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 381 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 382 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 383 #else 384 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 385 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 386 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 387 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 388 #endif 389 390 #define CONFIG_SYS_BR4_PRELIM \ 391 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 392 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 393 | BR_PS_8 /* Port Size = 8 bit */ \ 394 | BR_MS_FCM /* MSEL = FCM */ \ 395 | BR_V) /* valid */ 396 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 397 #define CONFIG_SYS_BR5_PRELIM \ 398 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 399 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 400 | BR_PS_8 /* Port Size = 8 bit */ \ 401 | BR_MS_FCM /* MSEL = FCM */ \ 402 | BR_V) /* valid */ 403 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 404 405 #define CONFIG_SYS_BR6_PRELIM \ 406 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 407 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 408 | BR_PS_8 /* Port Size = 8 bit */ \ 409 | BR_MS_FCM /* MSEL = FCM */ \ 410 | BR_V) /* valid */ 411 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 412 413 /* Serial Port - controlled on board with jumper J8 414 * open - index 2 415 * shorted - index 1 416 */ 417 #define CONFIG_CONS_INDEX 1 418 #define CONFIG_SYS_NS16550 419 #define CONFIG_SYS_NS16550_SERIAL 420 #define CONFIG_SYS_NS16550_REG_SIZE 1 421 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 422 #ifdef CONFIG_NAND_SPL 423 #define CONFIG_NS16550_MIN_FUNCTIONS 424 #endif 425 426 #define CONFIG_SYS_BAUDRATE_TABLE \ 427 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 428 429 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 430 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 431 432 /* Use the HUSH parser */ 433 #define CONFIG_SYS_HUSH_PARSER 434 #ifdef CONFIG_SYS_HUSH_PARSER 435 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 436 #endif 437 438 /* 439 * Pass open firmware flat tree 440 */ 441 #define CONFIG_OF_LIBFDT 1 442 #define CONFIG_OF_BOARD_SETUP 1 443 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 444 445 /* 446 * I2C 447 */ 448 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 449 #define CONFIG_HARD_I2C /* I2C with hardware support */ 450 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 451 #define CONFIG_I2C_MULTI_BUS 452 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 453 #define CONFIG_SYS_I2C_SLAVE 0x7F 454 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 455 #define CONFIG_SYS_I2C_OFFSET 0x3000 456 #define CONFIG_SYS_I2C2_OFFSET 0x3100 457 458 /* 459 * I2C2 EEPROM 460 */ 461 #define CONFIG_ID_EEPROM 462 #ifdef CONFIG_ID_EEPROM 463 #define CONFIG_SYS_I2C_EEPROM_NXID 464 #endif 465 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 466 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 467 #define CONFIG_SYS_EEPROM_BUS_NUM 1 468 469 /* 470 * General PCI 471 * Memory space is mapped 1-1, but I/O space must start from 0. 472 */ 473 474 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 475 #ifdef CONFIG_PHYS_64BIT 476 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 477 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 478 #else 479 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 480 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 481 #endif 482 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 483 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 484 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 487 #else 488 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 489 #endif 490 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 491 492 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 493 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 494 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 495 #ifdef CONFIG_PHYS_64BIT 496 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 497 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 498 #else 499 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 500 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 501 #endif 502 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 503 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 504 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 505 #ifdef CONFIG_PHYS_64BIT 506 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 507 #else 508 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 509 #endif 510 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 511 512 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 513 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 514 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 515 #ifdef CONFIG_PHYS_64BIT 516 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 517 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 518 #else 519 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 520 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 521 #endif 522 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 523 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 524 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 525 #ifdef CONFIG_PHYS_64BIT 526 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 527 #else 528 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 529 #endif 530 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 531 532 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 533 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 534 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 535 #ifdef CONFIG_PHYS_64BIT 536 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 537 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 538 #else 539 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 540 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 541 #endif 542 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 543 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 544 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 545 #ifdef CONFIG_PHYS_64BIT 546 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 547 #else 548 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 549 #endif 550 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 551 552 #if defined(CONFIG_PCI) 553 554 #define CONFIG_NET_MULTI 555 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 556 557 /*PCIE video card used*/ 558 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 559 560 /*PCI video card used*/ 561 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 562 563 /* video */ 564 #define CONFIG_VIDEO 565 566 #if defined(CONFIG_VIDEO) 567 #define CONFIG_BIOSEMU 568 #define CONFIG_CFB_CONSOLE 569 #define CONFIG_VIDEO_SW_CURSOR 570 #define CONFIG_VGA_AS_SINGLE_DEVICE 571 #define CONFIG_ATI_RADEON_FB 572 #define CONFIG_VIDEO_LOGO 573 /*#define CONFIG_CONSOLE_CURSOR*/ 574 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 575 #endif 576 577 #undef CONFIG_EEPRO100 578 #undef CONFIG_TULIP 579 #undef CONFIG_RTL8139 580 581 #ifndef CONFIG_PCI_PNP 582 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 583 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 584 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 585 #endif 586 587 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 588 589 #endif /* CONFIG_PCI */ 590 591 /* SATA */ 592 #define CONFIG_LIBATA 593 #define CONFIG_FSL_SATA 594 595 #define CONFIG_SYS_SATA_MAX_DEVICE 2 596 #define CONFIG_SATA1 597 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 598 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 599 #define CONFIG_SATA2 600 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 601 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 602 603 #ifdef CONFIG_FSL_SATA 604 #define CONFIG_LBA48 605 #define CONFIG_CMD_SATA 606 #define CONFIG_DOS_PARTITION 607 #define CONFIG_CMD_EXT2 608 #endif 609 610 #if defined(CONFIG_TSEC_ENET) 611 612 #ifndef CONFIG_NET_MULTI 613 #define CONFIG_NET_MULTI 1 614 #endif 615 616 #define CONFIG_MII 1 /* MII PHY management */ 617 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 618 #define CONFIG_TSEC1 1 619 #define CONFIG_TSEC1_NAME "eTSEC1" 620 #define CONFIG_TSEC3 1 621 #define CONFIG_TSEC3_NAME "eTSEC3" 622 623 #define CONFIG_FSL_SGMII_RISER 1 624 #define SGMII_RISER_PHY_OFFSET 0x1c 625 626 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 627 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 628 629 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 630 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 631 632 #define TSEC1_PHYIDX 0 633 #define TSEC3_PHYIDX 0 634 635 #define CONFIG_ETHPRIME "eTSEC1" 636 637 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 638 639 #endif /* CONFIG_TSEC_ENET */ 640 641 /* 642 * Environment 643 */ 644 645 #if defined(CONFIG_SYS_RAMBOOT) 646 #if defined(CONFIG_RAMBOOT_NAND) 647 #define CONFIG_ENV_IS_IN_NAND 1 648 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 649 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 650 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 651 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 652 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 653 #define CONFIG_ENV_SIZE 0x2000 654 #endif 655 #else 656 #define CONFIG_ENV_IS_IN_FLASH 1 657 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 658 #define CONFIG_ENV_ADDR 0xfff80000 659 #else 660 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 661 #endif 662 #define CONFIG_ENV_SIZE 0x2000 663 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 664 #endif 665 666 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 667 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 668 669 /* 670 * Command line configuration. 671 */ 672 #include <config_cmd_default.h> 673 674 #define CONFIG_CMD_IRQ 675 #define CONFIG_CMD_PING 676 #define CONFIG_CMD_I2C 677 #define CONFIG_CMD_MII 678 #define CONFIG_CMD_ELF 679 #define CONFIG_CMD_IRQ 680 #define CONFIG_CMD_SETEXPR 681 #define CONFIG_CMD_REGINFO 682 683 #if defined(CONFIG_PCI) 684 #define CONFIG_CMD_PCI 685 #define CONFIG_CMD_NET 686 #endif 687 688 #undef CONFIG_WATCHDOG /* watchdog disabled */ 689 690 #define CONFIG_MMC 1 691 692 #ifdef CONFIG_MMC 693 #define CONFIG_FSL_ESDHC 694 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 695 #define CONFIG_CMD_MMC 696 #define CONFIG_GENERIC_MMC 697 #define CONFIG_CMD_EXT2 698 #define CONFIG_CMD_FAT 699 #define CONFIG_DOS_PARTITION 700 #endif 701 702 /* 703 * Miscellaneous configurable options 704 */ 705 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 706 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 707 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 708 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 709 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 710 #if defined(CONFIG_CMD_KGDB) 711 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 712 #else 713 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 714 #endif 715 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 716 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 717 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 718 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 719 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 720 721 /* 722 * For booting Linux, the board info and command line data 723 * have to be in the first 16 MB of memory, since this is 724 * the maximum mapped by the Linux kernel during initialization. 725 */ 726 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 727 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 728 729 #if defined(CONFIG_CMD_KGDB) 730 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 731 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 732 #endif 733 734 /* 735 * Environment Configuration 736 */ 737 738 /* The mac addresses for all ethernet interface */ 739 #if defined(CONFIG_TSEC_ENET) 740 #define CONFIG_HAS_ETH0 741 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 742 #define CONFIG_HAS_ETH1 743 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 744 #define CONFIG_HAS_ETH2 745 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 746 #define CONFIG_HAS_ETH3 747 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 748 #endif 749 750 #define CONFIG_IPADDR 192.168.1.254 751 752 #define CONFIG_HOSTNAME unknown 753 #define CONFIG_ROOTPATH /opt/nfsroot 754 #define CONFIG_BOOTFILE uImage 755 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 756 757 #define CONFIG_SERVERIP 192.168.1.1 758 #define CONFIG_GATEWAYIP 192.168.1.1 759 #define CONFIG_NETMASK 255.255.255.0 760 761 /* default location for tftp and bootm */ 762 #define CONFIG_LOADADDR 1000000 763 764 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 765 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 766 767 #define CONFIG_BAUDRATE 115200 768 769 #define CONFIG_EXTRA_ENV_SETTINGS \ 770 "netdev=eth0\0" \ 771 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 772 "tftpflash=tftpboot $loadaddr $uboot; " \ 773 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 774 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 775 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 776 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 777 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 778 "consoledev=ttyS0\0" \ 779 "ramdiskaddr=2000000\0" \ 780 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 781 "fdtaddr=c00000\0" \ 782 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 783 "bdev=sda3\0" \ 784 "usb_phy_type=ulpi\0" 785 786 #define CONFIG_HDBOOT \ 787 "setenv bootargs root=/dev/$bdev rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $loadaddr $bootfile;" \ 790 "tftp $fdtaddr $fdtfile;" \ 791 "bootm $loadaddr - $fdtaddr" 792 793 #define CONFIG_NFSBOOTCOMMAND \ 794 "setenv bootargs root=/dev/nfs rw " \ 795 "nfsroot=$serverip:$rootpath " \ 796 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr - $fdtaddr" 801 802 #define CONFIG_RAMBOOTCOMMAND \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "tftp $ramdiskaddr $ramdiskfile;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr $ramdiskaddr $fdtaddr" 809 810 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 811 812 #endif /* __CONFIG_H */ 813