1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 1 18 #endif 19 20 #ifdef CONFIG_NAND 21 #define CONFIG_NAND_U_BOOT 1 22 #define CONFIG_RAMBOOT_NAND 1 23 #ifdef CONFIG_NAND_SPL 24 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 26 #else 27 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 28 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 29 #endif /* CONFIG_NAND_SPL */ 30 #endif 31 32 #ifdef CONFIG_SDCARD 33 #define CONFIG_RAMBOOT_SDCARD 1 34 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 36 #endif 37 38 #ifdef CONFIG_SPIFLASH 39 #define CONFIG_RAMBOOT_SPIFLASH 1 40 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 41 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 42 #endif 43 44 #ifndef CONFIG_SYS_TEXT_BASE 45 #define CONFIG_SYS_TEXT_BASE 0xeff80000 46 #endif 47 48 #ifndef CONFIG_RESET_VECTOR_ADDRESS 49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #endif 51 52 #ifndef CONFIG_SYS_MONITOR_BASE 53 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 54 #endif 55 56 /* High Level Configuration Options */ 57 #define CONFIG_BOOKE 1 /* BOOKE */ 58 #define CONFIG_E500 1 /* BOOKE e500 family */ 59 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 60 #define CONFIG_MPC8536 1 61 #define CONFIG_MPC8536DS 1 62 63 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 64 #define CONFIG_SPI_FLASH 1 /* Has SPI Flash */ 65 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 66 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 67 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 68 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 69 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 70 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 71 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 72 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 73 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 74 75 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 76 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 77 78 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 79 #define CONFIG_ENV_OVERWRITE 80 81 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 82 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 83 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 84 85 /* 86 * These can be toggled for performance analysis, otherwise use default. 87 */ 88 #define CONFIG_L2_CACHE /* toggle L2 cache */ 89 #define CONFIG_BTB /* toggle branch predition */ 90 91 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 92 93 #define CONFIG_ENABLE_36BIT_PHYS 1 94 95 #ifdef CONFIG_PHYS_64BIT 96 #define CONFIG_ADDR_MAP 1 97 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 98 #endif 99 100 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 101 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 102 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 103 104 /* 105 * Config the L2 Cache as L2 SRAM 106 */ 107 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 108 #ifdef CONFIG_PHYS_64BIT 109 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 110 #else 111 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 112 #endif 113 #define CONFIG_SYS_L2_SIZE (512 << 10) 114 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 115 116 #define CONFIG_SYS_CCSRBAR 0xffe00000 117 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 118 119 #if defined(CONFIG_NAND_SPL) 120 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 121 #endif 122 123 /* DDR Setup */ 124 #define CONFIG_VERY_BIG_RAM 125 #define CONFIG_FSL_DDR2 126 #undef CONFIG_FSL_DDR_INTERACTIVE 127 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 128 #define CONFIG_DDR_SPD 129 130 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 131 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 132 133 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 134 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 135 136 #define CONFIG_NUM_DDR_CONTROLLERS 1 137 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 138 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 139 140 /* I2C addresses of SPD EEPROMs */ 141 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 142 #define CONFIG_SYS_SPD_BUS_NUM 1 143 144 /* These are used when DDR doesn't use SPD. */ 145 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 147 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 148 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 149 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 150 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 151 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 152 #define CONFIG_SYS_DDR_MODE_1 0x00480432 153 #define CONFIG_SYS_DDR_MODE_2 0x00000000 154 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 155 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 156 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 157 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 158 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 159 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 160 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 161 162 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 163 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 164 #define CONFIG_SYS_DDR_SBE 0x00010000 165 166 /* Make sure required options are set */ 167 #ifndef CONFIG_SPD_EEPROM 168 #error ("CONFIG_SPD_EEPROM is required") 169 #endif 170 171 #undef CONFIG_CLOCKS_IN_MHZ 172 173 174 /* 175 * Memory map -- xxx -this is wrong, needs updating 176 * 177 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 178 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 179 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 180 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 181 * 182 * Localbus cacheable (TBD) 183 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 184 * 185 * Localbus non-cacheable 186 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 187 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 188 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 189 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 190 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 191 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 192 */ 193 194 /* 195 * Local Bus Definitions 196 */ 197 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 198 #ifdef CONFIG_PHYS_64BIT 199 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 200 #else 201 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 202 #endif 203 204 #define CONFIG_FLASH_BR_PRELIM \ 205 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 206 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 207 208 #define CONFIG_SYS_BR1_PRELIM \ 209 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 210 | BR_PS_16 | BR_V) 211 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 212 213 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 214 CONFIG_SYS_FLASH_BASE_PHYS } 215 #define CONFIG_SYS_FLASH_QUIET_TEST 216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 220 #undef CONFIG_SYS_FLASH_CHECKSUM 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ 225 defined(CONFIG_RAMBOOT_SPIFLASH) 226 #define CONFIG_SYS_RAMBOOT 227 #define CONFIG_SYS_EXTRA_ENV_RELOC 228 #else 229 #undef CONFIG_SYS_RAMBOOT 230 #endif 231 232 #define CONFIG_FLASH_CFI_DRIVER 233 #define CONFIG_SYS_FLASH_CFI 234 #define CONFIG_SYS_FLASH_EMPTY_INFO 235 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 236 237 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 238 239 #define CONFIG_HWCONFIG /* enable hwconfig */ 240 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 241 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 242 #ifdef CONFIG_PHYS_64BIT 243 #define PIXIS_BASE_PHYS 0xfffdf0000ull 244 #else 245 #define PIXIS_BASE_PHYS PIXIS_BASE 246 #endif 247 248 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 249 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 250 251 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 252 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 253 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 254 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 255 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 256 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 257 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 258 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 259 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 260 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 261 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 262 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 263 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 264 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 265 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 266 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 267 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 268 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 269 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 270 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 271 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 272 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 273 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 274 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 275 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 276 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 277 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 278 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 279 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 280 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 281 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 282 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 283 #define PIXIS_LED 0x25 /* LED Register */ 284 285 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 286 287 /* old pixis referenced names */ 288 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 289 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 290 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 291 292 #define CONFIG_SYS_INIT_RAM_LOCK 1 293 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 294 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 295 296 #define CONFIG_SYS_GBL_DATA_OFFSET \ 297 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 298 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 299 300 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 301 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 302 303 #ifndef CONFIG_NAND_SPL 304 #define CONFIG_SYS_NAND_BASE 0xffa00000 305 #ifdef CONFIG_PHYS_64BIT 306 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 307 #else 308 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 309 #endif 310 #else 311 #define CONFIG_SYS_NAND_BASE 0xfff00000 312 #ifdef CONFIG_PHYS_64BIT 313 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 314 #else 315 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 316 #endif 317 #endif 318 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 319 CONFIG_SYS_NAND_BASE + 0x40000, \ 320 CONFIG_SYS_NAND_BASE + 0x80000, \ 321 CONFIG_SYS_NAND_BASE + 0xC0000} 322 #define CONFIG_SYS_MAX_NAND_DEVICE 4 323 #define CONFIG_MTD_NAND_VERIFY_WRITE 324 #define CONFIG_CMD_NAND 1 325 #define CONFIG_NAND_FSL_ELBC 1 326 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 327 328 /* NAND boot: 4K NAND loader config */ 329 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 330 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 331 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 332 #define CONFIG_SYS_NAND_U_BOOT_START \ 333 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 334 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 335 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 336 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 337 338 /* NAND flash config */ 339 #define CONFIG_SYS_NAND_BR_PRELIM \ 340 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 341 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 342 | BR_PS_8 /* Port Size = 8 bit */ \ 343 | BR_MS_FCM /* MSEL = FCM */ \ 344 | BR_V) /* valid */ 345 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 346 | OR_FCM_PGS /* Large Page*/ \ 347 | OR_FCM_CSCT \ 348 | OR_FCM_CST \ 349 | OR_FCM_CHT \ 350 | OR_FCM_SCY_1 \ 351 | OR_FCM_TRLX \ 352 | OR_FCM_EHTR) 353 354 #ifdef CONFIG_RAMBOOT_NAND 355 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 356 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 357 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 358 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 359 #else 360 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 361 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 362 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 363 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 364 #endif 365 366 #define CONFIG_SYS_BR4_PRELIM \ 367 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 368 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 369 | BR_PS_8 /* Port Size = 8 bit */ \ 370 | BR_MS_FCM /* MSEL = FCM */ \ 371 | BR_V) /* valid */ 372 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 373 #define CONFIG_SYS_BR5_PRELIM \ 374 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 375 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 376 | BR_PS_8 /* Port Size = 8 bit */ \ 377 | BR_MS_FCM /* MSEL = FCM */ \ 378 | BR_V) /* valid */ 379 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 380 381 #define CONFIG_SYS_BR6_PRELIM \ 382 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 383 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 384 | BR_PS_8 /* Port Size = 8 bit */ \ 385 | BR_MS_FCM /* MSEL = FCM */ \ 386 | BR_V) /* valid */ 387 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 388 389 /* Serial Port - controlled on board with jumper J8 390 * open - index 2 391 * shorted - index 1 392 */ 393 #define CONFIG_CONS_INDEX 1 394 #define CONFIG_SYS_NS16550 395 #define CONFIG_SYS_NS16550_SERIAL 396 #define CONFIG_SYS_NS16550_REG_SIZE 1 397 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 398 #ifdef CONFIG_NAND_SPL 399 #define CONFIG_NS16550_MIN_FUNCTIONS 400 #endif 401 402 #define CONFIG_SYS_BAUDRATE_TABLE \ 403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 404 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 407 408 /* Use the HUSH parser */ 409 #define CONFIG_SYS_HUSH_PARSER 410 411 /* 412 * Pass open firmware flat tree 413 */ 414 #define CONFIG_OF_LIBFDT 1 415 #define CONFIG_OF_BOARD_SETUP 1 416 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 417 418 /* 419 * I2C 420 */ 421 #define CONFIG_SYS_I2C 422 #define CONFIG_SYS_I2C_FSL 423 #define CONFIG_SYS_FSL_I2C_SPEED 400000 424 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 425 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 426 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 427 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 428 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 429 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 430 431 /* 432 * I2C2 EEPROM 433 */ 434 #define CONFIG_ID_EEPROM 435 #ifdef CONFIG_ID_EEPROM 436 #define CONFIG_SYS_I2C_EEPROM_NXID 437 #endif 438 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 439 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 440 #define CONFIG_SYS_EEPROM_BUS_NUM 1 441 442 /* 443 * eSPI - Enhanced SPI 444 */ 445 #define CONFIG_HARD_SPI 446 #define CONFIG_FSL_ESPI 447 448 #if defined(CONFIG_SPI_FLASH) 449 #define CONFIG_SPI_FLASH_SPANSION 450 #define CONFIG_CMD_SF 451 #define CONFIG_SF_DEFAULT_SPEED 10000000 452 #define CONFIG_SF_DEFAULT_MODE 0 453 #endif 454 455 /* 456 * General PCI 457 * Memory space is mapped 1-1, but I/O space must start from 0. 458 */ 459 460 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 461 #ifdef CONFIG_PHYS_64BIT 462 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 463 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 464 #else 465 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 466 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 467 #endif 468 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 469 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 470 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 473 #else 474 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 475 #endif 476 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 477 478 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 479 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 480 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 484 #else 485 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 486 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 487 #endif 488 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 489 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 490 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 491 #ifdef CONFIG_PHYS_64BIT 492 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 493 #else 494 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 495 #endif 496 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 497 498 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 499 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 500 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 501 #ifdef CONFIG_PHYS_64BIT 502 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 503 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 504 #else 505 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 506 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 507 #endif 508 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 509 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 510 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 511 #ifdef CONFIG_PHYS_64BIT 512 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 513 #else 514 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 515 #endif 516 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 519 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 520 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 521 #ifdef CONFIG_PHYS_64BIT 522 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 523 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 524 #else 525 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 526 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 527 #endif 528 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 529 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 530 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 531 #ifdef CONFIG_PHYS_64BIT 532 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 533 #else 534 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 535 #endif 536 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 537 538 #if defined(CONFIG_PCI) 539 540 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 541 542 /*PCIE video card used*/ 543 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 544 545 /*PCI video card used*/ 546 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 547 548 /* video */ 549 #define CONFIG_VIDEO 550 551 #if defined(CONFIG_VIDEO) 552 #define CONFIG_BIOSEMU 553 #define CONFIG_CFB_CONSOLE 554 #define CONFIG_VIDEO_SW_CURSOR 555 #define CONFIG_VGA_AS_SINGLE_DEVICE 556 #define CONFIG_ATI_RADEON_FB 557 #define CONFIG_VIDEO_LOGO 558 /*#define CONFIG_CONSOLE_CURSOR*/ 559 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 560 #endif 561 562 #undef CONFIG_EEPRO100 563 #undef CONFIG_TULIP 564 #undef CONFIG_RTL8139 565 566 #ifndef CONFIG_PCI_PNP 567 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 568 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 569 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 570 #endif 571 572 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 573 574 #endif /* CONFIG_PCI */ 575 576 /* SATA */ 577 #define CONFIG_LIBATA 578 #define CONFIG_FSL_SATA 579 580 #define CONFIG_SYS_SATA_MAX_DEVICE 2 581 #define CONFIG_SATA1 582 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 583 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 584 #define CONFIG_SATA2 585 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 586 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 587 588 #ifdef CONFIG_FSL_SATA 589 #define CONFIG_LBA48 590 #define CONFIG_CMD_SATA 591 #define CONFIG_DOS_PARTITION 592 #define CONFIG_CMD_EXT2 593 #endif 594 595 #if defined(CONFIG_TSEC_ENET) 596 597 #define CONFIG_MII 1 /* MII PHY management */ 598 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 599 #define CONFIG_TSEC1 1 600 #define CONFIG_TSEC1_NAME "eTSEC1" 601 #define CONFIG_TSEC3 1 602 #define CONFIG_TSEC3_NAME "eTSEC3" 603 604 #define CONFIG_FSL_SGMII_RISER 1 605 #define SGMII_RISER_PHY_OFFSET 0x1c 606 607 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 608 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 609 610 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 611 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 612 613 #define TSEC1_PHYIDX 0 614 #define TSEC3_PHYIDX 0 615 616 #define CONFIG_ETHPRIME "eTSEC1" 617 618 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 619 620 #endif /* CONFIG_TSEC_ENET */ 621 622 /* 623 * Environment 624 */ 625 626 #if defined(CONFIG_SYS_RAMBOOT) 627 #if defined(CONFIG_RAMBOOT_NAND) 628 #define CONFIG_ENV_IS_IN_NAND 1 629 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 630 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 631 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 632 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 633 #define CONFIG_ENV_IS_IN_SPI_FLASH 634 #define CONFIG_ENV_SPI_BUS 0 635 #define CONFIG_ENV_SPI_CS 0 636 #define CONFIG_ENV_SPI_MAX_HZ 10000000 637 #define CONFIG_ENV_SPI_MODE 0 638 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 639 #define CONFIG_ENV_OFFSET 0xF0000 640 #define CONFIG_ENV_SECT_SIZE 0x10000 641 #elif defined(CONFIG_RAMBOOT_SDCARD) 642 #define CONFIG_ENV_IS_IN_MMC 643 #define CONFIG_FSL_FIXED_MMC_LOCATION 644 #define CONFIG_ENV_SIZE 0x2000 645 #define CONFIG_SYS_MMC_ENV_DEV 0 646 #else 647 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 648 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 649 #define CONFIG_ENV_SIZE 0x2000 650 #endif 651 #else 652 #define CONFIG_ENV_IS_IN_FLASH 1 653 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 654 #define CONFIG_ENV_ADDR 0xfff80000 655 #else 656 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 657 #endif 658 #define CONFIG_ENV_SIZE 0x2000 659 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 660 #endif 661 662 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 663 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 664 665 /* 666 * Command line configuration. 667 */ 668 #include <config_cmd_default.h> 669 670 #define CONFIG_CMD_IRQ 671 #define CONFIG_CMD_PING 672 #define CONFIG_CMD_I2C 673 #define CONFIG_CMD_MII 674 #define CONFIG_CMD_ELF 675 #define CONFIG_CMD_IRQ 676 #define CONFIG_CMD_SETEXPR 677 #define CONFIG_CMD_REGINFO 678 679 #if defined(CONFIG_PCI) 680 #define CONFIG_CMD_PCI 681 #define CONFIG_CMD_NET 682 #endif 683 684 #undef CONFIG_WATCHDOG /* watchdog disabled */ 685 686 #define CONFIG_MMC 1 687 688 #ifdef CONFIG_MMC 689 #define CONFIG_FSL_ESDHC 690 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 691 #define CONFIG_CMD_MMC 692 #define CONFIG_GENERIC_MMC 693 #endif 694 695 /* 696 * USB 697 */ 698 #define CONFIG_HAS_FSL_MPH_USB 699 #ifdef CONFIG_HAS_FSL_MPH_USB 700 #define CONFIG_USB_EHCI 701 702 #ifdef CONFIG_USB_EHCI 703 #define CONFIG_CMD_USB 704 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 705 #define CONFIG_USB_EHCI_FSL 706 #define CONFIG_USB_STORAGE 707 #endif 708 #endif 709 710 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 711 #define CONFIG_CMD_EXT2 712 #define CONFIG_CMD_FAT 713 #define CONFIG_DOS_PARTITION 714 #endif 715 716 /* 717 * Miscellaneous configurable options 718 */ 719 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 720 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 721 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 722 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 723 #if defined(CONFIG_CMD_KGDB) 724 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 725 #else 726 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 727 #endif 728 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 729 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 730 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 731 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 732 733 /* 734 * For booting Linux, the board info and command line data 735 * have to be in the first 64 MB of memory, since this is 736 * the maximum mapped by the Linux kernel during initialization. 737 */ 738 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 739 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 740 741 #if defined(CONFIG_CMD_KGDB) 742 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 743 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 744 #endif 745 746 /* 747 * Environment Configuration 748 */ 749 750 /* The mac addresses for all ethernet interface */ 751 #if defined(CONFIG_TSEC_ENET) 752 #define CONFIG_HAS_ETH0 753 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 754 #define CONFIG_HAS_ETH1 755 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 756 #define CONFIG_HAS_ETH2 757 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 758 #define CONFIG_HAS_ETH3 759 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 760 #endif 761 762 #define CONFIG_IPADDR 192.168.1.254 763 764 #define CONFIG_HOSTNAME unknown 765 #define CONFIG_ROOTPATH "/opt/nfsroot" 766 #define CONFIG_BOOTFILE "uImage" 767 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 768 769 #define CONFIG_SERVERIP 192.168.1.1 770 #define CONFIG_GATEWAYIP 192.168.1.1 771 #define CONFIG_NETMASK 255.255.255.0 772 773 /* default location for tftp and bootm */ 774 #define CONFIG_LOADADDR 1000000 775 776 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 777 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 778 779 #define CONFIG_BAUDRATE 115200 780 781 #define CONFIG_EXTRA_ENV_SETTINGS \ 782 "netdev=eth0\0" \ 783 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 784 "tftpflash=tftpboot $loadaddr $uboot; " \ 785 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 786 " +$filesize; " \ 787 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 788 " +$filesize; " \ 789 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 790 " $filesize; " \ 791 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 792 " +$filesize; " \ 793 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 794 " $filesize\0" \ 795 "consoledev=ttyS0\0" \ 796 "ramdiskaddr=2000000\0" \ 797 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 798 "fdtaddr=c00000\0" \ 799 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 800 "bdev=sda3\0" \ 801 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 802 803 #define CONFIG_HDBOOT \ 804 "setenv bootargs root=/dev/$bdev rw " \ 805 "console=$consoledev,$baudrate $othbootargs;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr - $fdtaddr" 809 810 #define CONFIG_NFSBOOTCOMMAND \ 811 "setenv bootargs root=/dev/nfs rw " \ 812 "nfsroot=$serverip:$rootpath " \ 813 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 814 "console=$consoledev,$baudrate $othbootargs;" \ 815 "tftp $loadaddr $bootfile;" \ 816 "tftp $fdtaddr $fdtfile;" \ 817 "bootm $loadaddr - $fdtaddr" 818 819 #define CONFIG_RAMBOOTCOMMAND \ 820 "setenv bootargs root=/dev/ram rw " \ 821 "console=$consoledev,$baudrate $othbootargs;" \ 822 "tftp $ramdiskaddr $ramdiskfile;" \ 823 "tftp $loadaddr $bootfile;" \ 824 "tftp $fdtaddr $fdtfile;" \ 825 "bootm $loadaddr $ramdiskaddr $fdtaddr" 826 827 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 828 829 #endif /* __CONFIG_H */ 830