1 /* 2 * Copyright 2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8536 1 35 #define CONFIG_MPC8536DS 1 36 37 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 38 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 39 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 44 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 50 /* 51 * When initializing flash, if we cannot find the manufacturer ID, 52 * assume this is the AMD flash associated with the CDS board. 53 * This allows booting from a promjet. 54 */ 55 #define CONFIG_ASSUME_AMD_FLASH 56 57 #ifndef __ASSEMBLY__ 58 extern unsigned long get_board_sys_clk(unsigned long dummy); 59 extern unsigned long get_board_ddr_clk(unsigned long dummy); 60 #endif 61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 62 /* #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /\* ddrclk for MPC85xx *\/ FIXME-8536*/ 63 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 64 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 65 from ICS307 instead of switches */ 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_L2_CACHE /* toggle L2 cache */ 71 #define CONFIG_BTB /* toggle branch predition */ 72 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 73 74 #define CONFIG_ENABLE_36BIT_PHYS 1 75 76 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ 77 #define CFG_MEMTEST_END 0x7fffffff 78 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 86 #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 87 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 88 89 #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) 90 #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 91 #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 92 #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) 93 94 /* DDR Setup */ 95 #define CONFIG_FSL_DDR2 96 #undef CONFIG_FSL_DDR_INTERACTIVE 97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 98 #define CONFIG_DDR_SPD 99 #undef CONFIG_DDR_DLL 100 101 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 102 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 103 104 #define CFG_DDR_SDRAM_BASE 0x00000000 105 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 106 107 #define CONFIG_NUM_DDR_CONTROLLERS 1 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 #define CFG_SPD_BUS_NUM 1 114 115 /* These are used when DDR doesn't use SPD. */ 116 #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 117 #define CFG_DDR_CS0_BNDS 0x0000001F 118 #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 119 #define CFG_DDR_TIMING_3 0x00000000 120 #define CFG_DDR_TIMING_0 0x00260802 121 #define CFG_DDR_TIMING_1 0x3935d322 122 #define CFG_DDR_TIMING_2 0x14904cc8 123 #define CFG_DDR_MODE_1 0x00480432 124 #define CFG_DDR_MODE_2 0x00000000 125 #define CFG_DDR_INTERVAL 0x06180100 126 #define CFG_DDR_DATA_INIT 0xdeadbeef 127 #define CFG_DDR_CLK_CTRL 0x03800000 128 #define CFG_DDR_OCD_CTRL 0x00000000 129 #define CFG_DDR_OCD_STATUS 0x00000000 130 #define CFG_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 131 #define CFG_DDR_CONTROL2 0x04400010 132 133 #define CFG_DDR_ERR_INT_EN 0x0000000d 134 #define CFG_DDR_ERR_DIS 0x00000000 135 #define CFG_DDR_SBE 0x00010000 136 137 /* FIXME: Not used in fixed_sdram function */ 138 #define CFG_DDR_MODE 0x00000022 139 #define CFG_DDR_CS1_BNDS 0x00000000 140 #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 141 #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 142 #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 143 #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 144 145 /* Make sure required options are set */ 146 #ifndef CONFIG_SPD_EEPROM 147 #error ("CONFIG_SPD_EEPROM is required") 148 #endif 149 150 #undef CONFIG_CLOCKS_IN_MHZ 151 152 153 /* 154 * Memory map -- xxx -this is wrong, needs updating 155 * 156 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 157 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 158 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 159 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 160 * 161 * Localbus cacheable (TBD) 162 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 163 * 164 * Localbus non-cacheable 165 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 166 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 167 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 168 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 169 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 170 */ 171 172 /* 173 * Local Bus Definitions 174 */ 175 #define CFG_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 176 177 #define CFG_BR0_PRELIM 0xe8001001 178 #define CFG_OR0_PRELIM 0xf8000ff7 179 180 #define CFG_BR1_PRELIM 0xe0001001 181 #define CFG_OR1_PRELIM 0xf8000ff7 182 183 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE} 184 #define CFG_FLASH_QUIET_TEST 185 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 186 187 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 188 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ 189 #undef CFG_FLASH_CHECKSUM 190 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 193 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 194 195 #define CONFIG_FLASH_CFI_DRIVER 196 #define CFG_FLASH_CFI 197 #define CFG_FLASH_EMPTY_INFO 198 #define CFG_FLASH_AMD_CHECK_DQ7 199 200 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 201 202 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 203 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 204 205 #define CFG_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ 206 #define CFG_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 207 208 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 209 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 210 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 211 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 212 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 213 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 214 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 215 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 216 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 217 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 218 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 219 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 220 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 221 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 222 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 223 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 224 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 225 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 226 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 227 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 228 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 229 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 230 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 231 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 232 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 233 #define PIXIS_LED 0x25 /* LED Register */ 234 235 /* old pixis referenced names */ 236 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 237 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 238 #define CFG_PIXIS_VBOOT_MASK 0xc0 239 240 /* define to use L1 as initial stack */ 241 #define CONFIG_L1_INIT_RAM 242 #define CFG_INIT_RAM_LOCK 1 243 #define CFG_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 244 #define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 245 246 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 247 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 248 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 249 250 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 251 #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 252 253 /* Serial Port - controlled on board with jumper J8 254 * open - index 2 255 * shorted - index 1 256 */ 257 #define CONFIG_CONS_INDEX 1 258 #undef CONFIG_SERIAL_SOFTWARE_FIFO 259 #define CFG_NS16550 260 #define CFG_NS16550_SERIAL 261 #define CFG_NS16550_REG_SIZE 1 262 #define CFG_NS16550_CLK get_bus_freq(0) 263 264 #define CFG_BAUDRATE_TABLE \ 265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 266 267 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 268 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 269 270 /* Use the HUSH parser */ 271 #define CFG_HUSH_PARSER 272 #ifdef CFG_HUSH_PARSER 273 #define CFG_PROMPT_HUSH_PS2 "> " 274 #endif 275 276 /* 277 * Pass open firmware flat tree 278 */ 279 #define CONFIG_OF_LIBFDT 1 280 #define CONFIG_OF_BOARD_SETUP 1 281 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 282 283 #define CFG_64BIT_STRTOUL 1 284 #define CFG_64BIT_VSPRINTF 1 285 286 287 /* 288 * I2C 289 */ 290 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 291 #define CONFIG_HARD_I2C /* I2C with hardware support */ 292 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 293 #define CONFIG_I2C_MULTI_BUS 294 #define CONFIG_I2C_CMD_TREE 295 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 296 #define CFG_I2C_SLAVE 0x7F 297 #define CFG_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 298 #define CFG_I2C_OFFSET 0x3000 299 #define CFG_I2C2_OFFSET 0x3100 300 301 /* 302 * I2C2 EEPROM 303 */ 304 #define CFG_ID_EEPROM 305 #ifdef CFG_ID_EEPROM 306 #define CONFIG_ID_EEPROM 307 #define CFG_I2C_EEPROM_NXID 308 #endif 309 #define CFG_I2C_EEPROM_ADDR 0x57 310 #define CFG_I2C_EEPROM_ADDR_LEN 1 311 #define CFG_EEPROM_BUS_NUM 1 312 313 /* 314 * General PCI 315 * Memory space is mapped 1-1, but I/O space must start from 0. 316 */ 317 318 /* PCI view of System Memory */ 319 #define CFG_PCI_MEMORY_BUS 0x00000000 320 #define CFG_PCI_MEMORY_PHYS 0x00000000 321 #define CFG_PCI_MEMORY_SIZE 0x80000000 322 323 #define CFG_PCI1_MEM_BASE 0x80000000 324 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 325 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 326 #define CFG_PCI1_IO_BASE 0x00000000 327 #define CFG_PCI1_IO_PHYS 0xffc00000 328 #define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */ 329 330 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 331 #define CFG_PCIE1_MEM_BASE 0x90000000 332 #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 333 #define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 334 #define CFG_PCIE1_IO_BASE 0x00000000 335 #define CFG_PCIE1_IO_PHYS 0xffc10000 336 #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ 337 338 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 339 #define CFG_PCIE2_MEM_BASE 0x98000000 340 #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 341 #define CFG_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 342 #define CFG_PCIE2_IO_BASE 0x00000000 343 #define CFG_PCIE2_IO_PHYS 0xffc20000 344 #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ 345 346 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 347 #define CFG_PCIE3_MEM_BASE 0xa0000000 348 #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE 349 #define CFG_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 350 #define CFG_PCIE3_IO_BASE 0x00000000 351 #define CFG_PCIE3_IO_PHYS 0xffc30000 352 #define CFG_PCIE3_IO_SIZE 0x00010000 /* 64k */ 353 354 #if defined(CONFIG_PCI) 355 356 #define CONFIG_NET_MULTI 357 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 358 359 /*PCIE video card used*/ 360 #define VIDEO_IO_OFFSET CFG_PCIE3_IO_PHYS 361 362 /*PCI video card used*/ 363 /*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ 364 365 /* video */ 366 #define CONFIG_VIDEO 367 368 #if defined(CONFIG_VIDEO) 369 #define CONFIG_BIOSEMU 370 #define CONFIG_CFB_CONSOLE 371 #define CONFIG_VIDEO_SW_CURSOR 372 #define CONFIG_VGA_AS_SINGLE_DEVICE 373 #define CONFIG_ATI_RADEON_FB 374 #define CONFIG_VIDEO_LOGO 375 /*#define CONFIG_CONSOLE_CURSOR*/ 376 #define CFG_ISA_IO_BASE_ADDRESS CFG_PCIE3_IO_PHYS 377 #endif 378 379 #undef CONFIG_EEPRO100 380 #undef CONFIG_TULIP 381 #undef CONFIG_RTL8139 382 383 #ifdef CONFIG_RTL8139 384 /* This macro is used by RTL8139 but not defined in PPC architecture */ 385 #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) 386 #define _IO_BASE 0x00000000 387 #endif 388 389 #ifndef CONFIG_PCI_PNP 390 #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE 391 #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE 392 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 393 #endif 394 395 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 396 397 #endif /* CONFIG_PCI */ 398 399 /* SATA */ 400 #define CONFIG_LIBATA 401 #define CONFIG_FSL_SATA 402 403 #define CFG_SATA_MAX_DEVICE 2 404 #define CONFIG_SATA1 405 #define CFG_SATA1 CFG_MPC85xx_SATA1_ADDR 406 #define CFG_SATA1_FLAGS FLAGS_DMA 407 #define CONFIG_SATA2 408 #define CFG_SATA2 CFG_MPC85xx_SATA2_ADDR 409 #define CFG_SATA2_FLAGS FLAGS_DMA 410 411 #ifdef CONFIG_FSL_SATA 412 #define CONFIG_LBA48 413 #define CONFIG_CMD_SATA 414 #define CONFIG_DOS_PARTITION 415 #define CONFIG_CMD_EXT2 416 #endif 417 418 #if defined(CONFIG_TSEC_ENET) 419 420 #ifndef CONFIG_NET_MULTI 421 #define CONFIG_NET_MULTI 1 422 #endif 423 424 #define CONFIG_MII 1 /* MII PHY management */ 425 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 426 #define CONFIG_TSEC1 1 427 #define CONFIG_TSEC1_NAME "eTSEC1" 428 #define CONFIG_TSEC3 1 429 #define CONFIG_TSEC3_NAME "eTSEC3" 430 431 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 432 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 433 434 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 435 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 436 437 #define TSEC1_PHYIDX 0 438 #define TSEC3_PHYIDX 0 439 440 #define CONFIG_ETHPRIME "eTSEC1" 441 442 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 443 444 #endif /* CONFIG_TSEC_ENET */ 445 446 /* 447 * Environment 448 */ 449 #define CFG_ENV_IS_IN_FLASH 1 450 #if CFG_MONITOR_BASE > 0xfff80000 451 #define CFG_ENV_ADDR 0xfff80000 452 #else 453 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) 454 #endif 455 #define CFG_ENV_SIZE 0x2000 456 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 457 458 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 459 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 460 461 /* 462 * Command line configuration. 463 */ 464 #include <config_cmd_default.h> 465 466 #define CONFIG_CMD_IRQ 467 #define CONFIG_CMD_PING 468 #define CONFIG_CMD_I2C 469 #define CONFIG_CMD_MII 470 #define CONFIG_CMD_ELF 471 472 #if defined(CONFIG_PCI) 473 #define CONFIG_CMD_PCI 474 #define CONFIG_CMD_BEDBUG 475 #define CONFIG_CMD_NET 476 #endif 477 478 #undef CONFIG_WATCHDOG /* watchdog disabled */ 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CFG_LONGHELP /* undef to save memory */ 484 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 485 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 486 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 487 #if defined(CONFIG_CMD_KGDB) 488 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 489 #else 490 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 491 #endif 492 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 493 #define CFG_MAXARGS 16 /* max number of command args */ 494 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 495 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 496 497 /* 498 * For booting Linux, the board info and command line data 499 * have to be in the first 8 MB of memory, since this is 500 * the maximum mapped by the Linux kernel during initialization. 501 */ 502 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 503 504 /* 505 * Internal Definitions 506 * 507 * Boot Flags 508 */ 509 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 510 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 511 512 #if defined(CONFIG_CMD_KGDB) 513 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 514 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 515 #endif 516 517 /* 518 * Environment Configuration 519 */ 520 521 /* The mac addresses for all ethernet interface */ 522 #if defined(CONFIG_TSEC_ENET) 523 #define CONFIG_HAS_ETH0 524 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 525 #define CONFIG_HAS_ETH1 526 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 527 #define CONFIG_HAS_ETH2 528 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 529 #define CONFIG_HAS_ETH3 530 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 531 #endif 532 533 #define CONFIG_IPADDR 192.168.1.254 534 535 #define CONFIG_HOSTNAME unknown 536 #define CONFIG_ROOTPATH /opt/nfsroot 537 #define CONFIG_BOOTFILE uImage 538 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 539 540 #define CONFIG_SERVERIP 192.168.1.1 541 #define CONFIG_GATEWAYIP 192.168.1.1 542 #define CONFIG_NETMASK 255.255.255.0 543 544 /* default location for tftp and bootm */ 545 #define CONFIG_LOADADDR 1000000 546 547 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 548 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 549 550 #define CONFIG_BAUDRATE 115200 551 552 #define CONFIG_EXTRA_ENV_SETTINGS \ 553 "netdev=eth0\0" \ 554 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 555 "tftpflash=tftpboot $loadaddr $uboot; " \ 556 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 557 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 558 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 559 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 560 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 561 "consoledev=ttyS0\0" \ 562 "ramdiskaddr=2000000\0" \ 563 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 564 "fdtaddr=c00000\0" \ 565 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 566 "bdev=sda3\0" 567 568 #define CONFIG_HDBOOT \ 569 "setenv bootargs root=/dev/$bdev rw " \ 570 "console=$consoledev,$baudrate $othbootargs;" \ 571 "tftp $loadaddr $bootfile;" \ 572 "tftp $fdtaddr $fdtfile;" \ 573 "bootm $loadaddr - $fdtaddr" 574 575 #define CONFIG_NFSBOOTCOMMAND \ 576 "setenv bootargs root=/dev/nfs rw " \ 577 "nfsroot=$serverip:$rootpath " \ 578 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 579 "console=$consoledev,$baudrate $othbootargs;" \ 580 "tftp $loadaddr $bootfile;" \ 581 "tftp $fdtaddr $fdtfile;" \ 582 "bootm $loadaddr - $fdtaddr" 583 584 #define CONFIG_RAMBOOTCOMMAND \ 585 "setenv bootargs root=/dev/ram rw " \ 586 "console=$consoledev,$baudrate $othbootargs;" \ 587 "tftp $ramdiskaddr $ramdiskfile;" \ 588 "tftp $loadaddr $bootfile;" \ 589 "tftp $fdtaddr $fdtfile;" \ 590 "bootm $loadaddr $ramdiskaddr $fdtaddr" 591 592 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 593 594 #endif /* __CONFIG_H */ 595