1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 19 #endif 20 21 #ifdef CONFIG_SPIFLASH 22 #define CONFIG_RAMBOOT_SPIFLASH 1 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 24 #endif 25 26 #ifndef CONFIG_RESET_VECTOR_ADDRESS 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 28 #endif 29 30 #ifndef CONFIG_SYS_MONITOR_BASE 31 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 32 #endif 33 34 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 35 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 36 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 37 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 38 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 39 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 40 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 41 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 42 43 44 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 45 #define CONFIG_ENV_OVERWRITE 46 47 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 48 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 49 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 50 51 /* 52 * These can be toggled for performance analysis, otherwise use default. 53 */ 54 #define CONFIG_L2_CACHE /* toggle L2 cache */ 55 #define CONFIG_BTB /* toggle branch predition */ 56 57 #define CONFIG_ENABLE_36BIT_PHYS 1 58 59 #ifdef CONFIG_PHYS_64BIT 60 #define CONFIG_ADDR_MAP 1 61 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 62 #endif 63 64 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 65 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 66 67 /* 68 * Config the L2 Cache as L2 SRAM 69 */ 70 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 71 #ifdef CONFIG_PHYS_64BIT 72 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 73 #else 74 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 75 #endif 76 #define CONFIG_SYS_L2_SIZE (512 << 10) 77 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 78 79 #define CONFIG_SYS_CCSRBAR 0xffe00000 80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 81 82 #if defined(CONFIG_NAND_SPL) 83 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 84 #endif 85 86 /* DDR Setup */ 87 #define CONFIG_VERY_BIG_RAM 88 #undef CONFIG_FSL_DDR_INTERACTIVE 89 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 90 #define CONFIG_DDR_SPD 91 92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 93 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 94 95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 97 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 100 101 /* I2C addresses of SPD EEPROMs */ 102 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 103 #define CONFIG_SYS_SPD_BUS_NUM 1 104 105 /* These are used when DDR doesn't use SPD. */ 106 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 108 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 109 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 110 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 111 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 112 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 113 #define CONFIG_SYS_DDR_MODE_1 0x00480432 114 #define CONFIG_SYS_DDR_MODE_2 0x00000000 115 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 116 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 117 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 118 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 119 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 120 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 121 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 122 123 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 124 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 125 #define CONFIG_SYS_DDR_SBE 0x00010000 126 127 /* Make sure required options are set */ 128 #ifndef CONFIG_SPD_EEPROM 129 #error ("CONFIG_SPD_EEPROM is required") 130 #endif 131 132 #undef CONFIG_CLOCKS_IN_MHZ 133 134 /* 135 * Memory map -- xxx -this is wrong, needs updating 136 * 137 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 138 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 139 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 140 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 141 * 142 * Localbus cacheable (TBD) 143 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 144 * 145 * Localbus non-cacheable 146 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 147 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 148 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 149 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 150 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 151 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 152 */ 153 154 /* 155 * Local Bus Definitions 156 */ 157 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 158 #ifdef CONFIG_PHYS_64BIT 159 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 160 #else 161 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 162 #endif 163 164 #define CONFIG_FLASH_BR_PRELIM \ 165 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 166 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 167 168 #define CONFIG_SYS_BR1_PRELIM \ 169 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 170 | BR_PS_16 | BR_V) 171 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 172 173 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 174 CONFIG_SYS_FLASH_BASE_PHYS } 175 #define CONFIG_SYS_FLASH_QUIET_TEST 176 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 177 178 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 179 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 180 #undef CONFIG_SYS_FLASH_CHECKSUM 181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 183 184 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 185 #define CONFIG_SYS_RAMBOOT 186 #define CONFIG_SYS_EXTRA_ENV_RELOC 187 #else 188 #undef CONFIG_SYS_RAMBOOT 189 #endif 190 191 #define CONFIG_FLASH_CFI_DRIVER 192 #define CONFIG_SYS_FLASH_CFI 193 #define CONFIG_SYS_FLASH_EMPTY_INFO 194 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 195 196 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 197 198 #define CONFIG_HWCONFIG /* enable hwconfig */ 199 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 200 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 201 #ifdef CONFIG_PHYS_64BIT 202 #define PIXIS_BASE_PHYS 0xfffdf0000ull 203 #else 204 #define PIXIS_BASE_PHYS PIXIS_BASE 205 #endif 206 207 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 208 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 209 210 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 211 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 212 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 213 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 214 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 215 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 216 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 217 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 218 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 219 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 220 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 221 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 222 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 223 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 224 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 225 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 226 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 227 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 228 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 229 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 230 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 231 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 232 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 233 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 234 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 235 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 236 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 237 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 238 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 239 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 240 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 241 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 242 #define PIXIS_LED 0x25 /* LED Register */ 243 244 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 245 246 /* old pixis referenced names */ 247 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 248 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 249 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 250 251 #define CONFIG_SYS_INIT_RAM_LOCK 1 252 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 253 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 254 255 #define CONFIG_SYS_GBL_DATA_OFFSET \ 256 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 257 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 258 259 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 260 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 261 262 #ifndef CONFIG_NAND_SPL 263 #define CONFIG_SYS_NAND_BASE 0xffa00000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 266 #else 267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 268 #endif 269 #else 270 #define CONFIG_SYS_NAND_BASE 0xfff00000 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 273 #else 274 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 275 #endif 276 #endif 277 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 278 CONFIG_SYS_NAND_BASE + 0x40000, \ 279 CONFIG_SYS_NAND_BASE + 0x80000, \ 280 CONFIG_SYS_NAND_BASE + 0xC0000} 281 #define CONFIG_SYS_MAX_NAND_DEVICE 4 282 #define CONFIG_NAND_FSL_ELBC 1 283 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 284 285 /* NAND boot: 4K NAND loader config */ 286 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 287 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 288 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 289 #define CONFIG_SYS_NAND_U_BOOT_START \ 290 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 291 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 292 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 293 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 294 295 /* NAND flash config */ 296 #define CONFIG_SYS_NAND_BR_PRELIM \ 297 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 298 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 299 | BR_PS_8 /* Port Size = 8 bit */ \ 300 | BR_MS_FCM /* MSEL = FCM */ \ 301 | BR_V) /* valid */ 302 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 303 | OR_FCM_PGS /* Large Page*/ \ 304 | OR_FCM_CSCT \ 305 | OR_FCM_CST \ 306 | OR_FCM_CHT \ 307 | OR_FCM_SCY_1 \ 308 | OR_FCM_TRLX \ 309 | OR_FCM_EHTR) 310 311 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 312 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 313 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 314 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 315 316 #define CONFIG_SYS_BR4_PRELIM \ 317 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 318 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 319 | BR_PS_8 /* Port Size = 8 bit */ \ 320 | BR_MS_FCM /* MSEL = FCM */ \ 321 | BR_V) /* valid */ 322 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 323 #define CONFIG_SYS_BR5_PRELIM \ 324 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 325 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 326 | BR_PS_8 /* Port Size = 8 bit */ \ 327 | BR_MS_FCM /* MSEL = FCM */ \ 328 | BR_V) /* valid */ 329 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 330 331 #define CONFIG_SYS_BR6_PRELIM \ 332 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 333 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 334 | BR_PS_8 /* Port Size = 8 bit */ \ 335 | BR_MS_FCM /* MSEL = FCM */ \ 336 | BR_V) /* valid */ 337 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 338 339 /* Serial Port - controlled on board with jumper J8 340 * open - index 2 341 * shorted - index 1 342 */ 343 #define CONFIG_CONS_INDEX 1 344 #define CONFIG_SYS_NS16550_SERIAL 345 #define CONFIG_SYS_NS16550_REG_SIZE 1 346 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 347 #ifdef CONFIG_NAND_SPL 348 #define CONFIG_NS16550_MIN_FUNCTIONS 349 #endif 350 351 #define CONFIG_SYS_BAUDRATE_TABLE \ 352 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 353 354 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 355 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 356 357 /* 358 * I2C 359 */ 360 #define CONFIG_SYS_I2C 361 #define CONFIG_SYS_I2C_FSL 362 #define CONFIG_SYS_FSL_I2C_SPEED 400000 363 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 364 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 365 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 366 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 367 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 368 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 369 370 /* 371 * I2C2 EEPROM 372 */ 373 #define CONFIG_ID_EEPROM 374 #ifdef CONFIG_ID_EEPROM 375 #define CONFIG_SYS_I2C_EEPROM_NXID 376 #endif 377 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 378 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 379 #define CONFIG_SYS_EEPROM_BUS_NUM 1 380 381 /* 382 * eSPI - Enhanced SPI 383 */ 384 #define CONFIG_HARD_SPI 385 386 #if defined(CONFIG_SPI_FLASH) 387 #define CONFIG_SF_DEFAULT_SPEED 10000000 388 #define CONFIG_SF_DEFAULT_MODE 0 389 #endif 390 391 /* 392 * General PCI 393 * Memory space is mapped 1-1, but I/O space must start from 0. 394 */ 395 396 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 399 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 400 #else 401 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 402 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 403 #endif 404 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 405 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 406 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 409 #else 410 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 411 #endif 412 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 413 414 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 415 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 416 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 419 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 420 #else 421 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 422 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 423 #endif 424 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 425 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 426 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 427 #ifdef CONFIG_PHYS_64BIT 428 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 429 #else 430 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 431 #endif 432 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 433 434 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 435 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 436 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 437 #ifdef CONFIG_PHYS_64BIT 438 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 439 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 440 #else 441 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 442 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 443 #endif 444 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 445 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 446 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 447 #ifdef CONFIG_PHYS_64BIT 448 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 449 #else 450 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 451 #endif 452 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 453 454 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 455 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 456 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 457 #ifdef CONFIG_PHYS_64BIT 458 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 459 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 460 #else 461 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 462 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 463 #endif 464 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 465 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 466 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 467 #ifdef CONFIG_PHYS_64BIT 468 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 469 #else 470 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 471 #endif 472 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 473 474 #if defined(CONFIG_PCI) 475 /*PCIE video card used*/ 476 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 477 478 /*PCI video card used*/ 479 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 480 481 /* video */ 482 483 #if defined(CONFIG_VIDEO) 484 #define CONFIG_BIOSEMU 485 #define CONFIG_ATI_RADEON_FB 486 #define CONFIG_VIDEO_LOGO 487 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 488 #endif 489 490 #undef CONFIG_EEPRO100 491 #undef CONFIG_TULIP 492 493 #ifndef CONFIG_PCI_PNP 494 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 495 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 496 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 497 #endif 498 499 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 500 501 #endif /* CONFIG_PCI */ 502 503 /* SATA */ 504 #define CONFIG_SYS_SATA_MAX_DEVICE 2 505 #define CONFIG_SATA1 506 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 507 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 508 #define CONFIG_SATA2 509 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 510 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 511 512 #ifdef CONFIG_FSL_SATA 513 #define CONFIG_LBA48 514 #endif 515 516 #if defined(CONFIG_TSEC_ENET) 517 518 #define CONFIG_MII 1 /* MII PHY management */ 519 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 520 #define CONFIG_TSEC1 1 521 #define CONFIG_TSEC1_NAME "eTSEC1" 522 #define CONFIG_TSEC3 1 523 #define CONFIG_TSEC3_NAME "eTSEC3" 524 525 #define CONFIG_FSL_SGMII_RISER 1 526 #define SGMII_RISER_PHY_OFFSET 0x1c 527 528 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 529 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 530 531 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 532 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 533 534 #define TSEC1_PHYIDX 0 535 #define TSEC3_PHYIDX 0 536 537 #define CONFIG_ETHPRIME "eTSEC1" 538 539 #endif /* CONFIG_TSEC_ENET */ 540 541 /* 542 * Environment 543 */ 544 545 #if defined(CONFIG_SYS_RAMBOOT) 546 #if defined(CONFIG_RAMBOOT_SPIFLASH) 547 #define CONFIG_ENV_SPI_BUS 0 548 #define CONFIG_ENV_SPI_CS 0 549 #define CONFIG_ENV_SPI_MAX_HZ 10000000 550 #define CONFIG_ENV_SPI_MODE 0 551 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 552 #define CONFIG_ENV_OFFSET 0xF0000 553 #define CONFIG_ENV_SECT_SIZE 0x10000 554 #elif defined(CONFIG_RAMBOOT_SDCARD) 555 #define CONFIG_FSL_FIXED_MMC_LOCATION 556 #define CONFIG_ENV_SIZE 0x2000 557 #define CONFIG_SYS_MMC_ENV_DEV 0 558 #else 559 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 560 #define CONFIG_ENV_SIZE 0x2000 561 #endif 562 #else 563 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 564 #define CONFIG_ENV_SIZE 0x2000 565 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 566 #endif 567 568 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 569 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 570 571 #undef CONFIG_WATCHDOG /* watchdog disabled */ 572 573 #ifdef CONFIG_MMC 574 #define CONFIG_FSL_ESDHC 575 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 576 #endif 577 578 /* 579 * USB 580 */ 581 #define CONFIG_HAS_FSL_MPH_USB 582 #ifdef CONFIG_HAS_FSL_MPH_USB 583 #ifdef CONFIG_USB_EHCI_HCD 584 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 585 #define CONFIG_USB_EHCI_FSL 586 #endif 587 #endif 588 589 /* 590 * Miscellaneous configurable options 591 */ 592 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 593 594 /* 595 * For booting Linux, the board info and command line data 596 * have to be in the first 64 MB of memory, since this is 597 * the maximum mapped by the Linux kernel during initialization. 598 */ 599 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 600 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 601 602 #if defined(CONFIG_CMD_KGDB) 603 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 604 #endif 605 606 /* 607 * Environment Configuration 608 */ 609 610 /* The mac addresses for all ethernet interface */ 611 #if defined(CONFIG_TSEC_ENET) 612 #define CONFIG_HAS_ETH0 613 #define CONFIG_HAS_ETH1 614 #define CONFIG_HAS_ETH2 615 #define CONFIG_HAS_ETH3 616 #endif 617 618 #define CONFIG_IPADDR 192.168.1.254 619 620 #define CONFIG_HOSTNAME unknown 621 #define CONFIG_ROOTPATH "/opt/nfsroot" 622 #define CONFIG_BOOTFILE "uImage" 623 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 624 625 #define CONFIG_SERVERIP 192.168.1.1 626 #define CONFIG_GATEWAYIP 192.168.1.1 627 #define CONFIG_NETMASK 255.255.255.0 628 629 /* default location for tftp and bootm */ 630 #define CONFIG_LOADADDR 1000000 631 632 #define CONFIG_EXTRA_ENV_SETTINGS \ 633 "netdev=eth0\0" \ 634 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 635 "tftpflash=tftpboot $loadaddr $uboot; " \ 636 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 637 " +$filesize; " \ 638 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 639 " +$filesize; " \ 640 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 641 " $filesize; " \ 642 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 643 " +$filesize; " \ 644 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 645 " $filesize\0" \ 646 "consoledev=ttyS0\0" \ 647 "ramdiskaddr=2000000\0" \ 648 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 649 "fdtaddr=1e00000\0" \ 650 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 651 "bdev=sda3\0" \ 652 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 653 654 #define CONFIG_HDBOOT \ 655 "setenv bootargs root=/dev/$bdev rw " \ 656 "console=$consoledev,$baudrate $othbootargs;" \ 657 "tftp $loadaddr $bootfile;" \ 658 "tftp $fdtaddr $fdtfile;" \ 659 "bootm $loadaddr - $fdtaddr" 660 661 #define CONFIG_NFSBOOTCOMMAND \ 662 "setenv bootargs root=/dev/nfs rw " \ 663 "nfsroot=$serverip:$rootpath " \ 664 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 665 "console=$consoledev,$baudrate $othbootargs;" \ 666 "tftp $loadaddr $bootfile;" \ 667 "tftp $fdtaddr $fdtfile;" \ 668 "bootm $loadaddr - $fdtaddr" 669 670 #define CONFIG_RAMBOOTCOMMAND \ 671 "setenv bootargs root=/dev/ram rw " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $ramdiskaddr $ramdiskfile;" \ 674 "tftp $loadaddr $bootfile;" \ 675 "tftp $fdtaddr $fdtfile;" \ 676 "bootm $loadaddr $ramdiskaddr $fdtaddr" 677 678 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 679 680 #endif /* __CONFIG_H */ 681