xref: /openbmc/u-boot/include/configs/MPC8536DS.h (revision a380279b)
1 /*
2  * Copyright 2008-2009 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * mpc8536ds board configuration file
25  *
26  */
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29 
30 #ifdef CONFIG_MK_36BIT
31 #define CONFIG_PHYS_64BIT	1
32 #endif
33 
34 #ifdef CONFIG_MK_NAND
35 #define CONFIG_NAND_U_BOOT		1
36 #define CONFIG_RAMBOOT_NAND		1
37 #define CONFIG_RAMBOOT_TEXT_BASE	0xf8f82000
38 #endif
39 
40 #ifdef CONFIG_MK_SDCARD
41 #define CONFIG_RAMBOOT_SDCARD		1
42 #define CONFIG_RAMBOOT_TEXT_BASE	0xf8f80000
43 #endif
44 
45 #ifdef CONFIG_MK_SPIFLASH
46 #define CONFIG_RAMBOOT_SPIFLASH		1
47 #define CONFIG_RAMBOOT_TEXT_BASE	0xf8f80000
48 #endif
49 
50 /* High Level Configuration Options */
51 #define CONFIG_BOOKE		1	/* BOOKE */
52 #define CONFIG_E500		1	/* BOOKE e500 family */
53 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
54 #define CONFIG_MPC8536		1
55 #define CONFIG_MPC8536DS	1
56 
57 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
58 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
59 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
60 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
61 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
62 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
63 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
64 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
65 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
66 
67 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
68 #define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
69 
70 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
71 #define CONFIG_ENV_OVERWRITE
72 
73 /*
74  * When initializing flash, if we cannot find the manufacturer ID,
75  * assume this is the AMD flash associated with the CDS board.
76  * This allows booting from a promjet.
77  */
78 #define CONFIG_ASSUME_AMD_FLASH
79 
80 #ifndef __ASSEMBLY__
81 extern unsigned long get_board_sys_clk(unsigned long dummy);
82 extern unsigned long get_board_ddr_clk(unsigned long dummy);
83 #endif
84 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
85 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0)
86 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
87 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
88 					     from ICS307 instead of switches */
89 
90 /*
91  * These can be toggled for performance analysis, otherwise use default.
92  */
93 #define CONFIG_L2_CACHE			/* toggle L2 cache */
94 #define CONFIG_BTB			/* toggle branch predition */
95 
96 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
97 
98 #define CONFIG_ENABLE_36BIT_PHYS	1
99 
100 #ifdef CONFIG_PHYS_64BIT
101 #define CONFIG_ADDR_MAP			1
102 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
103 #endif
104 
105 #define CONFIG_SYS_MEMTEST_START 0x00010000	/* skip exception vectors */
106 #define CONFIG_SYS_MEMTEST_END   0x1f000000	/* skip u-boot at top of RAM */
107 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
108 
109 /*
110  * Config the L2 Cache as L2 SRAM
111  */
112 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
113 #ifdef CONFIG_PHYS_64BIT
114 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
115 #else
116 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
117 #endif
118 #define CONFIG_SYS_L2_SIZE		(512 << 10)
119 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
120 
121 /*
122  * Base addresses -- Note these are effective addresses where the
123  * actual resources get mapped (not physical addresses)
124  */
125 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_SYS_CCSRBAR_PHYS	0xfffe00000ull /* physical addr of CCSRBAR */
128 #else
129 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
130 #endif
131 #define CONFIG_SYS_IMMR	CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
132 
133 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
134 #define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
135 #else
136 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
137 #endif
138 
139 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR + 0x8000)
140 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR + 0xa000)
141 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR + 0x9000)
142 #define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR + 0xb000)
143 
144 /* DDR Setup */
145 #define CONFIG_VERY_BIG_RAM
146 #define CONFIG_FSL_DDR2
147 #undef CONFIG_FSL_DDR_INTERACTIVE
148 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
149 #define CONFIG_DDR_SPD
150 #undef CONFIG_DDR_DLL
151 
152 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
153 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
154 
155 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
156 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
157 
158 #define CONFIG_NUM_DDR_CONTROLLERS	1
159 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
160 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
161 
162 /* I2C addresses of SPD EEPROMs */
163 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
164 #define CONFIG_SYS_SPD_BUS_NUM		1
165 
166 /* These are used when DDR doesn't use SPD. */
167 #define CONFIG_SYS_SDRAM_SIZE		256	/* DDR is 256MB */
168 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
169 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102 /* Enable, no interleaving */
170 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
171 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
172 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
173 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
174 #define CONFIG_SYS_DDR_MODE_1		0x00480432
175 #define CONFIG_SYS_DDR_MODE_2		0x00000000
176 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
177 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
178 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
179 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
180 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
181 #define CONFIG_SYS_DDR_CONTROL	0xC3008000	/* Type = DDR2 */
182 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
183 
184 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
185 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
186 #define CONFIG_SYS_DDR_SBE		0x00010000
187 
188 /* Make sure required options are set */
189 #ifndef CONFIG_SPD_EEPROM
190 #error ("CONFIG_SPD_EEPROM is required")
191 #endif
192 
193 #undef CONFIG_CLOCKS_IN_MHZ
194 
195 
196 /*
197  * Memory map -- xxx -this is wrong, needs updating
198  *
199  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
200  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
201  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
202  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
203  *
204  * Localbus cacheable (TBD)
205  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
206  *
207  * Localbus non-cacheable
208  * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
209  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
210  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
211  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
212  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
213  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
214  */
215 
216 /*
217  * Local Bus Definitions
218  */
219 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
220 #ifdef CONFIG_PHYS_64BIT
221 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
222 #else
223 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
224 #endif
225 
226 #define CONFIG_FLASH_BR_PRELIM \
227 		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
228 		 | BR_PS_16 | BR_V)
229 #define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
230 
231 #define CONFIG_SYS_BR1_PRELIM \
232 		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
233 		 | BR_PS_16 | BR_V)
234 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
235 
236 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
237 				      CONFIG_SYS_FLASH_BASE_PHYS }
238 #define CONFIG_SYS_FLASH_QUIET_TEST
239 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
240 
241 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
242 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
243 #undef	CONFIG_SYS_FLASH_CHECKSUM
244 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
245 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
246 
247 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
248 
249 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
250 	|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
251 #define CONFIG_SYS_RAMBOOT
252 #else
253 #undef CONFIG_SYS_RAMBOOT
254 #endif
255 
256 #define CONFIG_FLASH_CFI_DRIVER
257 #define CONFIG_SYS_FLASH_CFI
258 #define CONFIG_SYS_FLASH_EMPTY_INFO
259 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
260 
261 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
262 
263 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
264 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
265 #ifdef CONFIG_PHYS_64BIT
266 #define PIXIS_BASE_PHYS	0xfffdf0000ull
267 #else
268 #define PIXIS_BASE_PHYS	PIXIS_BASE
269 #endif
270 
271 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
272 #define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
273 
274 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
275 #define PIXIS_VER		0x1	/* Board version at offset 1 */
276 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
277 #define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
278 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
279 #define PIXIS_PWR		0x5	/* PIXIS Power status register */
280 #define PIXIS_AUX		0x6	/* Auxiliary 1 register */
281 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
282 #define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
283 #define PIXIS_VCTL		0x10	/* VELA Control Register */
284 #define PIXIS_VSTAT		0x11	/* VELA Status Register */
285 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
286 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
287 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
288 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
289 #define PIXIS_VBOOT_LBMAP	0xe0	/* VBOOT - CFG_LBMAP */
290 #define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
291 #define PIXIS_VBOOT_LBMAP_NOR1	0x01	/* cfg_lbmap - boot from NOR 1 */
292 #define PIXIS_VBOOT_LBMAP_NOR2	0x02	/* cfg_lbmap - boot from NOR 2 */
293 #define PIXIS_VBOOT_LBMAP_NOR3	0x03	/* cfg_lbmap - boot from NOR 3 */
294 #define PIXIS_VBOOT_LBMAP_PJET	0x04	/* cfg_lbmap - boot from projet */
295 #define PIXIS_VBOOT_LBMAP_NAND	0x05	/* cfg_lbmap - boot from NAND */
296 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
297 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
298 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
299 #define PIXIS_VSYSCLK0		0x1A	/* VELA SYSCLK0 Register */
300 #define PIXIS_VSYSCLK1		0x1B	/* VELA SYSCLK1 Register */
301 #define PIXIS_VSYSCLK2		0x1C	/* VELA SYSCLK2 Register */
302 #define PIXIS_VDDRCLK0		0x1D	/* VELA DDRCLK0 Register */
303 #define PIXIS_VDDRCLK1		0x1E	/* VELA DDRCLK1 Register */
304 #define PIXIS_VDDRCLK2		0x1F	/* VELA DDRCLK2 Register */
305 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
306 #define PIXIS_LED		0x25    /* LED Register */
307 
308 #define PIXIS_SPD_SYSCLK	0x7	/* SYSCLK option */
309 
310 /* old pixis referenced names */
311 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
312 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
313 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
314 
315 #define CONFIG_SYS_INIT_RAM_LOCK	1
316 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
317 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
318 
319 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
320 #define CONFIG_SYS_GBL_DATA_OFFSET \
321 		(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
322 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
323 
324 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
325 #define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
326 
327 #ifndef CONFIG_NAND_SPL
328 #define CONFIG_SYS_NAND_BASE		0xffa00000
329 #ifdef CONFIG_PHYS_64BIT
330 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
331 #else
332 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
333 #endif
334 #else
335 #define CONFIG_SYS_NAND_BASE		0xfff00000
336 #ifdef CONFIG_PHYS_64BIT
337 #define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
338 #else
339 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
340 #endif
341 #endif
342 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
343 				CONFIG_SYS_NAND_BASE + 0x40000, \
344 				CONFIG_SYS_NAND_BASE + 0x80000, \
345 				CONFIG_SYS_NAND_BASE + 0xC0000}
346 #define CONFIG_SYS_MAX_NAND_DEVICE	4
347 #define CONFIG_MTD_NAND_VERIFY_WRITE
348 #define CONFIG_CMD_NAND		1
349 #define CONFIG_NAND_FSL_ELBC	1
350 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
351 
352 /* NAND boot: 4K NAND loader config */
353 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
354 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
355 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
356 #define CONFIG_SYS_NAND_U_BOOT_START \
357 		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
358 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
359 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
360 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
361 
362 /* NAND flash config */
363 #define CONFIG_NAND_BR_PRELIM \
364 		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
365 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
366 		| BR_PS_8		/* Port Size = 8 bit */ \
367 		| BR_MS_FCM		/* MSEL = FCM */ \
368 		| BR_V)			/* valid */
369 #define CONFIG_NAND_OR_PRELIM	(0xFFFC0000	/* length 256K */ \
370 		| OR_FCM_PGS		/* Large Page*/ \
371 		| OR_FCM_CSCT \
372 		| OR_FCM_CST \
373 		| OR_FCM_CHT \
374 		| OR_FCM_SCY_1 \
375 		| OR_FCM_TRLX \
376 		| OR_FCM_EHTR)
377 
378 #ifdef CONFIG_RAMBOOT_NAND
379 #define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
380 #define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
381 #define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
382 #define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
383 #else
384 #define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
385 #define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
386 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
387 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
388 #endif
389 
390 #define CONFIG_SYS_BR4_PRELIM \
391 		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
392 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
393 		| BR_PS_8		/* Port Size = 8 bit */ \
394 		| BR_MS_FCM		/* MSEL = FCM */ \
395 		| BR_V)			/* valid */
396 #define CONFIG_SYS_OR4_PRELIM	CONFIG_NAND_OR_PRELIM	/* NAND Options */
397 #define CONFIG_SYS_BR5_PRELIM \
398 		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
399 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
400 		| BR_PS_8		/* Port Size = 8 bit */ \
401 		| BR_MS_FCM		/* MSEL = FCM */ \
402 		| BR_V)			/* valid */
403 #define CONFIG_SYS_OR5_PRELIM	CONFIG_NAND_OR_PRELIM	/* NAND Options */
404 
405 #define CONFIG_SYS_BR6_PRELIM \
406 		(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
407 		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
408 		| BR_PS_8		/* Port Size = 8 bit */ \
409 		| BR_MS_FCM		/* MSEL = FCM */ \
410 		| BR_V)			/* valid */
411 #define CONFIG_SYS_OR6_PRELIM	CONFIG_NAND_OR_PRELIM	/* NAND Options */
412 
413 /* Serial Port - controlled on board with jumper J8
414  * open - index 2
415  * shorted - index 1
416  */
417 #define CONFIG_CONS_INDEX	1
418 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
419 #define CONFIG_SYS_NS16550
420 #define CONFIG_SYS_NS16550_SERIAL
421 #define CONFIG_SYS_NS16550_REG_SIZE	1
422 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
423 
424 #define CONFIG_SYS_BAUDRATE_TABLE	\
425 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
426 
427 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
428 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
429 
430 /* Use the HUSH parser */
431 #define CONFIG_SYS_HUSH_PARSER
432 #ifdef	CONFIG_SYS_HUSH_PARSER
433 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
434 #endif
435 
436 /*
437  * Pass open firmware flat tree
438  */
439 #define CONFIG_OF_LIBFDT		1
440 #define CONFIG_OF_BOARD_SETUP		1
441 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
442 
443 #define CONFIG_SYS_64BIT_STRTOUL	1
444 #define CONFIG_SYS_64BIT_VSPRINTF	1
445 
446 
447 /*
448  * I2C
449  */
450 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
451 #define CONFIG_HARD_I2C		/* I2C with hardware support */
452 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
453 #define CONFIG_I2C_MULTI_BUS
454 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
455 #define CONFIG_SYS_I2C_SLAVE		0x7F
456 #define CONFIG_SYS_I2C_NOPROBES	{{0, 0x29}}	/* Don't probe these addrs */
457 #define CONFIG_SYS_I2C_OFFSET		0x3000
458 #define CONFIG_SYS_I2C2_OFFSET		0x3100
459 
460 /*
461  * I2C2 EEPROM
462  */
463 #define CONFIG_ID_EEPROM
464 #ifdef CONFIG_ID_EEPROM
465 #define CONFIG_SYS_I2C_EEPROM_NXID
466 #endif
467 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
468 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
469 #define CONFIG_SYS_EEPROM_BUS_NUM	1
470 
471 /*
472  * General PCI
473  * Memory space is mapped 1-1, but I/O space must start from 0.
474  */
475 
476 #define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
477 #ifdef CONFIG_PHYS_64BIT
478 #define CONFIG_SYS_PCI1_MEM_BUS		0xf0000000
479 #define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
480 #else
481 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
482 #define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
483 #endif
484 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
485 #define CONFIG_SYS_PCI1_IO_VIRT		0xffc00000
486 #define CONFIG_SYS_PCI1_IO_BUS		0x00000000
487 #ifdef CONFIG_PHYS_64BIT
488 #define CONFIG_SYS_PCI1_IO_PHYS		0xfffc00000ull
489 #else
490 #define CONFIG_SYS_PCI1_IO_PHYS		0xffc00000
491 #endif
492 #define CONFIG_SYS_PCI1_IO_SIZE		0x00010000	/* 64k */
493 
494 /* controller 1, Slot 1, tgtid 1, Base address a000 */
495 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
496 #ifdef CONFIG_PHYS_64BIT
497 #define CONFIG_SYS_PCIE1_MEM_BUS	0xf8000000
498 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc10000000ull
499 #else
500 #define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
501 #define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
502 #endif
503 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
504 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
505 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
506 #ifdef CONFIG_PHYS_64BIT
507 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc10000ull
508 #else
509 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
510 #endif
511 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
512 
513 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
514 #define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
515 #ifdef CONFIG_PHYS_64BIT
516 #define CONFIG_SYS_PCIE2_MEM_BUS	0xf8000000
517 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc18000000ull
518 #else
519 #define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
520 #define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
521 #endif
522 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
523 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
524 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
525 #ifdef CONFIG_PHYS_64BIT
526 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc20000ull
527 #else
528 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
529 #endif
530 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
531 
532 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
533 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
534 #ifdef CONFIG_PHYS_64BIT
535 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
536 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
537 #else
538 #define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
539 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
540 #endif
541 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
542 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
543 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
544 #ifdef CONFIG_PHYS_64BIT
545 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc30000ull
546 #else
547 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
548 #endif
549 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
550 
551 #if defined(CONFIG_PCI)
552 
553 #define CONFIG_NET_MULTI
554 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
555 
556 /*PCIE video card used*/
557 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
558 
559 /*PCI video card used*/
560 /*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
561 
562 /* video */
563 #define CONFIG_VIDEO
564 
565 #if defined(CONFIG_VIDEO)
566 #define CONFIG_BIOSEMU
567 #define CONFIG_CFB_CONSOLE
568 #define CONFIG_VIDEO_SW_CURSOR
569 #define CONFIG_VGA_AS_SINGLE_DEVICE
570 #define CONFIG_ATI_RADEON_FB
571 #define CONFIG_VIDEO_LOGO
572 /*#define CONFIG_CONSOLE_CURSOR*/
573 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
574 #endif
575 
576 #undef CONFIG_EEPRO100
577 #undef CONFIG_TULIP
578 #undef CONFIG_RTL8139
579 
580 #ifndef CONFIG_PCI_PNP
581 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
582 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
583 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
584 #endif
585 
586 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
587 
588 #endif	/* CONFIG_PCI */
589 
590 /* SATA */
591 #define CONFIG_LIBATA
592 #define CONFIG_FSL_SATA
593 
594 #define CONFIG_SYS_SATA_MAX_DEVICE	2
595 #define CONFIG_SATA1
596 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
597 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
598 #define CONFIG_SATA2
599 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
600 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
601 
602 #ifdef CONFIG_FSL_SATA
603 #define CONFIG_LBA48
604 #define CONFIG_CMD_SATA
605 #define CONFIG_DOS_PARTITION
606 #define CONFIG_CMD_EXT2
607 #endif
608 
609 #if defined(CONFIG_TSEC_ENET)
610 
611 #ifndef CONFIG_NET_MULTI
612 #define CONFIG_NET_MULTI	1
613 #endif
614 
615 #define CONFIG_MII		1	/* MII PHY management */
616 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
617 #define CONFIG_TSEC1	1
618 #define CONFIG_TSEC1_NAME	"eTSEC1"
619 #define CONFIG_TSEC3	1
620 #define CONFIG_TSEC3_NAME	"eTSEC3"
621 
622 #define CONFIG_FSL_SGMII_RISER	1
623 #define SGMII_RISER_PHY_OFFSET	0x1c
624 
625 #define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
626 #define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
627 
628 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
629 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
630 
631 #define TSEC1_PHYIDX		0
632 #define TSEC3_PHYIDX		0
633 
634 #define CONFIG_ETHPRIME		"eTSEC1"
635 
636 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
637 
638 #endif	/* CONFIG_TSEC_ENET */
639 
640 /*
641  * Environment
642  */
643 
644 #if defined(CONFIG_SYS_RAMBOOT)
645 #if defined(CONFIG_RAMBOOT_NAND)
646 	#define CONFIG_ENV_IS_IN_NAND	1
647 	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
648 	#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
649 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
650 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
651 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
652 	#define CONFIG_ENV_SIZE		0x2000
653 #endif
654 #else
655 	#define CONFIG_ENV_IS_IN_FLASH	1
656 	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
657 	#define CONFIG_ENV_ADDR		0xfff80000
658 	#else
659 	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
660 	#endif
661 	#define CONFIG_ENV_SIZE		0x2000
662 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
663 #endif
664 
665 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
666 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
667 
668 /*
669  * Command line configuration.
670  */
671 #include <config_cmd_default.h>
672 
673 #define CONFIG_CMD_IRQ
674 #define CONFIG_CMD_PING
675 #define CONFIG_CMD_I2C
676 #define CONFIG_CMD_MII
677 #define CONFIG_CMD_ELF
678 #define CONFIG_CMD_IRQ
679 #define CONFIG_CMD_SETEXPR
680 
681 #if defined(CONFIG_PCI)
682 #define CONFIG_CMD_PCI
683 #define CONFIG_CMD_NET
684 #endif
685 
686 #undef CONFIG_WATCHDOG			/* watchdog disabled */
687 
688 #define CONFIG_MMC     1
689 
690 #ifdef CONFIG_MMC
691 #define CONFIG_FSL_ESDHC
692 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
693 #define CONFIG_CMD_MMC
694 #define CONFIG_GENERIC_MMC
695 #define CONFIG_CMD_EXT2
696 #define CONFIG_CMD_FAT
697 #define CONFIG_DOS_PARTITION
698 #endif
699 
700 /*
701  * Miscellaneous configurable options
702  */
703 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
704 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
705 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
706 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
707 #if defined(CONFIG_CMD_KGDB)
708 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
709 #else
710 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
711 #endif
712 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
713 		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
714 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
715 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
716 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
717 
718 /*
719  * For booting Linux, the board info and command line data
720  * have to be in the first 16 MB of memory, since this is
721  * the maximum mapped by the Linux kernel during initialization.
722  */
723 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20) /* Initial Memory map for Linux */
724 
725 /*
726  * Internal Definitions
727  *
728  * Boot Flags
729  */
730 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
731 #define BOOTFLAG_WARM	0x02		/* Software reboot */
732 
733 #if defined(CONFIG_CMD_KGDB)
734 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
735 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
736 #endif
737 
738 /*
739  * Environment Configuration
740  */
741 
742 /* The mac addresses for all ethernet interface */
743 #if defined(CONFIG_TSEC_ENET)
744 #define CONFIG_HAS_ETH0
745 #define CONFIG_ETHADDR	00:E0:0C:02:00:FD
746 #define CONFIG_HAS_ETH1
747 #define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
748 #define CONFIG_HAS_ETH2
749 #define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
750 #define CONFIG_HAS_ETH3
751 #define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
752 #endif
753 
754 #define CONFIG_IPADDR		192.168.1.254
755 
756 #define CONFIG_HOSTNAME		unknown
757 #define CONFIG_ROOTPATH		/opt/nfsroot
758 #define CONFIG_BOOTFILE		uImage
759 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
760 
761 #define CONFIG_SERVERIP		192.168.1.1
762 #define CONFIG_GATEWAYIP	192.168.1.1
763 #define CONFIG_NETMASK		255.255.255.0
764 
765 /* default location for tftp and bootm */
766 #define CONFIG_LOADADDR		1000000
767 
768 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
769 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
770 
771 #define CONFIG_BAUDRATE	115200
772 
773 #define	CONFIG_EXTRA_ENV_SETTINGS				\
774  "netdev=eth0\0"						\
775  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
776  "tftpflash=tftpboot $loadaddr $uboot; "			\
777 	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
778 	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
779 	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
780 	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
781 	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
782  "consoledev=ttyS0\0"				\
783  "ramdiskaddr=2000000\0"			\
784  "ramdiskfile=8536ds/ramdisk.uboot\0"		\
785  "fdtaddr=c00000\0"				\
786  "fdtfile=8536ds/mpc8536ds.dtb\0"		\
787  "bdev=sda3\0"					\
788  "usb_phy_type=ulpi\0"
789 
790 #define CONFIG_HDBOOT				\
791  "setenv bootargs root=/dev/$bdev rw "		\
792  "console=$consoledev,$baudrate $othbootargs;"	\
793  "tftp $loadaddr $bootfile;"			\
794  "tftp $fdtaddr $fdtfile;"			\
795  "bootm $loadaddr - $fdtaddr"
796 
797 #define CONFIG_NFSBOOTCOMMAND		\
798  "setenv bootargs root=/dev/nfs rw "	\
799  "nfsroot=$serverip:$rootpath "		\
800  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
801  "console=$consoledev,$baudrate $othbootargs;"	\
802  "tftp $loadaddr $bootfile;"		\
803  "tftp $fdtaddr $fdtfile;"		\
804  "bootm $loadaddr - $fdtaddr"
805 
806 #define CONFIG_RAMBOOTCOMMAND		\
807  "setenv bootargs root=/dev/ram rw "	\
808  "console=$consoledev,$baudrate $othbootargs;"	\
809  "tftp $ramdiskaddr $ramdiskfile;"	\
810  "tftp $loadaddr $bootfile;"		\
811  "tftp $fdtaddr $fdtfile;"		\
812  "bootm $loadaddr $ramdiskaddr $fdtaddr"
813 
814 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
815 
816 #endif	/* __CONFIG_H */
817