1 /* 2 * Copyright 2008-2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8536 1 35 #define CONFIG_MPC8536DS 1 36 37 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 38 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 39 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 /* 54 * When initializing flash, if we cannot find the manufacturer ID, 55 * assume this is the AMD flash associated with the CDS board. 56 * This allows booting from a promjet. 57 */ 58 #define CONFIG_ASSUME_AMD_FLASH 59 60 #ifndef __ASSEMBLY__ 61 extern unsigned long get_board_sys_clk(unsigned long dummy); 62 extern unsigned long get_board_ddr_clk(unsigned long dummy); 63 #endif 64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 65 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) 66 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 67 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 68 from ICS307 instead of switches */ 69 70 /* 71 * These can be toggled for performance analysis, otherwise use default. 72 */ 73 #define CONFIG_L2_CACHE /* toggle L2 cache */ 74 #define CONFIG_BTB /* toggle branch predition */ 75 76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 77 78 #define CONFIG_ENABLE_36BIT_PHYS 1 79 80 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 81 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 82 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 83 84 /* 85 * Base addresses -- Note these are effective addresses where the 86 * actual resources get mapped (not physical addresses) 87 */ 88 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 89 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 90 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 91 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 92 93 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 94 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 95 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 96 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) 97 98 /* DDR Setup */ 99 #define CONFIG_FSL_DDR2 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 102 #define CONFIG_DDR_SPD 103 #undef CONFIG_DDR_DLL 104 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 106 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 107 108 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 110 111 #define CONFIG_NUM_DDR_CONTROLLERS 1 112 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 113 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 114 115 /* I2C addresses of SPD EEPROMs */ 116 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 117 #define CONFIG_SYS_SPD_BUS_NUM 1 118 119 /* These are used when DDR doesn't use SPD. */ 120 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 123 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 124 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 125 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 126 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 127 #define CONFIG_SYS_DDR_MODE_1 0x00480432 128 #define CONFIG_SYS_DDR_MODE_2 0x00000000 129 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 130 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 131 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 132 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 133 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 134 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 135 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 136 137 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 138 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 139 #define CONFIG_SYS_DDR_SBE 0x00010000 140 141 /* Make sure required options are set */ 142 #ifndef CONFIG_SPD_EEPROM 143 #error ("CONFIG_SPD_EEPROM is required") 144 #endif 145 146 #undef CONFIG_CLOCKS_IN_MHZ 147 148 149 /* 150 * Memory map -- xxx -this is wrong, needs updating 151 * 152 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 153 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 154 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 155 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 156 * 157 * Localbus cacheable (TBD) 158 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 159 * 160 * Localbus non-cacheable 161 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 162 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 163 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 164 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 165 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 166 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 167 */ 168 169 /* 170 * Local Bus Definitions 171 */ 172 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174 175 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 176 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 177 178 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180 181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 182 #define CONFIG_SYS_FLASH_QUIET_TEST 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 184 185 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 191 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 197 198 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 199 200 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 201 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 202 #define PIXIS_BASE_PHYS PIXIS_BASE 203 204 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 205 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 206 207 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 208 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 209 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 210 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 211 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 212 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 213 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 214 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 215 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 216 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 217 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 218 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 219 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 220 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 221 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 222 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 223 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 224 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 225 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 226 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 227 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 228 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 229 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 230 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 231 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 232 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 233 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 234 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 235 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 236 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 237 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 238 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 239 #define PIXIS_LED 0x25 /* LED Register */ 240 241 /* old pixis referenced names */ 242 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 243 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 244 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 245 246 #define CONFIG_SYS_INIT_RAM_LOCK 1 247 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 248 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 249 250 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 251 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 252 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 253 254 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 255 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 256 257 #define CONFIG_SYS_NAND_BASE 0xffa00000 258 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 259 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 260 CONFIG_SYS_NAND_BASE + 0x40000, \ 261 CONFIG_SYS_NAND_BASE + 0x80000, \ 262 CONFIG_SYS_NAND_BASE + 0xC0000} 263 #define CONFIG_SYS_MAX_NAND_DEVICE 4 264 #define CONFIG_MTD_NAND_VERIFY_WRITE 265 #define CONFIG_CMD_NAND 1 266 #define CONFIG_NAND_FSL_ELBC 1 267 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 268 269 /* NAND flash config */ 270 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 271 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 272 | BR_PS_8 /* Port Size = 8 bit */ \ 273 | BR_MS_FCM /* MSEL = FCM */ \ 274 | BR_V) /* valid */ 275 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 276 | OR_FCM_PGS /* Large Page*/ \ 277 | OR_FCM_CSCT \ 278 | OR_FCM_CST \ 279 | OR_FCM_CHT \ 280 | OR_FCM_SCY_1 \ 281 | OR_FCM_TRLX \ 282 | OR_FCM_EHTR) 283 284 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 285 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 286 287 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 288 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 289 | BR_PS_8 /* Port Size = 8 bit */ \ 290 | BR_MS_FCM /* MSEL = FCM */ \ 291 | BR_V) /* valid */ 292 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 293 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 294 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 295 | BR_PS_8 /* Port Size = 8 bit */ \ 296 | BR_MS_FCM /* MSEL = FCM */ \ 297 | BR_V) /* valid */ 298 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 299 300 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 301 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 302 | BR_PS_8 /* Port Size = 8 bit */ \ 303 | BR_MS_FCM /* MSEL = FCM */ \ 304 | BR_V) /* valid */ 305 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 306 307 /* Serial Port - controlled on board with jumper J8 308 * open - index 2 309 * shorted - index 1 310 */ 311 #define CONFIG_CONS_INDEX 1 312 #undef CONFIG_SERIAL_SOFTWARE_FIFO 313 #define CONFIG_SYS_NS16550 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 317 318 #define CONFIG_SYS_BAUDRATE_TABLE \ 319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 320 321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 323 324 /* Use the HUSH parser */ 325 #define CONFIG_SYS_HUSH_PARSER 326 #ifdef CONFIG_SYS_HUSH_PARSER 327 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 328 #endif 329 330 /* 331 * Pass open firmware flat tree 332 */ 333 #define CONFIG_OF_LIBFDT 1 334 #define CONFIG_OF_BOARD_SETUP 1 335 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 336 337 #define CONFIG_SYS_64BIT_STRTOUL 1 338 #define CONFIG_SYS_64BIT_VSPRINTF 1 339 340 341 /* 342 * I2C 343 */ 344 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 345 #define CONFIG_HARD_I2C /* I2C with hardware support */ 346 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 347 #define CONFIG_I2C_MULTI_BUS 348 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 349 #define CONFIG_SYS_I2C_SLAVE 0x7F 350 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 351 #define CONFIG_SYS_I2C_OFFSET 0x3000 352 #define CONFIG_SYS_I2C2_OFFSET 0x3100 353 354 /* 355 * I2C2 EEPROM 356 */ 357 #define CONFIG_ID_EEPROM 358 #ifdef CONFIG_ID_EEPROM 359 #define CONFIG_SYS_I2C_EEPROM_NXID 360 #endif 361 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 362 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 363 #define CONFIG_SYS_EEPROM_BUS_NUM 1 364 365 /* 366 * General PCI 367 * Memory space is mapped 1-1, but I/O space must start from 0. 368 */ 369 370 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 371 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 372 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 373 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 374 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 375 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 376 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 377 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 378 379 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 380 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 381 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 382 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 383 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 384 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 385 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 386 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 387 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 388 389 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 390 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 391 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 392 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 393 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 394 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 395 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 396 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 397 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 398 399 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 400 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 401 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 402 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 403 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 404 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 405 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 406 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 407 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 408 409 #if defined(CONFIG_PCI) 410 411 #define CONFIG_NET_MULTI 412 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 413 414 /*PCIE video card used*/ 415 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 416 417 /*PCI video card used*/ 418 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 419 420 /* video */ 421 #define CONFIG_VIDEO 422 423 #if defined(CONFIG_VIDEO) 424 #define CONFIG_BIOSEMU 425 #define CONFIG_CFB_CONSOLE 426 #define CONFIG_VIDEO_SW_CURSOR 427 #define CONFIG_VGA_AS_SINGLE_DEVICE 428 #define CONFIG_ATI_RADEON_FB 429 #define CONFIG_VIDEO_LOGO 430 /*#define CONFIG_CONSOLE_CURSOR*/ 431 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 432 #endif 433 434 #undef CONFIG_EEPRO100 435 #undef CONFIG_TULIP 436 #undef CONFIG_RTL8139 437 438 #ifndef CONFIG_PCI_PNP 439 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 440 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 441 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 442 #endif 443 444 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 445 446 #endif /* CONFIG_PCI */ 447 448 /* SATA */ 449 #define CONFIG_LIBATA 450 #define CONFIG_FSL_SATA 451 452 #define CONFIG_SYS_SATA_MAX_DEVICE 2 453 #define CONFIG_SATA1 454 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 455 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 456 #define CONFIG_SATA2 457 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 458 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 459 460 #ifdef CONFIG_FSL_SATA 461 #define CONFIG_LBA48 462 #define CONFIG_CMD_SATA 463 #define CONFIG_DOS_PARTITION 464 #define CONFIG_CMD_EXT2 465 #endif 466 467 /* 468 * USB 469 */ 470 #define CONFIG_CMD_USB 471 #define CONFIG_USB_STORAGE 472 #define CONFIG_USB_EHCI 473 #define CONFIG_USB_EHCI_FSL 474 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 475 476 #if defined(CONFIG_TSEC_ENET) 477 478 #ifndef CONFIG_NET_MULTI 479 #define CONFIG_NET_MULTI 1 480 #endif 481 482 #define CONFIG_MII 1 /* MII PHY management */ 483 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 484 #define CONFIG_TSEC1 1 485 #define CONFIG_TSEC1_NAME "eTSEC1" 486 #define CONFIG_TSEC3 1 487 #define CONFIG_TSEC3_NAME "eTSEC3" 488 489 #define CONFIG_FSL_SGMII_RISER 1 490 #define SGMII_RISER_PHY_OFFSET 0x1c 491 492 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 493 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 494 495 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 496 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 497 498 #define TSEC1_PHYIDX 0 499 #define TSEC3_PHYIDX 0 500 501 #define CONFIG_ETHPRIME "eTSEC1" 502 503 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 504 505 #endif /* CONFIG_TSEC_ENET */ 506 507 /* 508 * Environment 509 */ 510 #define CONFIG_ENV_IS_IN_FLASH 1 511 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 512 #define CONFIG_ENV_ADDR 0xfff80000 513 #else 514 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 515 #endif 516 #define CONFIG_ENV_SIZE 0x2000 517 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 518 519 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 520 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 521 522 /* 523 * Command line configuration. 524 */ 525 #include <config_cmd_default.h> 526 527 #define CONFIG_CMD_IRQ 528 #define CONFIG_CMD_PING 529 #define CONFIG_CMD_I2C 530 #define CONFIG_CMD_MII 531 #define CONFIG_CMD_ELF 532 #define CONFIG_CMD_IRQ 533 #define CONFIG_CMD_SETEXPR 534 535 #if defined(CONFIG_PCI) 536 #define CONFIG_CMD_PCI 537 #define CONFIG_CMD_BEDBUG 538 #define CONFIG_CMD_NET 539 #endif 540 541 #undef CONFIG_WATCHDOG /* watchdog disabled */ 542 543 #define CONFIG_MMC 1 544 545 #ifdef CONFIG_MMC 546 #define CONFIG_FSL_ESDHC 547 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 548 #define CONFIG_CMD_MMC 549 #define CONFIG_GENERIC_MMC 550 #define CONFIG_CMD_EXT2 551 #define CONFIG_CMD_FAT 552 #define CONFIG_DOS_PARTITION 553 #endif 554 555 /* 556 * Miscellaneous configurable options 557 */ 558 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 559 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 560 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 561 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 562 #if defined(CONFIG_CMD_KGDB) 563 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 564 #else 565 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 566 #endif 567 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 568 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 569 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 570 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 571 572 /* 573 * For booting Linux, the board info and command line data 574 * have to be in the first 16 MB of memory, since this is 575 * the maximum mapped by the Linux kernel during initialization. 576 */ 577 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 578 579 /* 580 * Internal Definitions 581 * 582 * Boot Flags 583 */ 584 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 585 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 586 587 #if defined(CONFIG_CMD_KGDB) 588 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 589 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 590 #endif 591 592 /* 593 * Environment Configuration 594 */ 595 596 /* The mac addresses for all ethernet interface */ 597 #if defined(CONFIG_TSEC_ENET) 598 #define CONFIG_HAS_ETH0 599 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 600 #define CONFIG_HAS_ETH1 601 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 602 #define CONFIG_HAS_ETH2 603 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 604 #define CONFIG_HAS_ETH3 605 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 606 #endif 607 608 #define CONFIG_IPADDR 192.168.1.254 609 610 #define CONFIG_HOSTNAME unknown 611 #define CONFIG_ROOTPATH /opt/nfsroot 612 #define CONFIG_BOOTFILE uImage 613 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 614 615 #define CONFIG_SERVERIP 192.168.1.1 616 #define CONFIG_GATEWAYIP 192.168.1.1 617 #define CONFIG_NETMASK 255.255.255.0 618 619 /* default location for tftp and bootm */ 620 #define CONFIG_LOADADDR 1000000 621 622 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 623 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 624 625 #define CONFIG_BAUDRATE 115200 626 627 #define CONFIG_EXTRA_ENV_SETTINGS \ 628 "netdev=eth0\0" \ 629 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 630 "tftpflash=tftpboot $loadaddr $uboot; " \ 631 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 632 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 633 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 634 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 635 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 636 "consoledev=ttyS0\0" \ 637 "ramdiskaddr=2000000\0" \ 638 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 639 "fdtaddr=c00000\0" \ 640 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 641 "bdev=sda3\0" \ 642 "usb_phy_type=ulpi\0" 643 644 #define CONFIG_HDBOOT \ 645 "setenv bootargs root=/dev/$bdev rw " \ 646 "console=$consoledev,$baudrate $othbootargs;" \ 647 "tftp $loadaddr $bootfile;" \ 648 "tftp $fdtaddr $fdtfile;" \ 649 "bootm $loadaddr - $fdtaddr" 650 651 #define CONFIG_NFSBOOTCOMMAND \ 652 "setenv bootargs root=/dev/nfs rw " \ 653 "nfsroot=$serverip:$rootpath " \ 654 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 655 "console=$consoledev,$baudrate $othbootargs;" \ 656 "tftp $loadaddr $bootfile;" \ 657 "tftp $fdtaddr $fdtfile;" \ 658 "bootm $loadaddr - $fdtaddr" 659 660 #define CONFIG_RAMBOOTCOMMAND \ 661 "setenv bootargs root=/dev/ram rw " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp $ramdiskaddr $ramdiskfile;" \ 664 "tftp $loadaddr $bootfile;" \ 665 "tftp $fdtaddr $fdtfile;" \ 666 "bootm $loadaddr $ramdiskaddr $fdtaddr" 667 668 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 669 670 #endif /* __CONFIG_H */ 671