1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifdef CONFIG_36BIT 19 #define CONFIG_PHYS_64BIT 1 20 #endif 21 22 #ifdef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_SDCARD 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifdef CONFIG_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH 1 30 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 32 #endif 33 34 #ifndef CONFIG_SYS_TEXT_BASE 35 #define CONFIG_SYS_TEXT_BASE 0xeff40000 36 #endif 37 38 #ifndef CONFIG_RESET_VECTOR_ADDRESS 39 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 40 #endif 41 42 #ifndef CONFIG_SYS_MONITOR_BASE 43 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 44 #endif 45 46 /* High Level Configuration Options */ 47 #define CONFIG_BOOKE 1 /* BOOKE */ 48 #define CONFIG_E500 1 /* BOOKE e500 family */ 49 #define CONFIG_MPC8536 1 50 #define CONFIG_MPC8536DS 1 51 52 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 53 #define CONFIG_SPI_FLASH 1 /* Has SPI Flash */ 54 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 55 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 56 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 57 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 58 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 59 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 60 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 61 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 62 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 63 64 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 65 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 66 67 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 68 #define CONFIG_ENV_OVERWRITE 69 70 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 71 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 72 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_L2_CACHE /* toggle L2 cache */ 78 #define CONFIG_BTB /* toggle branch predition */ 79 80 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 81 82 #define CONFIG_ENABLE_36BIT_PHYS 1 83 84 #ifdef CONFIG_PHYS_64BIT 85 #define CONFIG_ADDR_MAP 1 86 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 87 #endif 88 89 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 90 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 91 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 92 93 /* 94 * Config the L2 Cache as L2 SRAM 95 */ 96 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 97 #ifdef CONFIG_PHYS_64BIT 98 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 99 #else 100 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 101 #endif 102 #define CONFIG_SYS_L2_SIZE (512 << 10) 103 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 104 105 #define CONFIG_SYS_CCSRBAR 0xffe00000 106 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 107 108 #if defined(CONFIG_NAND_SPL) 109 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 110 #endif 111 112 /* DDR Setup */ 113 #define CONFIG_VERY_BIG_RAM 114 #define CONFIG_SYS_FSL_DDR2 115 #undef CONFIG_FSL_DDR_INTERACTIVE 116 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 117 #define CONFIG_DDR_SPD 118 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 120 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 121 122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 124 125 #define CONFIG_NUM_DDR_CONTROLLERS 1 126 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 127 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 128 129 /* I2C addresses of SPD EEPROMs */ 130 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 131 #define CONFIG_SYS_SPD_BUS_NUM 1 132 133 /* These are used when DDR doesn't use SPD. */ 134 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 135 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 136 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 138 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 139 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 140 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 141 #define CONFIG_SYS_DDR_MODE_1 0x00480432 142 #define CONFIG_SYS_DDR_MODE_2 0x00000000 143 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 144 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 145 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 146 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 147 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 148 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 149 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 150 151 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 152 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 153 #define CONFIG_SYS_DDR_SBE 0x00010000 154 155 /* Make sure required options are set */ 156 #ifndef CONFIG_SPD_EEPROM 157 #error ("CONFIG_SPD_EEPROM is required") 158 #endif 159 160 #undef CONFIG_CLOCKS_IN_MHZ 161 162 163 /* 164 * Memory map -- xxx -this is wrong, needs updating 165 * 166 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 167 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 168 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 169 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 170 * 171 * Localbus cacheable (TBD) 172 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 173 * 174 * Localbus non-cacheable 175 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 176 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 177 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 178 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 179 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 180 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 181 */ 182 183 /* 184 * Local Bus Definitions 185 */ 186 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 187 #ifdef CONFIG_PHYS_64BIT 188 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 189 #else 190 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 191 #endif 192 193 #define CONFIG_FLASH_BR_PRELIM \ 194 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 195 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 196 197 #define CONFIG_SYS_BR1_PRELIM \ 198 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 199 | BR_PS_16 | BR_V) 200 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 201 202 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 203 CONFIG_SYS_FLASH_BASE_PHYS } 204 #define CONFIG_SYS_FLASH_QUIET_TEST 205 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 206 207 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 209 #undef CONFIG_SYS_FLASH_CHECKSUM 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 212 213 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 214 #define CONFIG_SYS_RAMBOOT 215 #define CONFIG_SYS_EXTRA_ENV_RELOC 216 #else 217 #undef CONFIG_SYS_RAMBOOT 218 #endif 219 220 #define CONFIG_FLASH_CFI_DRIVER 221 #define CONFIG_SYS_FLASH_CFI 222 #define CONFIG_SYS_FLASH_EMPTY_INFO 223 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 224 225 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 226 227 #define CONFIG_HWCONFIG /* enable hwconfig */ 228 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 229 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 230 #ifdef CONFIG_PHYS_64BIT 231 #define PIXIS_BASE_PHYS 0xfffdf0000ull 232 #else 233 #define PIXIS_BASE_PHYS PIXIS_BASE 234 #endif 235 236 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 237 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 238 239 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 240 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 241 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 242 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 243 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 244 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 245 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 246 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 247 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 248 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 249 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 250 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 251 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 252 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 253 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 254 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 255 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 256 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 257 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 258 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 259 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 260 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 261 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 262 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 263 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 264 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 265 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 266 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 267 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 268 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 269 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 270 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 271 #define PIXIS_LED 0x25 /* LED Register */ 272 273 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 274 275 /* old pixis referenced names */ 276 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 277 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 278 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 279 280 #define CONFIG_SYS_INIT_RAM_LOCK 1 281 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 282 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 283 284 #define CONFIG_SYS_GBL_DATA_OFFSET \ 285 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 286 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 287 288 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 289 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 290 291 #ifndef CONFIG_NAND_SPL 292 #define CONFIG_SYS_NAND_BASE 0xffa00000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 295 #else 296 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 297 #endif 298 #else 299 #define CONFIG_SYS_NAND_BASE 0xfff00000 300 #ifdef CONFIG_PHYS_64BIT 301 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 302 #else 303 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 304 #endif 305 #endif 306 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 307 CONFIG_SYS_NAND_BASE + 0x40000, \ 308 CONFIG_SYS_NAND_BASE + 0x80000, \ 309 CONFIG_SYS_NAND_BASE + 0xC0000} 310 #define CONFIG_SYS_MAX_NAND_DEVICE 4 311 #define CONFIG_MTD_NAND_VERIFY_WRITE 312 #define CONFIG_CMD_NAND 1 313 #define CONFIG_NAND_FSL_ELBC 1 314 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 315 316 /* NAND boot: 4K NAND loader config */ 317 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 318 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 319 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 320 #define CONFIG_SYS_NAND_U_BOOT_START \ 321 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 322 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 323 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 324 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 325 326 /* NAND flash config */ 327 #define CONFIG_SYS_NAND_BR_PRELIM \ 328 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 329 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 330 | BR_PS_8 /* Port Size = 8 bit */ \ 331 | BR_MS_FCM /* MSEL = FCM */ \ 332 | BR_V) /* valid */ 333 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 334 | OR_FCM_PGS /* Large Page*/ \ 335 | OR_FCM_CSCT \ 336 | OR_FCM_CST \ 337 | OR_FCM_CHT \ 338 | OR_FCM_SCY_1 \ 339 | OR_FCM_TRLX \ 340 | OR_FCM_EHTR) 341 342 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 343 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 344 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 345 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 346 347 #define CONFIG_SYS_BR4_PRELIM \ 348 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 349 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 350 | BR_PS_8 /* Port Size = 8 bit */ \ 351 | BR_MS_FCM /* MSEL = FCM */ \ 352 | BR_V) /* valid */ 353 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 354 #define CONFIG_SYS_BR5_PRELIM \ 355 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 356 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 357 | BR_PS_8 /* Port Size = 8 bit */ \ 358 | BR_MS_FCM /* MSEL = FCM */ \ 359 | BR_V) /* valid */ 360 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 361 362 #define CONFIG_SYS_BR6_PRELIM \ 363 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 364 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 365 | BR_PS_8 /* Port Size = 8 bit */ \ 366 | BR_MS_FCM /* MSEL = FCM */ \ 367 | BR_V) /* valid */ 368 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 369 370 /* Serial Port - controlled on board with jumper J8 371 * open - index 2 372 * shorted - index 1 373 */ 374 #define CONFIG_CONS_INDEX 1 375 #define CONFIG_SYS_NS16550 376 #define CONFIG_SYS_NS16550_SERIAL 377 #define CONFIG_SYS_NS16550_REG_SIZE 1 378 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 379 #ifdef CONFIG_NAND_SPL 380 #define CONFIG_NS16550_MIN_FUNCTIONS 381 #endif 382 383 #define CONFIG_SYS_BAUDRATE_TABLE \ 384 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 385 386 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 387 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 388 389 /* Use the HUSH parser */ 390 #define CONFIG_SYS_HUSH_PARSER 391 392 /* 393 * Pass open firmware flat tree 394 */ 395 #define CONFIG_OF_LIBFDT 1 396 #define CONFIG_OF_BOARD_SETUP 1 397 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 398 399 /* 400 * I2C 401 */ 402 #define CONFIG_SYS_I2C 403 #define CONFIG_SYS_I2C_FSL 404 #define CONFIG_SYS_FSL_I2C_SPEED 400000 405 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 406 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 407 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 408 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 409 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 410 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 411 412 /* 413 * I2C2 EEPROM 414 */ 415 #define CONFIG_ID_EEPROM 416 #ifdef CONFIG_ID_EEPROM 417 #define CONFIG_SYS_I2C_EEPROM_NXID 418 #endif 419 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 420 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 421 #define CONFIG_SYS_EEPROM_BUS_NUM 1 422 423 /* 424 * eSPI - Enhanced SPI 425 */ 426 #define CONFIG_HARD_SPI 427 #define CONFIG_FSL_ESPI 428 429 #if defined(CONFIG_SPI_FLASH) 430 #define CONFIG_SPI_FLASH_SPANSION 431 #define CONFIG_CMD_SF 432 #define CONFIG_SF_DEFAULT_SPEED 10000000 433 #define CONFIG_SF_DEFAULT_MODE 0 434 #endif 435 436 /* 437 * General PCI 438 * Memory space is mapped 1-1, but I/O space must start from 0. 439 */ 440 441 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 444 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 445 #else 446 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 447 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 448 #endif 449 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 450 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 451 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 454 #else 455 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 456 #endif 457 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 458 459 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 460 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 461 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 464 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 465 #else 466 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 467 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 468 #endif 469 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 470 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 471 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 474 #else 475 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 476 #endif 477 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 478 479 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 480 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 481 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 484 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 485 #else 486 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 487 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 488 #endif 489 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 490 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 491 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 492 #ifdef CONFIG_PHYS_64BIT 493 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 494 #else 495 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 496 #endif 497 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 498 499 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 500 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 501 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 504 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 505 #else 506 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 508 #endif 509 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 510 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 511 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 512 #ifdef CONFIG_PHYS_64BIT 513 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 514 #else 515 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 516 #endif 517 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 518 519 #if defined(CONFIG_PCI) 520 521 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 522 523 /*PCIE video card used*/ 524 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 525 526 /*PCI video card used*/ 527 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 528 529 /* video */ 530 #define CONFIG_VIDEO 531 532 #if defined(CONFIG_VIDEO) 533 #define CONFIG_BIOSEMU 534 #define CONFIG_CFB_CONSOLE 535 #define CONFIG_VIDEO_SW_CURSOR 536 #define CONFIG_VGA_AS_SINGLE_DEVICE 537 #define CONFIG_ATI_RADEON_FB 538 #define CONFIG_VIDEO_LOGO 539 /*#define CONFIG_CONSOLE_CURSOR*/ 540 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 541 #endif 542 543 #undef CONFIG_EEPRO100 544 #undef CONFIG_TULIP 545 #undef CONFIG_RTL8139 546 547 #ifndef CONFIG_PCI_PNP 548 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 549 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 550 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 551 #endif 552 553 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 554 555 #endif /* CONFIG_PCI */ 556 557 /* SATA */ 558 #define CONFIG_LIBATA 559 #define CONFIG_FSL_SATA 560 561 #define CONFIG_SYS_SATA_MAX_DEVICE 2 562 #define CONFIG_SATA1 563 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 564 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 565 #define CONFIG_SATA2 566 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 567 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 568 569 #ifdef CONFIG_FSL_SATA 570 #define CONFIG_LBA48 571 #define CONFIG_CMD_SATA 572 #define CONFIG_DOS_PARTITION 573 #define CONFIG_CMD_EXT2 574 #endif 575 576 #if defined(CONFIG_TSEC_ENET) 577 578 #define CONFIG_MII 1 /* MII PHY management */ 579 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 580 #define CONFIG_TSEC1 1 581 #define CONFIG_TSEC1_NAME "eTSEC1" 582 #define CONFIG_TSEC3 1 583 #define CONFIG_TSEC3_NAME "eTSEC3" 584 585 #define CONFIG_FSL_SGMII_RISER 1 586 #define SGMII_RISER_PHY_OFFSET 0x1c 587 588 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 589 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 590 591 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 592 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 593 594 #define TSEC1_PHYIDX 0 595 #define TSEC3_PHYIDX 0 596 597 #define CONFIG_ETHPRIME "eTSEC1" 598 599 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 600 601 #endif /* CONFIG_TSEC_ENET */ 602 603 /* 604 * Environment 605 */ 606 607 #if defined(CONFIG_SYS_RAMBOOT) 608 #if defined(CONFIG_RAMBOOT_SPIFLASH) 609 #define CONFIG_ENV_IS_IN_SPI_FLASH 610 #define CONFIG_ENV_SPI_BUS 0 611 #define CONFIG_ENV_SPI_CS 0 612 #define CONFIG_ENV_SPI_MAX_HZ 10000000 613 #define CONFIG_ENV_SPI_MODE 0 614 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 615 #define CONFIG_ENV_OFFSET 0xF0000 616 #define CONFIG_ENV_SECT_SIZE 0x10000 617 #elif defined(CONFIG_RAMBOOT_SDCARD) 618 #define CONFIG_ENV_IS_IN_MMC 619 #define CONFIG_FSL_FIXED_MMC_LOCATION 620 #define CONFIG_ENV_SIZE 0x2000 621 #define CONFIG_SYS_MMC_ENV_DEV 0 622 #else 623 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 624 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 625 #define CONFIG_ENV_SIZE 0x2000 626 #endif 627 #else 628 #define CONFIG_ENV_IS_IN_FLASH 1 629 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 630 #define CONFIG_ENV_SIZE 0x2000 631 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 632 #endif 633 634 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 635 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 636 637 /* 638 * Command line configuration. 639 */ 640 #include <config_cmd_default.h> 641 642 #define CONFIG_CMD_IRQ 643 #define CONFIG_CMD_PING 644 #define CONFIG_CMD_I2C 645 #define CONFIG_CMD_MII 646 #define CONFIG_CMD_ELF 647 #define CONFIG_CMD_IRQ 648 #define CONFIG_CMD_SETEXPR 649 #define CONFIG_CMD_REGINFO 650 651 #if defined(CONFIG_PCI) 652 #define CONFIG_CMD_PCI 653 #define CONFIG_CMD_NET 654 #endif 655 656 #undef CONFIG_WATCHDOG /* watchdog disabled */ 657 658 #define CONFIG_MMC 1 659 660 #ifdef CONFIG_MMC 661 #define CONFIG_FSL_ESDHC 662 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 663 #define CONFIG_CMD_MMC 664 #define CONFIG_GENERIC_MMC 665 #endif 666 667 /* 668 * USB 669 */ 670 #define CONFIG_HAS_FSL_MPH_USB 671 #ifdef CONFIG_HAS_FSL_MPH_USB 672 #define CONFIG_USB_EHCI 673 674 #ifdef CONFIG_USB_EHCI 675 #define CONFIG_CMD_USB 676 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 677 #define CONFIG_USB_EHCI_FSL 678 #define CONFIG_USB_STORAGE 679 #endif 680 #endif 681 682 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 683 #define CONFIG_CMD_EXT2 684 #define CONFIG_CMD_FAT 685 #define CONFIG_DOS_PARTITION 686 #endif 687 688 /* 689 * Miscellaneous configurable options 690 */ 691 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 692 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 693 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 694 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 695 #if defined(CONFIG_CMD_KGDB) 696 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 697 #else 698 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 699 #endif 700 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 701 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 702 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 703 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 704 705 /* 706 * For booting Linux, the board info and command line data 707 * have to be in the first 64 MB of memory, since this is 708 * the maximum mapped by the Linux kernel during initialization. 709 */ 710 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 711 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 712 713 #if defined(CONFIG_CMD_KGDB) 714 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 715 #endif 716 717 /* 718 * Environment Configuration 719 */ 720 721 /* The mac addresses for all ethernet interface */ 722 #if defined(CONFIG_TSEC_ENET) 723 #define CONFIG_HAS_ETH0 724 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 725 #define CONFIG_HAS_ETH1 726 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 727 #define CONFIG_HAS_ETH2 728 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 729 #define CONFIG_HAS_ETH3 730 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 731 #endif 732 733 #define CONFIG_IPADDR 192.168.1.254 734 735 #define CONFIG_HOSTNAME unknown 736 #define CONFIG_ROOTPATH "/opt/nfsroot" 737 #define CONFIG_BOOTFILE "uImage" 738 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 739 740 #define CONFIG_SERVERIP 192.168.1.1 741 #define CONFIG_GATEWAYIP 192.168.1.1 742 #define CONFIG_NETMASK 255.255.255.0 743 744 /* default location for tftp and bootm */ 745 #define CONFIG_LOADADDR 1000000 746 747 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 748 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 749 750 #define CONFIG_BAUDRATE 115200 751 752 #define CONFIG_EXTRA_ENV_SETTINGS \ 753 "netdev=eth0\0" \ 754 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 755 "tftpflash=tftpboot $loadaddr $uboot; " \ 756 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 757 " +$filesize; " \ 758 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 759 " +$filesize; " \ 760 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 761 " $filesize; " \ 762 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 763 " +$filesize; " \ 764 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 765 " $filesize\0" \ 766 "consoledev=ttyS0\0" \ 767 "ramdiskaddr=2000000\0" \ 768 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 769 "fdtaddr=c00000\0" \ 770 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 771 "bdev=sda3\0" \ 772 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 773 774 #define CONFIG_HDBOOT \ 775 "setenv bootargs root=/dev/$bdev rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "tftp $loadaddr $bootfile;" \ 778 "tftp $fdtaddr $fdtfile;" \ 779 "bootm $loadaddr - $fdtaddr" 780 781 #define CONFIG_NFSBOOTCOMMAND \ 782 "setenv bootargs root=/dev/nfs rw " \ 783 "nfsroot=$serverip:$rootpath " \ 784 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 785 "console=$consoledev,$baudrate $othbootargs;" \ 786 "tftp $loadaddr $bootfile;" \ 787 "tftp $fdtaddr $fdtfile;" \ 788 "bootm $loadaddr - $fdtaddr" 789 790 #define CONFIG_RAMBOOTCOMMAND \ 791 "setenv bootargs root=/dev/ram rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "tftp $ramdiskaddr $ramdiskfile;" \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr $ramdiskaddr $fdtaddr" 797 798 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 799 800 #endif /* __CONFIG_H */ 801