1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 41 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 44 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 46 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 47 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 49 50 51 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE /* toggle L2 cache */ 62 #define CONFIG_BTB /* toggle branch predition */ 63 64 #define CONFIG_ENABLE_36BIT_PHYS 1 65 66 #ifdef CONFIG_PHYS_64BIT 67 #define CONFIG_ADDR_MAP 1 68 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 69 #endif 70 71 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 72 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 73 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 74 75 /* 76 * Config the L2 Cache as L2 SRAM 77 */ 78 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 79 #ifdef CONFIG_PHYS_64BIT 80 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 81 #else 82 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 83 #endif 84 #define CONFIG_SYS_L2_SIZE (512 << 10) 85 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 86 87 #define CONFIG_SYS_CCSRBAR 0xffe00000 88 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 89 90 #if defined(CONFIG_NAND_SPL) 91 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 92 #endif 93 94 /* DDR Setup */ 95 #define CONFIG_VERY_BIG_RAM 96 #undef CONFIG_FSL_DDR_INTERACTIVE 97 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 98 #define CONFIG_DDR_SPD 99 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 107 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 108 109 /* I2C addresses of SPD EEPROMs */ 110 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 111 #define CONFIG_SYS_SPD_BUS_NUM 1 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 115 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 116 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 117 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 118 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 119 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 120 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 121 #define CONFIG_SYS_DDR_MODE_1 0x00480432 122 #define CONFIG_SYS_DDR_MODE_2 0x00000000 123 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 124 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 125 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 126 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 127 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 128 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 129 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 130 131 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 132 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 133 #define CONFIG_SYS_DDR_SBE 0x00010000 134 135 /* Make sure required options are set */ 136 #ifndef CONFIG_SPD_EEPROM 137 #error ("CONFIG_SPD_EEPROM is required") 138 #endif 139 140 #undef CONFIG_CLOCKS_IN_MHZ 141 142 /* 143 * Memory map -- xxx -this is wrong, needs updating 144 * 145 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 146 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 147 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 148 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 149 * 150 * Localbus cacheable (TBD) 151 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 152 * 153 * Localbus non-cacheable 154 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 155 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 156 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 157 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 158 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 159 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 160 */ 161 162 /* 163 * Local Bus Definitions 164 */ 165 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 166 #ifdef CONFIG_PHYS_64BIT 167 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 168 #else 169 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 170 #endif 171 172 #define CONFIG_FLASH_BR_PRELIM \ 173 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 174 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 175 176 #define CONFIG_SYS_BR1_PRELIM \ 177 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 178 | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180 181 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 182 CONFIG_SYS_FLASH_BASE_PHYS } 183 #define CONFIG_SYS_FLASH_QUIET_TEST 184 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 185 186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 187 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 188 #undef CONFIG_SYS_FLASH_CHECKSUM 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 192 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 193 #define CONFIG_SYS_RAMBOOT 194 #define CONFIG_SYS_EXTRA_ENV_RELOC 195 #else 196 #undef CONFIG_SYS_RAMBOOT 197 #endif 198 199 #define CONFIG_FLASH_CFI_DRIVER 200 #define CONFIG_SYS_FLASH_CFI 201 #define CONFIG_SYS_FLASH_EMPTY_INFO 202 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 203 204 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 205 206 #define CONFIG_HWCONFIG /* enable hwconfig */ 207 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 208 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 209 #ifdef CONFIG_PHYS_64BIT 210 #define PIXIS_BASE_PHYS 0xfffdf0000ull 211 #else 212 #define PIXIS_BASE_PHYS PIXIS_BASE 213 #endif 214 215 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 216 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 217 218 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 219 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 220 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 221 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 222 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 223 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 224 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 225 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 226 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 227 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 228 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 229 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 230 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 231 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 232 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 233 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 234 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 235 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 236 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 237 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 238 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 239 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 240 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 241 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 242 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 243 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 244 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 245 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 246 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 247 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 248 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 249 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 250 #define PIXIS_LED 0x25 /* LED Register */ 251 252 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 253 254 /* old pixis referenced names */ 255 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 256 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 257 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 258 259 #define CONFIG_SYS_INIT_RAM_LOCK 1 260 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 261 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 262 263 #define CONFIG_SYS_GBL_DATA_OFFSET \ 264 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 265 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 266 267 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 268 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 269 270 #ifndef CONFIG_NAND_SPL 271 #define CONFIG_SYS_NAND_BASE 0xffa00000 272 #ifdef CONFIG_PHYS_64BIT 273 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 274 #else 275 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 276 #endif 277 #else 278 #define CONFIG_SYS_NAND_BASE 0xfff00000 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 281 #else 282 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 283 #endif 284 #endif 285 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 286 CONFIG_SYS_NAND_BASE + 0x40000, \ 287 CONFIG_SYS_NAND_BASE + 0x80000, \ 288 CONFIG_SYS_NAND_BASE + 0xC0000} 289 #define CONFIG_SYS_MAX_NAND_DEVICE 4 290 #define CONFIG_CMD_NAND 1 291 #define CONFIG_NAND_FSL_ELBC 1 292 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 293 294 /* NAND boot: 4K NAND loader config */ 295 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 296 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 297 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 298 #define CONFIG_SYS_NAND_U_BOOT_START \ 299 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 300 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 301 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 302 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 303 304 /* NAND flash config */ 305 #define CONFIG_SYS_NAND_BR_PRELIM \ 306 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 307 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 308 | BR_PS_8 /* Port Size = 8 bit */ \ 309 | BR_MS_FCM /* MSEL = FCM */ \ 310 | BR_V) /* valid */ 311 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 312 | OR_FCM_PGS /* Large Page*/ \ 313 | OR_FCM_CSCT \ 314 | OR_FCM_CST \ 315 | OR_FCM_CHT \ 316 | OR_FCM_SCY_1 \ 317 | OR_FCM_TRLX \ 318 | OR_FCM_EHTR) 319 320 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 321 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 322 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 323 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 324 325 #define CONFIG_SYS_BR4_PRELIM \ 326 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 327 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 328 | BR_PS_8 /* Port Size = 8 bit */ \ 329 | BR_MS_FCM /* MSEL = FCM */ \ 330 | BR_V) /* valid */ 331 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 332 #define CONFIG_SYS_BR5_PRELIM \ 333 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 334 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 335 | BR_PS_8 /* Port Size = 8 bit */ \ 336 | BR_MS_FCM /* MSEL = FCM */ \ 337 | BR_V) /* valid */ 338 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 339 340 #define CONFIG_SYS_BR6_PRELIM \ 341 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 343 | BR_PS_8 /* Port Size = 8 bit */ \ 344 | BR_MS_FCM /* MSEL = FCM */ \ 345 | BR_V) /* valid */ 346 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 347 348 /* Serial Port - controlled on board with jumper J8 349 * open - index 2 350 * shorted - index 1 351 */ 352 #define CONFIG_CONS_INDEX 1 353 #define CONFIG_SYS_NS16550_SERIAL 354 #define CONFIG_SYS_NS16550_REG_SIZE 1 355 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 356 #ifdef CONFIG_NAND_SPL 357 #define CONFIG_NS16550_MIN_FUNCTIONS 358 #endif 359 360 #define CONFIG_SYS_BAUDRATE_TABLE \ 361 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 362 363 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 364 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 365 366 /* 367 * I2C 368 */ 369 #define CONFIG_SYS_I2C 370 #define CONFIG_SYS_I2C_FSL 371 #define CONFIG_SYS_FSL_I2C_SPEED 400000 372 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 373 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 374 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 375 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 376 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 377 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 378 379 /* 380 * I2C2 EEPROM 381 */ 382 #define CONFIG_ID_EEPROM 383 #ifdef CONFIG_ID_EEPROM 384 #define CONFIG_SYS_I2C_EEPROM_NXID 385 #endif 386 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 387 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 388 #define CONFIG_SYS_EEPROM_BUS_NUM 1 389 390 /* 391 * eSPI - Enhanced SPI 392 */ 393 #define CONFIG_HARD_SPI 394 395 #if defined(CONFIG_SPI_FLASH) 396 #define CONFIG_SF_DEFAULT_SPEED 10000000 397 #define CONFIG_SF_DEFAULT_MODE 0 398 #endif 399 400 /* 401 * General PCI 402 * Memory space is mapped 1-1, but I/O space must start from 0. 403 */ 404 405 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 408 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 409 #else 410 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 411 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 412 #endif 413 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 414 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 415 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 418 #else 419 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 420 #endif 421 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 422 423 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 424 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 429 #else 430 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 432 #endif 433 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 434 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 435 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 438 #else 439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 440 #endif 441 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 442 443 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 444 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 445 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 449 #else 450 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 452 #endif 453 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 454 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 455 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 458 #else 459 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 460 #endif 461 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 462 463 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 464 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 465 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 469 #else 470 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 471 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 472 #endif 473 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 474 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 475 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 478 #else 479 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 480 #endif 481 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 482 483 #if defined(CONFIG_PCI) 484 /*PCIE video card used*/ 485 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 486 487 /*PCI video card used*/ 488 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 489 490 /* video */ 491 492 #if defined(CONFIG_VIDEO) 493 #define CONFIG_BIOSEMU 494 #define CONFIG_ATI_RADEON_FB 495 #define CONFIG_VIDEO_LOGO 496 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 497 #endif 498 499 #undef CONFIG_EEPRO100 500 #undef CONFIG_TULIP 501 502 #ifndef CONFIG_PCI_PNP 503 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 504 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 505 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 506 #endif 507 508 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 509 510 #endif /* CONFIG_PCI */ 511 512 /* SATA */ 513 #define CONFIG_LIBATA 514 #define CONFIG_FSL_SATA 515 516 #define CONFIG_SYS_SATA_MAX_DEVICE 2 517 #define CONFIG_SATA1 518 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 519 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 520 #define CONFIG_SATA2 521 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 522 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 523 524 #ifdef CONFIG_FSL_SATA 525 #define CONFIG_LBA48 526 #define CONFIG_CMD_SATA 527 #endif 528 529 #if defined(CONFIG_TSEC_ENET) 530 531 #define CONFIG_MII 1 /* MII PHY management */ 532 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 533 #define CONFIG_TSEC1 1 534 #define CONFIG_TSEC1_NAME "eTSEC1" 535 #define CONFIG_TSEC3 1 536 #define CONFIG_TSEC3_NAME "eTSEC3" 537 538 #define CONFIG_FSL_SGMII_RISER 1 539 #define SGMII_RISER_PHY_OFFSET 0x1c 540 541 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 542 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 543 544 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 545 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 546 547 #define TSEC1_PHYIDX 0 548 #define TSEC3_PHYIDX 0 549 550 #define CONFIG_ETHPRIME "eTSEC1" 551 552 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 553 554 #endif /* CONFIG_TSEC_ENET */ 555 556 /* 557 * Environment 558 */ 559 560 #if defined(CONFIG_SYS_RAMBOOT) 561 #if defined(CONFIG_RAMBOOT_SPIFLASH) 562 #define CONFIG_ENV_IS_IN_SPI_FLASH 563 #define CONFIG_ENV_SPI_BUS 0 564 #define CONFIG_ENV_SPI_CS 0 565 #define CONFIG_ENV_SPI_MAX_HZ 10000000 566 #define CONFIG_ENV_SPI_MODE 0 567 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 568 #define CONFIG_ENV_OFFSET 0xF0000 569 #define CONFIG_ENV_SECT_SIZE 0x10000 570 #elif defined(CONFIG_RAMBOOT_SDCARD) 571 #define CONFIG_ENV_IS_IN_MMC 572 #define CONFIG_FSL_FIXED_MMC_LOCATION 573 #define CONFIG_ENV_SIZE 0x2000 574 #define CONFIG_SYS_MMC_ENV_DEV 0 575 #else 576 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 577 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 578 #define CONFIG_ENV_SIZE 0x2000 579 #endif 580 #else 581 #define CONFIG_ENV_IS_IN_FLASH 1 582 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 583 #define CONFIG_ENV_SIZE 0x2000 584 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 585 #endif 586 587 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 588 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 589 590 /* 591 * Command line configuration. 592 */ 593 #define CONFIG_CMD_IRQ 594 #define CONFIG_CMD_IRQ 595 #define CONFIG_CMD_REGINFO 596 597 #if defined(CONFIG_PCI) 598 #define CONFIG_CMD_PCI 599 #endif 600 601 #undef CONFIG_WATCHDOG /* watchdog disabled */ 602 603 #ifdef CONFIG_MMC 604 #define CONFIG_FSL_ESDHC 605 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 606 #define CONFIG_GENERIC_MMC 607 #endif 608 609 /* 610 * USB 611 */ 612 #define CONFIG_HAS_FSL_MPH_USB 613 #ifdef CONFIG_HAS_FSL_MPH_USB 614 #define CONFIG_USB_EHCI 615 616 #ifdef CONFIG_USB_EHCI 617 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 618 #define CONFIG_USB_EHCI_FSL 619 #endif 620 #endif 621 622 /* 623 * Miscellaneous configurable options 624 */ 625 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 626 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 627 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 628 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 629 #if defined(CONFIG_CMD_KGDB) 630 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 631 #else 632 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 633 #endif 634 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 635 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 636 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 637 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 638 639 /* 640 * For booting Linux, the board info and command line data 641 * have to be in the first 64 MB of memory, since this is 642 * the maximum mapped by the Linux kernel during initialization. 643 */ 644 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 645 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 646 647 #if defined(CONFIG_CMD_KGDB) 648 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 649 #endif 650 651 /* 652 * Environment Configuration 653 */ 654 655 /* The mac addresses for all ethernet interface */ 656 #if defined(CONFIG_TSEC_ENET) 657 #define CONFIG_HAS_ETH0 658 #define CONFIG_HAS_ETH1 659 #define CONFIG_HAS_ETH2 660 #define CONFIG_HAS_ETH3 661 #endif 662 663 #define CONFIG_IPADDR 192.168.1.254 664 665 #define CONFIG_HOSTNAME unknown 666 #define CONFIG_ROOTPATH "/opt/nfsroot" 667 #define CONFIG_BOOTFILE "uImage" 668 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 669 670 #define CONFIG_SERVERIP 192.168.1.1 671 #define CONFIG_GATEWAYIP 192.168.1.1 672 #define CONFIG_NETMASK 255.255.255.0 673 674 /* default location for tftp and bootm */ 675 #define CONFIG_LOADADDR 1000000 676 677 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 678 679 #define CONFIG_BAUDRATE 115200 680 681 #define CONFIG_EXTRA_ENV_SETTINGS \ 682 "netdev=eth0\0" \ 683 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 684 "tftpflash=tftpboot $loadaddr $uboot; " \ 685 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 686 " +$filesize; " \ 687 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 688 " +$filesize; " \ 689 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 690 " $filesize; " \ 691 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 692 " +$filesize; " \ 693 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 694 " $filesize\0" \ 695 "consoledev=ttyS0\0" \ 696 "ramdiskaddr=2000000\0" \ 697 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 698 "fdtaddr=1e00000\0" \ 699 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 700 "bdev=sda3\0" \ 701 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 702 703 #define CONFIG_HDBOOT \ 704 "setenv bootargs root=/dev/$bdev rw " \ 705 "console=$consoledev,$baudrate $othbootargs;" \ 706 "tftp $loadaddr $bootfile;" \ 707 "tftp $fdtaddr $fdtfile;" \ 708 "bootm $loadaddr - $fdtaddr" 709 710 #define CONFIG_NFSBOOTCOMMAND \ 711 "setenv bootargs root=/dev/nfs rw " \ 712 "nfsroot=$serverip:$rootpath " \ 713 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 714 "console=$consoledev,$baudrate $othbootargs;" \ 715 "tftp $loadaddr $bootfile;" \ 716 "tftp $fdtaddr $fdtfile;" \ 717 "bootm $loadaddr - $fdtaddr" 718 719 #define CONFIG_RAMBOOTCOMMAND \ 720 "setenv bootargs root=/dev/ram rw " \ 721 "console=$consoledev,$baudrate $othbootargs;" \ 722 "tftp $ramdiskaddr $ramdiskfile;" \ 723 "tftp $loadaddr $bootfile;" \ 724 "tftp $fdtaddr $fdtfile;" \ 725 "bootm $loadaddr $ramdiskaddr $fdtaddr" 726 727 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 728 729 #endif /* __CONFIG_H */ 730