1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 41 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 42 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 43 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 44 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 46 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 47 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 48 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 54 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 55 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 56 57 /* 58 * These can be toggled for performance analysis, otherwise use default. 59 */ 60 #define CONFIG_L2_CACHE /* toggle L2 cache */ 61 #define CONFIG_BTB /* toggle branch predition */ 62 63 #define CONFIG_ENABLE_36BIT_PHYS 1 64 65 #ifdef CONFIG_PHYS_64BIT 66 #define CONFIG_ADDR_MAP 1 67 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 68 #endif 69 70 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 71 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 72 73 /* 74 * Config the L2 Cache as L2 SRAM 75 */ 76 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 77 #ifdef CONFIG_PHYS_64BIT 78 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 79 #else 80 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 81 #endif 82 #define CONFIG_SYS_L2_SIZE (512 << 10) 83 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 84 85 #define CONFIG_SYS_CCSRBAR 0xffe00000 86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 87 88 #if defined(CONFIG_NAND_SPL) 89 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 90 #endif 91 92 /* DDR Setup */ 93 #define CONFIG_VERY_BIG_RAM 94 #undef CONFIG_FSL_DDR_INTERACTIVE 95 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 96 #define CONFIG_DDR_SPD 97 98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 99 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 100 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 104 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 105 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 106 107 /* I2C addresses of SPD EEPROMs */ 108 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 109 #define CONFIG_SYS_SPD_BUS_NUM 1 110 111 /* These are used when DDR doesn't use SPD. */ 112 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 113 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 114 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 116 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 117 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 118 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 119 #define CONFIG_SYS_DDR_MODE_1 0x00480432 120 #define CONFIG_SYS_DDR_MODE_2 0x00000000 121 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 122 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 123 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 124 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 125 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 126 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 127 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 128 129 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 130 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 131 #define CONFIG_SYS_DDR_SBE 0x00010000 132 133 /* Make sure required options are set */ 134 #ifndef CONFIG_SPD_EEPROM 135 #error ("CONFIG_SPD_EEPROM is required") 136 #endif 137 138 #undef CONFIG_CLOCKS_IN_MHZ 139 140 /* 141 * Memory map -- xxx -this is wrong, needs updating 142 * 143 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 144 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 145 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 146 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 147 * 148 * Localbus cacheable (TBD) 149 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 150 * 151 * Localbus non-cacheable 152 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 153 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 154 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 155 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 156 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 157 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 158 */ 159 160 /* 161 * Local Bus Definitions 162 */ 163 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 164 #ifdef CONFIG_PHYS_64BIT 165 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 166 #else 167 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 168 #endif 169 170 #define CONFIG_FLASH_BR_PRELIM \ 171 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 172 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 173 174 #define CONFIG_SYS_BR1_PRELIM \ 175 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 176 | BR_PS_16 | BR_V) 177 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 178 179 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 180 CONFIG_SYS_FLASH_BASE_PHYS } 181 #define CONFIG_SYS_FLASH_QUIET_TEST 182 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 183 184 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 185 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 186 #undef CONFIG_SYS_FLASH_CHECKSUM 187 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 189 190 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 191 #define CONFIG_SYS_RAMBOOT 192 #define CONFIG_SYS_EXTRA_ENV_RELOC 193 #else 194 #undef CONFIG_SYS_RAMBOOT 195 #endif 196 197 #define CONFIG_FLASH_CFI_DRIVER 198 #define CONFIG_SYS_FLASH_CFI 199 #define CONFIG_SYS_FLASH_EMPTY_INFO 200 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 201 202 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 203 204 #define CONFIG_HWCONFIG /* enable hwconfig */ 205 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 206 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 207 #ifdef CONFIG_PHYS_64BIT 208 #define PIXIS_BASE_PHYS 0xfffdf0000ull 209 #else 210 #define PIXIS_BASE_PHYS PIXIS_BASE 211 #endif 212 213 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 214 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 215 216 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 217 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 218 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 219 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 220 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 221 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 222 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 223 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 224 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 225 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 226 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 227 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 228 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 229 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 230 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 231 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 232 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 233 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 234 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 235 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 236 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 237 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 238 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 239 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 240 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 241 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 242 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 243 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 244 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 245 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 246 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 247 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 248 #define PIXIS_LED 0x25 /* LED Register */ 249 250 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 251 252 /* old pixis referenced names */ 253 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 254 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 255 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 256 257 #define CONFIG_SYS_INIT_RAM_LOCK 1 258 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 259 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 260 261 #define CONFIG_SYS_GBL_DATA_OFFSET \ 262 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 263 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 264 265 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 266 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 267 268 #ifndef CONFIG_NAND_SPL 269 #define CONFIG_SYS_NAND_BASE 0xffa00000 270 #ifdef CONFIG_PHYS_64BIT 271 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 272 #else 273 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 274 #endif 275 #else 276 #define CONFIG_SYS_NAND_BASE 0xfff00000 277 #ifdef CONFIG_PHYS_64BIT 278 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 279 #else 280 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 281 #endif 282 #endif 283 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 284 CONFIG_SYS_NAND_BASE + 0x40000, \ 285 CONFIG_SYS_NAND_BASE + 0x80000, \ 286 CONFIG_SYS_NAND_BASE + 0xC0000} 287 #define CONFIG_SYS_MAX_NAND_DEVICE 4 288 #define CONFIG_NAND_FSL_ELBC 1 289 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 290 291 /* NAND boot: 4K NAND loader config */ 292 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 293 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 294 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 295 #define CONFIG_SYS_NAND_U_BOOT_START \ 296 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 297 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 298 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 299 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 300 301 /* NAND flash config */ 302 #define CONFIG_SYS_NAND_BR_PRELIM \ 303 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 304 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 305 | BR_PS_8 /* Port Size = 8 bit */ \ 306 | BR_MS_FCM /* MSEL = FCM */ \ 307 | BR_V) /* valid */ 308 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 309 | OR_FCM_PGS /* Large Page*/ \ 310 | OR_FCM_CSCT \ 311 | OR_FCM_CST \ 312 | OR_FCM_CHT \ 313 | OR_FCM_SCY_1 \ 314 | OR_FCM_TRLX \ 315 | OR_FCM_EHTR) 316 317 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 318 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 319 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 320 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 321 322 #define CONFIG_SYS_BR4_PRELIM \ 323 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 329 #define CONFIG_SYS_BR5_PRELIM \ 330 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 331 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 332 | BR_PS_8 /* Port Size = 8 bit */ \ 333 | BR_MS_FCM /* MSEL = FCM */ \ 334 | BR_V) /* valid */ 335 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 336 337 #define CONFIG_SYS_BR6_PRELIM \ 338 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 339 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 340 | BR_PS_8 /* Port Size = 8 bit */ \ 341 | BR_MS_FCM /* MSEL = FCM */ \ 342 | BR_V) /* valid */ 343 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 344 345 /* Serial Port - controlled on board with jumper J8 346 * open - index 2 347 * shorted - index 1 348 */ 349 #define CONFIG_CONS_INDEX 1 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 353 #ifdef CONFIG_NAND_SPL 354 #define CONFIG_NS16550_MIN_FUNCTIONS 355 #endif 356 357 #define CONFIG_SYS_BAUDRATE_TABLE \ 358 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 359 360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 362 363 /* 364 * I2C 365 */ 366 #define CONFIG_SYS_I2C 367 #define CONFIG_SYS_I2C_FSL 368 #define CONFIG_SYS_FSL_I2C_SPEED 400000 369 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 370 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 371 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 372 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 373 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 374 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 375 376 /* 377 * I2C2 EEPROM 378 */ 379 #define CONFIG_ID_EEPROM 380 #ifdef CONFIG_ID_EEPROM 381 #define CONFIG_SYS_I2C_EEPROM_NXID 382 #endif 383 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 384 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 385 #define CONFIG_SYS_EEPROM_BUS_NUM 1 386 387 /* 388 * eSPI - Enhanced SPI 389 */ 390 #define CONFIG_HARD_SPI 391 392 #if defined(CONFIG_SPI_FLASH) 393 #define CONFIG_SF_DEFAULT_SPEED 10000000 394 #define CONFIG_SF_DEFAULT_MODE 0 395 #endif 396 397 /* 398 * General PCI 399 * Memory space is mapped 1-1, but I/O space must start from 0. 400 */ 401 402 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 403 #ifdef CONFIG_PHYS_64BIT 404 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 405 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 406 #else 407 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 408 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 409 #endif 410 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 411 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 412 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 413 #ifdef CONFIG_PHYS_64BIT 414 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 415 #else 416 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 417 #endif 418 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 419 420 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 421 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 422 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 423 #ifdef CONFIG_PHYS_64BIT 424 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 425 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 426 #else 427 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 429 #endif 430 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 431 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 432 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 435 #else 436 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 437 #endif 438 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 439 440 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 441 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 442 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 445 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 446 #else 447 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 449 #endif 450 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 451 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 452 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 453 #ifdef CONFIG_PHYS_64BIT 454 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 455 #else 456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 457 #endif 458 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 459 460 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 461 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 462 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 465 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 466 #else 467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 469 #endif 470 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 471 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 472 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 473 #ifdef CONFIG_PHYS_64BIT 474 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 475 #else 476 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 477 #endif 478 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 479 480 #if defined(CONFIG_PCI) 481 /*PCIE video card used*/ 482 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 483 484 /*PCI video card used*/ 485 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 486 487 /* video */ 488 489 #if defined(CONFIG_VIDEO) 490 #define CONFIG_BIOSEMU 491 #define CONFIG_ATI_RADEON_FB 492 #define CONFIG_VIDEO_LOGO 493 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 494 #endif 495 496 #undef CONFIG_EEPRO100 497 #undef CONFIG_TULIP 498 499 #ifndef CONFIG_PCI_PNP 500 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 501 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 502 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 503 #endif 504 505 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 506 507 #endif /* CONFIG_PCI */ 508 509 /* SATA */ 510 #define CONFIG_SYS_SATA_MAX_DEVICE 2 511 #define CONFIG_SATA1 512 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 513 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 514 #define CONFIG_SATA2 515 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 516 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 517 518 #ifdef CONFIG_FSL_SATA 519 #define CONFIG_LBA48 520 #endif 521 522 #if defined(CONFIG_TSEC_ENET) 523 524 #define CONFIG_MII 1 /* MII PHY management */ 525 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 526 #define CONFIG_TSEC1 1 527 #define CONFIG_TSEC1_NAME "eTSEC1" 528 #define CONFIG_TSEC3 1 529 #define CONFIG_TSEC3_NAME "eTSEC3" 530 531 #define CONFIG_FSL_SGMII_RISER 1 532 #define SGMII_RISER_PHY_OFFSET 0x1c 533 534 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 535 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 536 537 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 538 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 539 540 #define TSEC1_PHYIDX 0 541 #define TSEC3_PHYIDX 0 542 543 #define CONFIG_ETHPRIME "eTSEC1" 544 545 #endif /* CONFIG_TSEC_ENET */ 546 547 /* 548 * Environment 549 */ 550 551 #if defined(CONFIG_SYS_RAMBOOT) 552 #if defined(CONFIG_RAMBOOT_SPIFLASH) 553 #define CONFIG_ENV_SPI_BUS 0 554 #define CONFIG_ENV_SPI_CS 0 555 #define CONFIG_ENV_SPI_MAX_HZ 10000000 556 #define CONFIG_ENV_SPI_MODE 0 557 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 558 #define CONFIG_ENV_OFFSET 0xF0000 559 #define CONFIG_ENV_SECT_SIZE 0x10000 560 #elif defined(CONFIG_RAMBOOT_SDCARD) 561 #define CONFIG_FSL_FIXED_MMC_LOCATION 562 #define CONFIG_ENV_SIZE 0x2000 563 #define CONFIG_SYS_MMC_ENV_DEV 0 564 #else 565 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 566 #define CONFIG_ENV_SIZE 0x2000 567 #endif 568 #else 569 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 570 #define CONFIG_ENV_SIZE 0x2000 571 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 572 #endif 573 574 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 575 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 576 577 #undef CONFIG_WATCHDOG /* watchdog disabled */ 578 579 #ifdef CONFIG_MMC 580 #define CONFIG_FSL_ESDHC 581 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 582 #endif 583 584 /* 585 * USB 586 */ 587 #define CONFIG_HAS_FSL_MPH_USB 588 #ifdef CONFIG_HAS_FSL_MPH_USB 589 #ifdef CONFIG_USB_EHCI_HCD 590 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 591 #define CONFIG_USB_EHCI_FSL 592 #endif 593 #endif 594 595 /* 596 * Miscellaneous configurable options 597 */ 598 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 599 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 600 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 601 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 602 603 /* 604 * For booting Linux, the board info and command line data 605 * have to be in the first 64 MB of memory, since this is 606 * the maximum mapped by the Linux kernel during initialization. 607 */ 608 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 609 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 610 611 #if defined(CONFIG_CMD_KGDB) 612 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 613 #endif 614 615 /* 616 * Environment Configuration 617 */ 618 619 /* The mac addresses for all ethernet interface */ 620 #if defined(CONFIG_TSEC_ENET) 621 #define CONFIG_HAS_ETH0 622 #define CONFIG_HAS_ETH1 623 #define CONFIG_HAS_ETH2 624 #define CONFIG_HAS_ETH3 625 #endif 626 627 #define CONFIG_IPADDR 192.168.1.254 628 629 #define CONFIG_HOSTNAME unknown 630 #define CONFIG_ROOTPATH "/opt/nfsroot" 631 #define CONFIG_BOOTFILE "uImage" 632 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 633 634 #define CONFIG_SERVERIP 192.168.1.1 635 #define CONFIG_GATEWAYIP 192.168.1.1 636 #define CONFIG_NETMASK 255.255.255.0 637 638 /* default location for tftp and bootm */ 639 #define CONFIG_LOADADDR 1000000 640 641 #define CONFIG_EXTRA_ENV_SETTINGS \ 642 "netdev=eth0\0" \ 643 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 644 "tftpflash=tftpboot $loadaddr $uboot; " \ 645 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 646 " +$filesize; " \ 647 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 648 " +$filesize; " \ 649 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 650 " $filesize; " \ 651 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 652 " +$filesize; " \ 653 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 654 " $filesize\0" \ 655 "consoledev=ttyS0\0" \ 656 "ramdiskaddr=2000000\0" \ 657 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 658 "fdtaddr=1e00000\0" \ 659 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 660 "bdev=sda3\0" \ 661 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 662 663 #define CONFIG_HDBOOT \ 664 "setenv bootargs root=/dev/$bdev rw " \ 665 "console=$consoledev,$baudrate $othbootargs;" \ 666 "tftp $loadaddr $bootfile;" \ 667 "tftp $fdtaddr $fdtfile;" \ 668 "bootm $loadaddr - $fdtaddr" 669 670 #define CONFIG_NFSBOOTCOMMAND \ 671 "setenv bootargs root=/dev/nfs rw " \ 672 "nfsroot=$serverip:$rootpath " \ 673 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 674 "console=$consoledev,$baudrate $othbootargs;" \ 675 "tftp $loadaddr $bootfile;" \ 676 "tftp $fdtaddr $fdtfile;" \ 677 "bootm $loadaddr - $fdtaddr" 678 679 #define CONFIG_RAMBOOTCOMMAND \ 680 "setenv bootargs root=/dev/ram rw " \ 681 "console=$consoledev,$baudrate $othbootargs;" \ 682 "tftp $ramdiskaddr $ramdiskfile;" \ 683 "tftp $loadaddr $bootfile;" \ 684 "tftp $fdtaddr $fdtfile;" \ 685 "bootm $loadaddr $ramdiskaddr $fdtaddr" 686 687 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 688 689 #endif /* __CONFIG_H */ 690