1 /* 2 * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_36BIT 33 #define CONFIG_PHYS_64BIT 1 34 #endif 35 36 #ifdef CONFIG_NAND 37 #define CONFIG_NAND_U_BOOT 1 38 #define CONFIG_RAMBOOT_NAND 1 39 #ifdef CONFIG_NAND_SPL 40 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42 #else 43 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 44 #endif /* CONFIG_NAND_SPL */ 45 #endif 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RAMBOOT_SDCARD 1 49 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 50 #endif 51 52 #ifdef CONFIG_SPIFLASH 53 #define CONFIG_RAMBOOT_SPIFLASH 1 54 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 55 #endif 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0xeff80000 59 #endif 60 61 #ifndef CONFIG_SYS_MONITOR_BASE 62 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 63 #endif 64 65 /* High Level Configuration Options */ 66 #define CONFIG_BOOKE 1 /* BOOKE */ 67 #define CONFIG_E500 1 /* BOOKE e500 family */ 68 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 69 #define CONFIG_MPC8536 1 70 #define CONFIG_MPC8536DS 1 71 72 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 73 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 74 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 75 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 76 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 77 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 78 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 79 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 80 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 81 #define CONFIG_SYS_HAS_SERDES /* has SERDES */ 82 83 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 84 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 85 86 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 87 #define CONFIG_ENV_OVERWRITE 88 89 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 90 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 91 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 92 93 /* 94 * These can be toggled for performance analysis, otherwise use default. 95 */ 96 #define CONFIG_L2_CACHE /* toggle L2 cache */ 97 #define CONFIG_BTB /* toggle branch predition */ 98 99 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 100 101 #define CONFIG_ENABLE_36BIT_PHYS 1 102 103 #ifdef CONFIG_PHYS_64BIT 104 #define CONFIG_ADDR_MAP 1 105 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 106 #endif 107 108 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 109 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 110 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 111 112 /* 113 * Config the L2 Cache as L2 SRAM 114 */ 115 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 116 #ifdef CONFIG_PHYS_64BIT 117 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 118 #else 119 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 120 #endif 121 #define CONFIG_SYS_L2_SIZE (512 << 10) 122 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 123 124 /* 125 * Base addresses -- Note these are effective addresses where the 126 * actual resources get mapped (not physical addresses) 127 */ 128 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 129 #ifdef CONFIG_PHYS_64BIT 130 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 131 #else 132 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 133 #endif 134 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 135 136 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 137 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 138 #else 139 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 140 #endif 141 142 /* DDR Setup */ 143 #define CONFIG_VERY_BIG_RAM 144 #define CONFIG_FSL_DDR2 145 #undef CONFIG_FSL_DDR_INTERACTIVE 146 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 147 #define CONFIG_DDR_SPD 148 #undef CONFIG_DDR_DLL 149 150 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 151 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 152 153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 155 156 #define CONFIG_NUM_DDR_CONTROLLERS 1 157 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 158 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 159 160 /* I2C addresses of SPD EEPROMs */ 161 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 162 #define CONFIG_SYS_SPD_BUS_NUM 1 163 164 /* These are used when DDR doesn't use SPD. */ 165 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 166 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 167 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 168 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 169 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 170 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 171 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 172 #define CONFIG_SYS_DDR_MODE_1 0x00480432 173 #define CONFIG_SYS_DDR_MODE_2 0x00000000 174 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 175 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 176 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 177 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 178 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 179 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 180 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 181 182 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 183 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 184 #define CONFIG_SYS_DDR_SBE 0x00010000 185 186 /* Make sure required options are set */ 187 #ifndef CONFIG_SPD_EEPROM 188 #error ("CONFIG_SPD_EEPROM is required") 189 #endif 190 191 #undef CONFIG_CLOCKS_IN_MHZ 192 193 194 /* 195 * Memory map -- xxx -this is wrong, needs updating 196 * 197 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 198 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 199 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 200 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 201 * 202 * Localbus cacheable (TBD) 203 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 204 * 205 * Localbus non-cacheable 206 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 207 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 208 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 209 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 210 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 211 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 212 */ 213 214 /* 215 * Local Bus Definitions 216 */ 217 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 218 #ifdef CONFIG_PHYS_64BIT 219 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 220 #else 221 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 222 #endif 223 224 #define CONFIG_FLASH_BR_PRELIM \ 225 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 226 | BR_PS_16 | BR_V) 227 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 228 229 #define CONFIG_SYS_BR1_PRELIM \ 230 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 231 | BR_PS_16 | BR_V) 232 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 233 234 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 235 CONFIG_SYS_FLASH_BASE_PHYS } 236 #define CONFIG_SYS_FLASH_QUIET_TEST 237 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 238 239 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 240 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 241 #undef CONFIG_SYS_FLASH_CHECKSUM 242 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 243 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 244 245 #if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \ 246 defined(CONFIG_RAMBOOT_SPIFLASH) 247 #define CONFIG_SYS_RAMBOOT 248 #define CONFIG_SYS_EXTRA_ENV_RELOC 249 #else 250 #undef CONFIG_SYS_RAMBOOT 251 #endif 252 253 #define CONFIG_FLASH_CFI_DRIVER 254 #define CONFIG_SYS_FLASH_CFI 255 #define CONFIG_SYS_FLASH_EMPTY_INFO 256 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 257 258 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 259 260 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 261 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 262 #ifdef CONFIG_PHYS_64BIT 263 #define PIXIS_BASE_PHYS 0xfffdf0000ull 264 #else 265 #define PIXIS_BASE_PHYS PIXIS_BASE 266 #endif 267 268 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 269 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 270 271 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 272 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 273 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 274 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 275 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 276 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 277 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 278 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 279 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 280 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 281 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 282 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 283 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 284 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 285 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 286 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 287 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 288 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 289 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 290 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 291 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 292 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 293 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 294 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 295 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 296 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 297 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 298 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 299 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 300 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 301 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 302 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 303 #define PIXIS_LED 0x25 /* LED Register */ 304 305 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 306 307 /* old pixis referenced names */ 308 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 309 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 310 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 311 312 #define CONFIG_SYS_INIT_RAM_LOCK 1 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 315 316 #define CONFIG_SYS_GBL_DATA_OFFSET \ 317 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 318 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 319 320 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 321 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 322 323 #ifndef CONFIG_NAND_SPL 324 #define CONFIG_SYS_NAND_BASE 0xffa00000 325 #ifdef CONFIG_PHYS_64BIT 326 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 327 #else 328 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 329 #endif 330 #else 331 #define CONFIG_SYS_NAND_BASE 0xfff00000 332 #ifdef CONFIG_PHYS_64BIT 333 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 334 #else 335 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 336 #endif 337 #endif 338 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 339 CONFIG_SYS_NAND_BASE + 0x40000, \ 340 CONFIG_SYS_NAND_BASE + 0x80000, \ 341 CONFIG_SYS_NAND_BASE + 0xC0000} 342 #define CONFIG_SYS_MAX_NAND_DEVICE 4 343 #define CONFIG_MTD_NAND_VERIFY_WRITE 344 #define CONFIG_CMD_NAND 1 345 #define CONFIG_NAND_FSL_ELBC 1 346 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 347 348 /* NAND boot: 4K NAND loader config */ 349 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 350 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 351 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 352 #define CONFIG_SYS_NAND_U_BOOT_START \ 353 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 354 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 355 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 356 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 357 358 /* NAND flash config */ 359 #define CONFIG_NAND_BR_PRELIM \ 360 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 361 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 362 | BR_PS_8 /* Port Size = 8 bit */ \ 363 | BR_MS_FCM /* MSEL = FCM */ \ 364 | BR_V) /* valid */ 365 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 366 | OR_FCM_PGS /* Large Page*/ \ 367 | OR_FCM_CSCT \ 368 | OR_FCM_CST \ 369 | OR_FCM_CHT \ 370 | OR_FCM_SCY_1 \ 371 | OR_FCM_TRLX \ 372 | OR_FCM_EHTR) 373 374 #ifdef CONFIG_RAMBOOT_NAND 375 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 376 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 377 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 378 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 379 #else 380 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 381 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 382 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 383 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 384 #endif 385 386 #define CONFIG_SYS_BR4_PRELIM \ 387 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 388 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 389 | BR_PS_8 /* Port Size = 8 bit */ \ 390 | BR_MS_FCM /* MSEL = FCM */ \ 391 | BR_V) /* valid */ 392 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 393 #define CONFIG_SYS_BR5_PRELIM \ 394 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 395 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 396 | BR_PS_8 /* Port Size = 8 bit */ \ 397 | BR_MS_FCM /* MSEL = FCM */ \ 398 | BR_V) /* valid */ 399 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 400 401 #define CONFIG_SYS_BR6_PRELIM \ 402 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 403 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 404 | BR_PS_8 /* Port Size = 8 bit */ \ 405 | BR_MS_FCM /* MSEL = FCM */ \ 406 | BR_V) /* valid */ 407 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 408 409 /* Serial Port - controlled on board with jumper J8 410 * open - index 2 411 * shorted - index 1 412 */ 413 #define CONFIG_CONS_INDEX 1 414 #define CONFIG_SYS_NS16550 415 #define CONFIG_SYS_NS16550_SERIAL 416 #define CONFIG_SYS_NS16550_REG_SIZE 1 417 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 418 #ifdef CONFIG_NAND_SPL 419 #define CONFIG_NS16550_MIN_FUNCTIONS 420 #endif 421 422 #define CONFIG_SYS_BAUDRATE_TABLE \ 423 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 424 425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 427 428 /* Use the HUSH parser */ 429 #define CONFIG_SYS_HUSH_PARSER 430 #ifdef CONFIG_SYS_HUSH_PARSER 431 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 432 #endif 433 434 /* 435 * Pass open firmware flat tree 436 */ 437 #define CONFIG_OF_LIBFDT 1 438 #define CONFIG_OF_BOARD_SETUP 1 439 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 440 441 /* 442 * I2C 443 */ 444 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 445 #define CONFIG_HARD_I2C /* I2C with hardware support */ 446 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 447 #define CONFIG_I2C_MULTI_BUS 448 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 449 #define CONFIG_SYS_I2C_SLAVE 0x7F 450 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 451 #define CONFIG_SYS_I2C_OFFSET 0x3000 452 #define CONFIG_SYS_I2C2_OFFSET 0x3100 453 454 /* 455 * I2C2 EEPROM 456 */ 457 #define CONFIG_ID_EEPROM 458 #ifdef CONFIG_ID_EEPROM 459 #define CONFIG_SYS_I2C_EEPROM_NXID 460 #endif 461 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 462 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 463 #define CONFIG_SYS_EEPROM_BUS_NUM 1 464 465 /* 466 * General PCI 467 * Memory space is mapped 1-1, but I/O space must start from 0. 468 */ 469 470 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 471 #ifdef CONFIG_PHYS_64BIT 472 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 473 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 474 #else 475 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 476 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 477 #endif 478 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 479 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 480 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 481 #ifdef CONFIG_PHYS_64BIT 482 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 483 #else 484 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 485 #endif 486 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 487 488 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 489 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 492 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 493 #else 494 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 495 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 496 #endif 497 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 498 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 499 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 500 #ifdef CONFIG_PHYS_64BIT 501 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 502 #else 503 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 504 #endif 505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 506 507 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 508 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 509 #ifdef CONFIG_PHYS_64BIT 510 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 511 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 512 #else 513 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 514 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 515 #endif 516 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 517 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 518 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 519 #ifdef CONFIG_PHYS_64BIT 520 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 521 #else 522 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 523 #endif 524 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 525 526 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 527 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 528 #ifdef CONFIG_PHYS_64BIT 529 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 530 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 531 #else 532 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 533 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 534 #endif 535 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 536 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 537 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 540 #else 541 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 542 #endif 543 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 544 545 #if defined(CONFIG_PCI) 546 547 #define CONFIG_NET_MULTI 548 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 549 550 /*PCIE video card used*/ 551 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 552 553 /*PCI video card used*/ 554 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 555 556 /* video */ 557 #define CONFIG_VIDEO 558 559 #if defined(CONFIG_VIDEO) 560 #define CONFIG_BIOSEMU 561 #define CONFIG_CFB_CONSOLE 562 #define CONFIG_VIDEO_SW_CURSOR 563 #define CONFIG_VGA_AS_SINGLE_DEVICE 564 #define CONFIG_ATI_RADEON_FB 565 #define CONFIG_VIDEO_LOGO 566 /*#define CONFIG_CONSOLE_CURSOR*/ 567 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 568 #endif 569 570 #undef CONFIG_EEPRO100 571 #undef CONFIG_TULIP 572 #undef CONFIG_RTL8139 573 574 #ifndef CONFIG_PCI_PNP 575 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 576 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 577 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 578 #endif 579 580 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 581 582 #endif /* CONFIG_PCI */ 583 584 /* SATA */ 585 #define CONFIG_LIBATA 586 #define CONFIG_FSL_SATA 587 588 #define CONFIG_SYS_SATA_MAX_DEVICE 2 589 #define CONFIG_SATA1 590 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 591 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 592 #define CONFIG_SATA2 593 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 594 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 595 596 #ifdef CONFIG_FSL_SATA 597 #define CONFIG_LBA48 598 #define CONFIG_CMD_SATA 599 #define CONFIG_DOS_PARTITION 600 #define CONFIG_CMD_EXT2 601 #endif 602 603 #if defined(CONFIG_TSEC_ENET) 604 605 #ifndef CONFIG_NET_MULTI 606 #define CONFIG_NET_MULTI 1 607 #endif 608 609 #define CONFIG_MII 1 /* MII PHY management */ 610 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 611 #define CONFIG_TSEC1 1 612 #define CONFIG_TSEC1_NAME "eTSEC1" 613 #define CONFIG_TSEC3 1 614 #define CONFIG_TSEC3_NAME "eTSEC3" 615 616 #define CONFIG_FSL_SGMII_RISER 1 617 #define SGMII_RISER_PHY_OFFSET 0x1c 618 619 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 620 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 621 622 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 623 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 624 625 #define TSEC1_PHYIDX 0 626 #define TSEC3_PHYIDX 0 627 628 #define CONFIG_ETHPRIME "eTSEC1" 629 630 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 631 632 #endif /* CONFIG_TSEC_ENET */ 633 634 /* 635 * Environment 636 */ 637 638 #if defined(CONFIG_SYS_RAMBOOT) 639 #if defined(CONFIG_RAMBOOT_NAND) 640 #define CONFIG_ENV_IS_IN_NAND 1 641 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 642 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 643 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 644 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 645 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 646 #define CONFIG_ENV_SIZE 0x2000 647 #endif 648 #else 649 #define CONFIG_ENV_IS_IN_FLASH 1 650 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 651 #define CONFIG_ENV_ADDR 0xfff80000 652 #else 653 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 654 #endif 655 #define CONFIG_ENV_SIZE 0x2000 656 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 657 #endif 658 659 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 660 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 661 662 /* 663 * Command line configuration. 664 */ 665 #include <config_cmd_default.h> 666 667 #define CONFIG_CMD_IRQ 668 #define CONFIG_CMD_PING 669 #define CONFIG_CMD_I2C 670 #define CONFIG_CMD_MII 671 #define CONFIG_CMD_ELF 672 #define CONFIG_CMD_IRQ 673 #define CONFIG_CMD_SETEXPR 674 #define CONFIG_CMD_REGINFO 675 676 #if defined(CONFIG_PCI) 677 #define CONFIG_CMD_PCI 678 #define CONFIG_CMD_NET 679 #endif 680 681 #undef CONFIG_WATCHDOG /* watchdog disabled */ 682 683 #define CONFIG_MMC 1 684 685 #ifdef CONFIG_MMC 686 #define CONFIG_FSL_ESDHC 687 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 688 #define CONFIG_CMD_MMC 689 #define CONFIG_GENERIC_MMC 690 #define CONFIG_CMD_EXT2 691 #define CONFIG_CMD_FAT 692 #define CONFIG_DOS_PARTITION 693 #endif 694 695 /* 696 * Miscellaneous configurable options 697 */ 698 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 699 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 700 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 701 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 702 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 703 #if defined(CONFIG_CMD_KGDB) 704 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 705 #else 706 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 707 #endif 708 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 709 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 710 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 711 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 712 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 713 714 /* 715 * For booting Linux, the board info and command line data 716 * have to be in the first 16 MB of memory, since this is 717 * the maximum mapped by the Linux kernel during initialization. 718 */ 719 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 720 721 #if defined(CONFIG_CMD_KGDB) 722 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 723 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 724 #endif 725 726 /* 727 * Environment Configuration 728 */ 729 730 /* The mac addresses for all ethernet interface */ 731 #if defined(CONFIG_TSEC_ENET) 732 #define CONFIG_HAS_ETH0 733 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 734 #define CONFIG_HAS_ETH1 735 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 736 #define CONFIG_HAS_ETH2 737 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 738 #define CONFIG_HAS_ETH3 739 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 740 #endif 741 742 #define CONFIG_IPADDR 192.168.1.254 743 744 #define CONFIG_HOSTNAME unknown 745 #define CONFIG_ROOTPATH /opt/nfsroot 746 #define CONFIG_BOOTFILE uImage 747 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 748 749 #define CONFIG_SERVERIP 192.168.1.1 750 #define CONFIG_GATEWAYIP 192.168.1.1 751 #define CONFIG_NETMASK 255.255.255.0 752 753 /* default location for tftp and bootm */ 754 #define CONFIG_LOADADDR 1000000 755 756 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 757 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 758 759 #define CONFIG_BAUDRATE 115200 760 761 #define CONFIG_EXTRA_ENV_SETTINGS \ 762 "netdev=eth0\0" \ 763 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 764 "tftpflash=tftpboot $loadaddr $uboot; " \ 765 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 766 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 767 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 768 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 769 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 770 "consoledev=ttyS0\0" \ 771 "ramdiskaddr=2000000\0" \ 772 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 773 "fdtaddr=c00000\0" \ 774 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 775 "bdev=sda3\0" \ 776 "usb_phy_type=ulpi\0" 777 778 #define CONFIG_HDBOOT \ 779 "setenv bootargs root=/dev/$bdev rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "tftp $loadaddr $bootfile;" \ 782 "tftp $fdtaddr $fdtfile;" \ 783 "bootm $loadaddr - $fdtaddr" 784 785 #define CONFIG_NFSBOOTCOMMAND \ 786 "setenv bootargs root=/dev/nfs rw " \ 787 "nfsroot=$serverip:$rootpath " \ 788 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 789 "console=$consoledev,$baudrate $othbootargs;" \ 790 "tftp $loadaddr $bootfile;" \ 791 "tftp $fdtaddr $fdtfile;" \ 792 "bootm $loadaddr - $fdtaddr" 793 794 #define CONFIG_RAMBOOTCOMMAND \ 795 "setenv bootargs root=/dev/ram rw " \ 796 "console=$consoledev,$baudrate $othbootargs;" \ 797 "tftp $ramdiskaddr $ramdiskfile;" \ 798 "tftp $loadaddr $bootfile;" \ 799 "tftp $fdtaddr $fdtfile;" \ 800 "bootm $loadaddr $ramdiskaddr $fdtaddr" 801 802 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 803 804 #endif /* __CONFIG_H */ 805