1 /* 2 * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8536ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_36BIT 33 #define CONFIG_PHYS_64BIT 1 34 #endif 35 36 #ifdef CONFIG_NAND 37 #define CONFIG_NAND_U_BOOT 1 38 #define CONFIG_RAMBOOT_NAND 1 39 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 40 #endif 41 42 #ifdef CONFIG_SDCARD 43 #define CONFIG_RAMBOOT_SDCARD 1 44 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 45 #endif 46 47 #ifdef CONFIG_SPIFLASH 48 #define CONFIG_RAMBOOT_SPIFLASH 1 49 #define CONFIG_SYS_TEXT_BASE 0xf8f80000 50 #endif 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff80000 54 #endif 55 56 /* High Level Configuration Options */ 57 #define CONFIG_BOOKE 1 /* BOOKE */ 58 #define CONFIG_E500 1 /* BOOKE e500 family */ 59 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 60 #define CONFIG_MPC8536 1 61 #define CONFIG_MPC8536DS 1 62 63 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 64 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 65 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 66 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 67 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 68 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 69 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 70 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 71 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 72 #define CONFIG_SYS_HAS_SERDES /* has SERDES */ 73 74 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 75 #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ 76 77 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 78 #define CONFIG_ENV_OVERWRITE 79 80 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 81 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 82 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 83 84 /* 85 * These can be toggled for performance analysis, otherwise use default. 86 */ 87 #define CONFIG_L2_CACHE /* toggle L2 cache */ 88 #define CONFIG_BTB /* toggle branch predition */ 89 90 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 91 92 #define CONFIG_ENABLE_36BIT_PHYS 1 93 94 #ifdef CONFIG_PHYS_64BIT 95 #define CONFIG_ADDR_MAP 1 96 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 97 #endif 98 99 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 100 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 101 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 102 103 /* 104 * Config the L2 Cache as L2 SRAM 105 */ 106 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 107 #ifdef CONFIG_PHYS_64BIT 108 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 109 #else 110 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 111 #endif 112 #define CONFIG_SYS_L2_SIZE (512 << 10) 113 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 114 115 /* 116 * Base addresses -- Note these are effective addresses where the 117 * actual resources get mapped (not physical addresses) 118 */ 119 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 120 #ifdef CONFIG_PHYS_64BIT 121 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 122 #else 123 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 124 #endif 125 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 126 127 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 128 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 129 #else 130 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 131 #endif 132 133 /* DDR Setup */ 134 #define CONFIG_VERY_BIG_RAM 135 #define CONFIG_FSL_DDR2 136 #undef CONFIG_FSL_DDR_INTERACTIVE 137 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 138 #define CONFIG_DDR_SPD 139 #undef CONFIG_DDR_DLL 140 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 142 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 143 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_NUM_DDR_CONTROLLERS 1 148 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 150 151 /* I2C addresses of SPD EEPROMs */ 152 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 153 #define CONFIG_SYS_SPD_BUS_NUM 1 154 155 /* These are used when DDR doesn't use SPD. */ 156 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 157 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 158 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 159 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 160 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 161 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 162 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 163 #define CONFIG_SYS_DDR_MODE_1 0x00480432 164 #define CONFIG_SYS_DDR_MODE_2 0x00000000 165 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 166 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 167 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 168 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 169 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 170 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 171 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 172 173 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 174 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 175 #define CONFIG_SYS_DDR_SBE 0x00010000 176 177 /* Make sure required options are set */ 178 #ifndef CONFIG_SPD_EEPROM 179 #error ("CONFIG_SPD_EEPROM is required") 180 #endif 181 182 #undef CONFIG_CLOCKS_IN_MHZ 183 184 185 /* 186 * Memory map -- xxx -this is wrong, needs updating 187 * 188 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 189 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 190 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 191 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 192 * 193 * Localbus cacheable (TBD) 194 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 195 * 196 * Localbus non-cacheable 197 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 198 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 199 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 200 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 201 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 202 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 203 */ 204 205 /* 206 * Local Bus Definitions 207 */ 208 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 209 #ifdef CONFIG_PHYS_64BIT 210 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 211 #else 212 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 213 #endif 214 215 #define CONFIG_FLASH_BR_PRELIM \ 216 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 217 | BR_PS_16 | BR_V) 218 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 219 220 #define CONFIG_SYS_BR1_PRELIM \ 221 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 222 | BR_PS_16 | BR_V) 223 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 224 225 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 226 CONFIG_SYS_FLASH_BASE_PHYS } 227 #define CONFIG_SYS_FLASH_QUIET_TEST 228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 229 230 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 232 #undef CONFIG_SYS_FLASH_CHECKSUM 233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 235 236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 237 238 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ 239 || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 240 #define CONFIG_SYS_RAMBOOT 241 #else 242 #undef CONFIG_SYS_RAMBOOT 243 #endif 244 245 #define CONFIG_FLASH_CFI_DRIVER 246 #define CONFIG_SYS_FLASH_CFI 247 #define CONFIG_SYS_FLASH_EMPTY_INFO 248 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 249 250 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 251 252 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 253 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 254 #ifdef CONFIG_PHYS_64BIT 255 #define PIXIS_BASE_PHYS 0xfffdf0000ull 256 #else 257 #define PIXIS_BASE_PHYS PIXIS_BASE 258 #endif 259 260 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 261 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 262 263 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 264 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 265 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 266 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 267 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 268 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 269 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 270 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 271 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 272 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 273 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 274 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 275 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 276 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 277 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 278 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 279 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 280 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 281 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 282 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 283 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 284 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 285 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 286 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 287 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 288 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 289 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 290 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 291 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 292 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 293 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 294 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 295 #define PIXIS_LED 0x25 /* LED Register */ 296 297 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 298 299 /* old pixis referenced names */ 300 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 301 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 302 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 303 304 #define CONFIG_SYS_INIT_RAM_LOCK 1 305 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 306 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 307 308 #define CONFIG_SYS_GBL_DATA_OFFSET \ 309 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 310 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 311 312 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 313 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 314 315 #ifndef CONFIG_NAND_SPL 316 #define CONFIG_SYS_NAND_BASE 0xffa00000 317 #ifdef CONFIG_PHYS_64BIT 318 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 319 #else 320 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 321 #endif 322 #else 323 #define CONFIG_SYS_NAND_BASE 0xfff00000 324 #ifdef CONFIG_PHYS_64BIT 325 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 326 #else 327 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 328 #endif 329 #endif 330 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 331 CONFIG_SYS_NAND_BASE + 0x40000, \ 332 CONFIG_SYS_NAND_BASE + 0x80000, \ 333 CONFIG_SYS_NAND_BASE + 0xC0000} 334 #define CONFIG_SYS_MAX_NAND_DEVICE 4 335 #define CONFIG_MTD_NAND_VERIFY_WRITE 336 #define CONFIG_CMD_NAND 1 337 #define CONFIG_NAND_FSL_ELBC 1 338 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 339 340 /* NAND boot: 4K NAND loader config */ 341 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 342 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 343 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 344 #define CONFIG_SYS_NAND_U_BOOT_START \ 345 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 346 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 347 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 348 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 349 350 /* NAND flash config */ 351 #define CONFIG_NAND_BR_PRELIM \ 352 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 353 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 354 | BR_PS_8 /* Port Size = 8 bit */ \ 355 | BR_MS_FCM /* MSEL = FCM */ \ 356 | BR_V) /* valid */ 357 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 358 | OR_FCM_PGS /* Large Page*/ \ 359 | OR_FCM_CSCT \ 360 | OR_FCM_CST \ 361 | OR_FCM_CHT \ 362 | OR_FCM_SCY_1 \ 363 | OR_FCM_TRLX \ 364 | OR_FCM_EHTR) 365 366 #ifdef CONFIG_RAMBOOT_NAND 367 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 368 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 369 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 370 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 371 #else 372 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 373 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 374 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 375 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 376 #endif 377 378 #define CONFIG_SYS_BR4_PRELIM \ 379 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ 380 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 381 | BR_PS_8 /* Port Size = 8 bit */ \ 382 | BR_MS_FCM /* MSEL = FCM */ \ 383 | BR_V) /* valid */ 384 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 385 #define CONFIG_SYS_BR5_PRELIM \ 386 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ 387 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 388 | BR_PS_8 /* Port Size = 8 bit */ \ 389 | BR_MS_FCM /* MSEL = FCM */ \ 390 | BR_V) /* valid */ 391 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 392 393 #define CONFIG_SYS_BR6_PRELIM \ 394 (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ 395 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 396 | BR_PS_8 /* Port Size = 8 bit */ \ 397 | BR_MS_FCM /* MSEL = FCM */ \ 398 | BR_V) /* valid */ 399 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 400 401 /* Serial Port - controlled on board with jumper J8 402 * open - index 2 403 * shorted - index 1 404 */ 405 #define CONFIG_CONS_INDEX 1 406 #define CONFIG_SYS_NS16550 407 #define CONFIG_SYS_NS16550_SERIAL 408 #define CONFIG_SYS_NS16550_REG_SIZE 1 409 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 410 #ifdef CONFIG_NAND_SPL 411 #define CONFIG_NS16550_MIN_FUNCTIONS 412 #endif 413 414 #define CONFIG_SYS_BAUDRATE_TABLE \ 415 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 416 417 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 418 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 419 420 /* Use the HUSH parser */ 421 #define CONFIG_SYS_HUSH_PARSER 422 #ifdef CONFIG_SYS_HUSH_PARSER 423 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 424 #endif 425 426 /* 427 * Pass open firmware flat tree 428 */ 429 #define CONFIG_OF_LIBFDT 1 430 #define CONFIG_OF_BOARD_SETUP 1 431 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 432 433 /* 434 * I2C 435 */ 436 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 437 #define CONFIG_HARD_I2C /* I2C with hardware support */ 438 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 439 #define CONFIG_I2C_MULTI_BUS 440 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 441 #define CONFIG_SYS_I2C_SLAVE 0x7F 442 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ 443 #define CONFIG_SYS_I2C_OFFSET 0x3000 444 #define CONFIG_SYS_I2C2_OFFSET 0x3100 445 446 /* 447 * I2C2 EEPROM 448 */ 449 #define CONFIG_ID_EEPROM 450 #ifdef CONFIG_ID_EEPROM 451 #define CONFIG_SYS_I2C_EEPROM_NXID 452 #endif 453 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 454 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 455 #define CONFIG_SYS_EEPROM_BUS_NUM 1 456 457 /* 458 * General PCI 459 * Memory space is mapped 1-1, but I/O space must start from 0. 460 */ 461 462 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 463 #ifdef CONFIG_PHYS_64BIT 464 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 465 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 466 #else 467 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 468 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 469 #endif 470 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 471 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 472 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 473 #ifdef CONFIG_PHYS_64BIT 474 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 475 #else 476 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 477 #endif 478 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 479 480 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 484 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 485 #else 486 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 487 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 488 #endif 489 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 490 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 491 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 492 #ifdef CONFIG_PHYS_64BIT 493 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 494 #else 495 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 496 #endif 497 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 498 499 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 500 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 501 #ifdef CONFIG_PHYS_64BIT 502 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 503 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 504 #else 505 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 506 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 507 #endif 508 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 509 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 510 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 511 #ifdef CONFIG_PHYS_64BIT 512 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 513 #else 514 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 515 #endif 516 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 519 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 522 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 523 #else 524 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 525 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 526 #endif 527 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 528 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 529 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 530 #ifdef CONFIG_PHYS_64BIT 531 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 532 #else 533 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 534 #endif 535 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 536 537 #if defined(CONFIG_PCI) 538 539 #define CONFIG_NET_MULTI 540 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 541 542 /*PCIE video card used*/ 543 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 544 545 /*PCI video card used*/ 546 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 547 548 /* video */ 549 #define CONFIG_VIDEO 550 551 #if defined(CONFIG_VIDEO) 552 #define CONFIG_BIOSEMU 553 #define CONFIG_CFB_CONSOLE 554 #define CONFIG_VIDEO_SW_CURSOR 555 #define CONFIG_VGA_AS_SINGLE_DEVICE 556 #define CONFIG_ATI_RADEON_FB 557 #define CONFIG_VIDEO_LOGO 558 /*#define CONFIG_CONSOLE_CURSOR*/ 559 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 560 #endif 561 562 #undef CONFIG_EEPRO100 563 #undef CONFIG_TULIP 564 #undef CONFIG_RTL8139 565 566 #ifndef CONFIG_PCI_PNP 567 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 568 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 569 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 570 #endif 571 572 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 573 574 #endif /* CONFIG_PCI */ 575 576 /* SATA */ 577 #define CONFIG_LIBATA 578 #define CONFIG_FSL_SATA 579 580 #define CONFIG_SYS_SATA_MAX_DEVICE 2 581 #define CONFIG_SATA1 582 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 583 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 584 #define CONFIG_SATA2 585 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 586 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 587 588 #ifdef CONFIG_FSL_SATA 589 #define CONFIG_LBA48 590 #define CONFIG_CMD_SATA 591 #define CONFIG_DOS_PARTITION 592 #define CONFIG_CMD_EXT2 593 #endif 594 595 #if defined(CONFIG_TSEC_ENET) 596 597 #ifndef CONFIG_NET_MULTI 598 #define CONFIG_NET_MULTI 1 599 #endif 600 601 #define CONFIG_MII 1 /* MII PHY management */ 602 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 603 #define CONFIG_TSEC1 1 604 #define CONFIG_TSEC1_NAME "eTSEC1" 605 #define CONFIG_TSEC3 1 606 #define CONFIG_TSEC3_NAME "eTSEC3" 607 608 #define CONFIG_FSL_SGMII_RISER 1 609 #define SGMII_RISER_PHY_OFFSET 0x1c 610 611 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 612 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 613 614 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 615 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 616 617 #define TSEC1_PHYIDX 0 618 #define TSEC3_PHYIDX 0 619 620 #define CONFIG_ETHPRIME "eTSEC1" 621 622 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 623 624 #endif /* CONFIG_TSEC_ENET */ 625 626 /* 627 * Environment 628 */ 629 630 #if defined(CONFIG_SYS_RAMBOOT) 631 #if defined(CONFIG_RAMBOOT_NAND) 632 #define CONFIG_ENV_IS_IN_NAND 1 633 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 634 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 635 #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 636 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 637 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 638 #define CONFIG_ENV_SIZE 0x2000 639 #endif 640 #else 641 #define CONFIG_ENV_IS_IN_FLASH 1 642 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 643 #define CONFIG_ENV_ADDR 0xfff80000 644 #else 645 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 646 #endif 647 #define CONFIG_ENV_SIZE 0x2000 648 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 649 #endif 650 651 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 652 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 653 654 /* 655 * Command line configuration. 656 */ 657 #include <config_cmd_default.h> 658 659 #define CONFIG_CMD_IRQ 660 #define CONFIG_CMD_PING 661 #define CONFIG_CMD_I2C 662 #define CONFIG_CMD_MII 663 #define CONFIG_CMD_ELF 664 #define CONFIG_CMD_IRQ 665 #define CONFIG_CMD_SETEXPR 666 #define CONFIG_CMD_REGINFO 667 668 #if defined(CONFIG_PCI) 669 #define CONFIG_CMD_PCI 670 #define CONFIG_CMD_NET 671 #endif 672 673 #undef CONFIG_WATCHDOG /* watchdog disabled */ 674 675 #define CONFIG_MMC 1 676 677 #ifdef CONFIG_MMC 678 #define CONFIG_FSL_ESDHC 679 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 680 #define CONFIG_CMD_MMC 681 #define CONFIG_GENERIC_MMC 682 #define CONFIG_CMD_EXT2 683 #define CONFIG_CMD_FAT 684 #define CONFIG_DOS_PARTITION 685 #endif 686 687 /* 688 * Miscellaneous configurable options 689 */ 690 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 691 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 692 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 693 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 694 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 695 #if defined(CONFIG_CMD_KGDB) 696 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 697 #else 698 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 699 #endif 700 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 701 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 702 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 703 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 704 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 705 706 /* 707 * For booting Linux, the board info and command line data 708 * have to be in the first 16 MB of memory, since this is 709 * the maximum mapped by the Linux kernel during initialization. 710 */ 711 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ 712 713 #if defined(CONFIG_CMD_KGDB) 714 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 715 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 716 #endif 717 718 /* 719 * Environment Configuration 720 */ 721 722 /* The mac addresses for all ethernet interface */ 723 #if defined(CONFIG_TSEC_ENET) 724 #define CONFIG_HAS_ETH0 725 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 726 #define CONFIG_HAS_ETH1 727 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 728 #define CONFIG_HAS_ETH2 729 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 730 #define CONFIG_HAS_ETH3 731 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 732 #endif 733 734 #define CONFIG_IPADDR 192.168.1.254 735 736 #define CONFIG_HOSTNAME unknown 737 #define CONFIG_ROOTPATH /opt/nfsroot 738 #define CONFIG_BOOTFILE uImage 739 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 740 741 #define CONFIG_SERVERIP 192.168.1.1 742 #define CONFIG_GATEWAYIP 192.168.1.1 743 #define CONFIG_NETMASK 255.255.255.0 744 745 /* default location for tftp and bootm */ 746 #define CONFIG_LOADADDR 1000000 747 748 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 749 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 750 751 #define CONFIG_BAUDRATE 115200 752 753 #define CONFIG_EXTRA_ENV_SETTINGS \ 754 "netdev=eth0\0" \ 755 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 756 "tftpflash=tftpboot $loadaddr $uboot; " \ 757 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 758 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 759 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 760 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 761 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 762 "consoledev=ttyS0\0" \ 763 "ramdiskaddr=2000000\0" \ 764 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 765 "fdtaddr=c00000\0" \ 766 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 767 "bdev=sda3\0" \ 768 "usb_phy_type=ulpi\0" 769 770 #define CONFIG_HDBOOT \ 771 "setenv bootargs root=/dev/$bdev rw " \ 772 "console=$consoledev,$baudrate $othbootargs;" \ 773 "tftp $loadaddr $bootfile;" \ 774 "tftp $fdtaddr $fdtfile;" \ 775 "bootm $loadaddr - $fdtaddr" 776 777 #define CONFIG_NFSBOOTCOMMAND \ 778 "setenv bootargs root=/dev/nfs rw " \ 779 "nfsroot=$serverip:$rootpath " \ 780 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 781 "console=$consoledev,$baudrate $othbootargs;" \ 782 "tftp $loadaddr $bootfile;" \ 783 "tftp $fdtaddr $fdtfile;" \ 784 "bootm $loadaddr - $fdtaddr" 785 786 #define CONFIG_RAMBOOTCOMMAND \ 787 "setenv bootargs root=/dev/ram rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "tftp $ramdiskaddr $ramdiskfile;" \ 790 "tftp $loadaddr $bootfile;" \ 791 "tftp $fdtaddr $fdtfile;" \ 792 "bootm $loadaddr $ramdiskaddr $fdtaddr" 793 794 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 795 796 #endif /* __CONFIG_H */ 797