1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8536ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_SDCARD 16 #define CONFIG_RAMBOOT_SDCARD 1 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 1 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 23 #endif 24 25 #ifndef CONFIG_RESET_VECTOR_ADDRESS 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 27 #endif 28 29 #ifndef CONFIG_SYS_MONITOR_BASE 30 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 31 #endif 32 33 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 34 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 35 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 36 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 37 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 39 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 41 42 43 #define CONFIG_ENV_OVERWRITE 44 45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 47 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 48 49 /* 50 * These can be toggled for performance analysis, otherwise use default. 51 */ 52 #define CONFIG_L2_CACHE /* toggle L2 cache */ 53 #define CONFIG_BTB /* toggle branch predition */ 54 55 #define CONFIG_ENABLE_36BIT_PHYS 1 56 57 #ifdef CONFIG_PHYS_64BIT 58 #define CONFIG_ADDR_MAP 1 59 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 60 #endif 61 62 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 64 65 /* 66 * Config the L2 Cache as L2 SRAM 67 */ 68 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 69 #ifdef CONFIG_PHYS_64BIT 70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 71 #else 72 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 73 #endif 74 #define CONFIG_SYS_L2_SIZE (512 << 10) 75 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 76 77 #define CONFIG_SYS_CCSRBAR 0xffe00000 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 80 #if defined(CONFIG_NAND_SPL) 81 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 82 #endif 83 84 /* DDR Setup */ 85 #define CONFIG_VERY_BIG_RAM 86 #undef CONFIG_FSL_DDR_INTERACTIVE 87 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 88 #define CONFIG_DDR_SPD 89 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 97 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 98 99 /* I2C addresses of SPD EEPROMs */ 100 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 101 #define CONFIG_SYS_SPD_BUS_NUM 1 102 103 /* These are used when DDR doesn't use SPD. */ 104 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 105 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 106 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 107 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 108 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 109 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 110 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 111 #define CONFIG_SYS_DDR_MODE_1 0x00480432 112 #define CONFIG_SYS_DDR_MODE_2 0x00000000 113 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 114 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 115 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 116 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 117 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 118 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 119 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 120 121 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 122 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 123 #define CONFIG_SYS_DDR_SBE 0x00010000 124 125 /* Make sure required options are set */ 126 #ifndef CONFIG_SPD_EEPROM 127 #error ("CONFIG_SPD_EEPROM is required") 128 #endif 129 130 #undef CONFIG_CLOCKS_IN_MHZ 131 132 /* 133 * Memory map -- xxx -this is wrong, needs updating 134 * 135 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 136 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 137 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 138 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 139 * 140 * Localbus cacheable (TBD) 141 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 142 * 143 * Localbus non-cacheable 144 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 145 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 146 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 147 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 148 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 149 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 150 */ 151 152 /* 153 * Local Bus Definitions 154 */ 155 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 156 #ifdef CONFIG_PHYS_64BIT 157 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 158 #else 159 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 160 #endif 161 162 #define CONFIG_FLASH_BR_PRELIM \ 163 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 164 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 165 166 #define CONFIG_SYS_BR1_PRELIM \ 167 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 168 | BR_PS_16 | BR_V) 169 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 170 171 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 172 CONFIG_SYS_FLASH_BASE_PHYS } 173 #define CONFIG_SYS_FLASH_QUIET_TEST 174 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 175 176 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 177 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 178 #undef CONFIG_SYS_FLASH_CHECKSUM 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 183 #define CONFIG_SYS_RAMBOOT 184 #else 185 #undef CONFIG_SYS_RAMBOOT 186 #endif 187 188 #define CONFIG_SYS_FLASH_EMPTY_INFO 189 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 190 191 #define CONFIG_HWCONFIG /* enable hwconfig */ 192 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 193 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 194 #ifdef CONFIG_PHYS_64BIT 195 #define PIXIS_BASE_PHYS 0xfffdf0000ull 196 #else 197 #define PIXIS_BASE_PHYS PIXIS_BASE 198 #endif 199 200 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 201 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 202 203 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 204 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 205 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 206 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 207 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 208 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 209 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 210 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 211 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 212 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 213 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 214 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 215 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 216 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 217 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 218 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 219 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 220 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 221 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 222 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 223 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 224 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 225 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 226 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 227 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 228 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 229 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 230 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 231 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 232 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 233 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 234 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 235 #define PIXIS_LED 0x25 /* LED Register */ 236 237 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 238 239 /* old pixis referenced names */ 240 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 241 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 242 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 243 244 #define CONFIG_SYS_INIT_RAM_LOCK 1 245 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 246 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 247 248 #define CONFIG_SYS_GBL_DATA_OFFSET \ 249 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 250 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 251 252 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 253 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 254 255 #ifndef CONFIG_NAND_SPL 256 #define CONFIG_SYS_NAND_BASE 0xffa00000 257 #ifdef CONFIG_PHYS_64BIT 258 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 259 #else 260 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 261 #endif 262 #else 263 #define CONFIG_SYS_NAND_BASE 0xfff00000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 266 #else 267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 268 #endif 269 #endif 270 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 271 CONFIG_SYS_NAND_BASE + 0x40000, \ 272 CONFIG_SYS_NAND_BASE + 0x80000, \ 273 CONFIG_SYS_NAND_BASE + 0xC0000} 274 #define CONFIG_SYS_MAX_NAND_DEVICE 4 275 #define CONFIG_NAND_FSL_ELBC 1 276 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 277 278 /* NAND boot: 4K NAND loader config */ 279 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 280 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 281 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 282 #define CONFIG_SYS_NAND_U_BOOT_START \ 283 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 284 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 285 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 286 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 287 288 /* NAND flash config */ 289 #define CONFIG_SYS_NAND_BR_PRELIM \ 290 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 291 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 292 | BR_PS_8 /* Port Size = 8 bit */ \ 293 | BR_MS_FCM /* MSEL = FCM */ \ 294 | BR_V) /* valid */ 295 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 296 | OR_FCM_PGS /* Large Page*/ \ 297 | OR_FCM_CSCT \ 298 | OR_FCM_CST \ 299 | OR_FCM_CHT \ 300 | OR_FCM_SCY_1 \ 301 | OR_FCM_TRLX \ 302 | OR_FCM_EHTR) 303 304 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 305 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 306 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 307 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 308 309 #define CONFIG_SYS_BR4_PRELIM \ 310 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 311 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 312 | BR_PS_8 /* Port Size = 8 bit */ \ 313 | BR_MS_FCM /* MSEL = FCM */ \ 314 | BR_V) /* valid */ 315 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 316 #define CONFIG_SYS_BR5_PRELIM \ 317 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 318 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 319 | BR_PS_8 /* Port Size = 8 bit */ \ 320 | BR_MS_FCM /* MSEL = FCM */ \ 321 | BR_V) /* valid */ 322 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 323 324 #define CONFIG_SYS_BR6_PRELIM \ 325 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 326 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 327 | BR_PS_8 /* Port Size = 8 bit */ \ 328 | BR_MS_FCM /* MSEL = FCM */ \ 329 | BR_V) /* valid */ 330 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 331 332 /* Serial Port - controlled on board with jumper J8 333 * open - index 2 334 * shorted - index 1 335 */ 336 #define CONFIG_SYS_NS16550_SERIAL 337 #define CONFIG_SYS_NS16550_REG_SIZE 1 338 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 339 #ifdef CONFIG_NAND_SPL 340 #define CONFIG_NS16550_MIN_FUNCTIONS 341 #endif 342 343 #define CONFIG_SYS_BAUDRATE_TABLE \ 344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 345 346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 348 349 /* 350 * I2C 351 */ 352 #define CONFIG_SYS_I2C 353 #define CONFIG_SYS_I2C_FSL 354 #define CONFIG_SYS_FSL_I2C_SPEED 400000 355 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 356 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 357 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 358 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 359 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 360 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 361 362 /* 363 * I2C2 EEPROM 364 */ 365 #define CONFIG_ID_EEPROM 366 #ifdef CONFIG_ID_EEPROM 367 #define CONFIG_SYS_I2C_EEPROM_NXID 368 #endif 369 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 370 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 371 #define CONFIG_SYS_EEPROM_BUS_NUM 1 372 373 #if defined(CONFIG_SPI_FLASH) 374 #define CONFIG_SF_DEFAULT_SPEED 10000000 375 #define CONFIG_SF_DEFAULT_MODE 0 376 #endif 377 378 /* 379 * General PCI 380 * Memory space is mapped 1-1, but I/O space must start from 0. 381 */ 382 383 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 386 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 387 #else 388 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 389 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 390 #endif 391 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 392 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 393 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 396 #else 397 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 398 #endif 399 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 400 401 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 402 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 403 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 406 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 407 #else 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 410 #endif 411 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 412 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 413 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 416 #else 417 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 418 #endif 419 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 420 421 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 422 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 423 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 426 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 427 #else 428 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 430 #endif 431 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 432 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 433 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 436 #else 437 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 438 #endif 439 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 440 441 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 442 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 443 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 446 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 447 #else 448 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 449 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 450 #endif 451 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 452 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 453 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 456 #else 457 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 458 #endif 459 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 460 461 #if defined(CONFIG_PCI) 462 /*PCIE video card used*/ 463 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 464 465 /*PCI video card used*/ 466 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 467 468 /* video */ 469 470 #if defined(CONFIG_VIDEO) 471 #define CONFIG_BIOSEMU 472 #define CONFIG_ATI_RADEON_FB 473 #define CONFIG_VIDEO_LOGO 474 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 475 #endif 476 477 #undef CONFIG_EEPRO100 478 #undef CONFIG_TULIP 479 480 #ifndef CONFIG_PCI_PNP 481 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 482 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 483 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 484 #endif 485 486 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 487 488 #endif /* CONFIG_PCI */ 489 490 /* SATA */ 491 #define CONFIG_SYS_SATA_MAX_DEVICE 2 492 #define CONFIG_SATA1 493 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 494 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 495 #define CONFIG_SATA2 496 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 497 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 498 499 #ifdef CONFIG_FSL_SATA 500 #define CONFIG_LBA48 501 #endif 502 503 #if defined(CONFIG_TSEC_ENET) 504 505 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 506 #define CONFIG_TSEC1 1 507 #define CONFIG_TSEC1_NAME "eTSEC1" 508 #define CONFIG_TSEC3 1 509 #define CONFIG_TSEC3_NAME "eTSEC3" 510 511 #define CONFIG_FSL_SGMII_RISER 1 512 #define SGMII_RISER_PHY_OFFSET 0x1c 513 514 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 515 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 516 517 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 518 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 519 520 #define TSEC1_PHYIDX 0 521 #define TSEC3_PHYIDX 0 522 523 #define CONFIG_ETHPRIME "eTSEC1" 524 525 #endif /* CONFIG_TSEC_ENET */ 526 527 /* 528 * Environment 529 */ 530 531 #if defined(CONFIG_SYS_RAMBOOT) 532 #if defined(CONFIG_RAMBOOT_SPIFLASH) 533 #define CONFIG_ENV_SPI_BUS 0 534 #define CONFIG_ENV_SPI_CS 0 535 #define CONFIG_ENV_SPI_MAX_HZ 10000000 536 #define CONFIG_ENV_SPI_MODE 0 537 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 538 #define CONFIG_ENV_OFFSET 0xF0000 539 #define CONFIG_ENV_SECT_SIZE 0x10000 540 #elif defined(CONFIG_RAMBOOT_SDCARD) 541 #define CONFIG_FSL_FIXED_MMC_LOCATION 542 #define CONFIG_ENV_SIZE 0x2000 543 #define CONFIG_SYS_MMC_ENV_DEV 0 544 #else 545 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 546 #define CONFIG_ENV_SIZE 0x2000 547 #endif 548 #else 549 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 550 #define CONFIG_ENV_SIZE 0x2000 551 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 552 #endif 553 554 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 555 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 556 557 #undef CONFIG_WATCHDOG /* watchdog disabled */ 558 559 #ifdef CONFIG_MMC 560 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 561 #endif 562 563 /* 564 * USB 565 */ 566 #define CONFIG_HAS_FSL_MPH_USB 567 #ifdef CONFIG_HAS_FSL_MPH_USB 568 #ifdef CONFIG_USB_EHCI_HCD 569 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 570 #define CONFIG_USB_EHCI_FSL 571 #endif 572 #endif 573 574 /* 575 * Miscellaneous configurable options 576 */ 577 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 578 579 /* 580 * For booting Linux, the board info and command line data 581 * have to be in the first 64 MB of memory, since this is 582 * the maximum mapped by the Linux kernel during initialization. 583 */ 584 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 585 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 586 587 #if defined(CONFIG_CMD_KGDB) 588 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 589 #endif 590 591 /* 592 * Environment Configuration 593 */ 594 595 /* The mac addresses for all ethernet interface */ 596 #if defined(CONFIG_TSEC_ENET) 597 #define CONFIG_HAS_ETH0 598 #define CONFIG_HAS_ETH1 599 #define CONFIG_HAS_ETH2 600 #define CONFIG_HAS_ETH3 601 #endif 602 603 #define CONFIG_IPADDR 192.168.1.254 604 605 #define CONFIG_HOSTNAME "unknown" 606 #define CONFIG_ROOTPATH "/opt/nfsroot" 607 #define CONFIG_BOOTFILE "uImage" 608 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 609 610 #define CONFIG_SERVERIP 192.168.1.1 611 #define CONFIG_GATEWAYIP 192.168.1.1 612 #define CONFIG_NETMASK 255.255.255.0 613 614 /* default location for tftp and bootm */ 615 #define CONFIG_LOADADDR 1000000 616 617 #define CONFIG_EXTRA_ENV_SETTINGS \ 618 "netdev=eth0\0" \ 619 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 620 "tftpflash=tftpboot $loadaddr $uboot; " \ 621 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 622 " +$filesize; " \ 623 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 624 " +$filesize; " \ 625 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 626 " $filesize; " \ 627 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 628 " +$filesize; " \ 629 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 630 " $filesize\0" \ 631 "consoledev=ttyS0\0" \ 632 "ramdiskaddr=2000000\0" \ 633 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 634 "fdtaddr=1e00000\0" \ 635 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 636 "bdev=sda3\0" \ 637 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 638 639 #define CONFIG_HDBOOT \ 640 "setenv bootargs root=/dev/$bdev rw " \ 641 "console=$consoledev,$baudrate $othbootargs;" \ 642 "tftp $loadaddr $bootfile;" \ 643 "tftp $fdtaddr $fdtfile;" \ 644 "bootm $loadaddr - $fdtaddr" 645 646 #define CONFIG_NFSBOOTCOMMAND \ 647 "setenv bootargs root=/dev/nfs rw " \ 648 "nfsroot=$serverip:$rootpath " \ 649 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 650 "console=$consoledev,$baudrate $othbootargs;" \ 651 "tftp $loadaddr $bootfile;" \ 652 "tftp $fdtaddr $fdtfile;" \ 653 "bootm $loadaddr - $fdtaddr" 654 655 #define CONFIG_RAMBOOTCOMMAND \ 656 "setenv bootargs root=/dev/ram rw " \ 657 "console=$consoledev,$baudrate $othbootargs;" \ 658 "tftp $ramdiskaddr $ramdiskfile;" \ 659 "tftp $loadaddr $bootfile;" \ 660 "tftp $fdtaddr $fdtfile;" \ 661 "bootm $loadaddr $ramdiskaddr $fdtaddr" 662 663 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 664 665 #endif /* __CONFIG_H */ 666