1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 41 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 44 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 46 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 47 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 49 50 51 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 52 #define CONFIG_ENV_OVERWRITE 53 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 57 58 /* 59 * These can be toggled for performance analysis, otherwise use default. 60 */ 61 #define CONFIG_L2_CACHE /* toggle L2 cache */ 62 #define CONFIG_BTB /* toggle branch predition */ 63 64 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 65 66 #define CONFIG_ENABLE_36BIT_PHYS 1 67 68 #ifdef CONFIG_PHYS_64BIT 69 #define CONFIG_ADDR_MAP 1 70 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 71 #endif 72 73 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 74 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 75 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 76 77 /* 78 * Config the L2 Cache as L2 SRAM 79 */ 80 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 83 #else 84 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 85 #endif 86 #define CONFIG_SYS_L2_SIZE (512 << 10) 87 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 88 89 #define CONFIG_SYS_CCSRBAR 0xffe00000 90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 91 92 #if defined(CONFIG_NAND_SPL) 93 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 94 #endif 95 96 /* DDR Setup */ 97 #define CONFIG_VERY_BIG_RAM 98 #undef CONFIG_FSL_DDR_INTERACTIVE 99 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 100 #define CONFIG_DDR_SPD 101 102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 104 105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 107 108 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 109 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 110 111 /* I2C addresses of SPD EEPROMs */ 112 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 113 #define CONFIG_SYS_SPD_BUS_NUM 1 114 115 /* These are used when DDR doesn't use SPD. */ 116 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123 #define CONFIG_SYS_DDR_MODE_1 0x00480432 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x00010000 136 137 /* Make sure required options are set */ 138 #ifndef CONFIG_SPD_EEPROM 139 #error ("CONFIG_SPD_EEPROM is required") 140 #endif 141 142 #undef CONFIG_CLOCKS_IN_MHZ 143 144 /* 145 * Memory map -- xxx -this is wrong, needs updating 146 * 147 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 148 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 149 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 150 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 151 * 152 * Localbus cacheable (TBD) 153 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 154 * 155 * Localbus non-cacheable 156 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 157 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 158 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 159 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 160 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 161 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 162 */ 163 164 /* 165 * Local Bus Definitions 166 */ 167 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 168 #ifdef CONFIG_PHYS_64BIT 169 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 170 #else 171 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 172 #endif 173 174 #define CONFIG_FLASH_BR_PRELIM \ 175 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 176 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 177 178 #define CONFIG_SYS_BR1_PRELIM \ 179 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 180 | BR_PS_16 | BR_V) 181 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 182 183 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 184 CONFIG_SYS_FLASH_BASE_PHYS } 185 #define CONFIG_SYS_FLASH_QUIET_TEST 186 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 187 188 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 189 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 190 #undef CONFIG_SYS_FLASH_CHECKSUM 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 194 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 195 #define CONFIG_SYS_RAMBOOT 196 #define CONFIG_SYS_EXTRA_ENV_RELOC 197 #else 198 #undef CONFIG_SYS_RAMBOOT 199 #endif 200 201 #define CONFIG_FLASH_CFI_DRIVER 202 #define CONFIG_SYS_FLASH_CFI 203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 205 206 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 207 208 #define CONFIG_HWCONFIG /* enable hwconfig */ 209 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 210 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define PIXIS_BASE_PHYS 0xfffdf0000ull 213 #else 214 #define PIXIS_BASE_PHYS PIXIS_BASE 215 #endif 216 217 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 218 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 219 220 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 221 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 222 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 223 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 224 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 225 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 226 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 227 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 228 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 229 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 230 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 231 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 232 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 233 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 234 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 235 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 236 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 237 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 238 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 239 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 240 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 241 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 242 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 243 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 244 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 245 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 246 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 247 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 248 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 249 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 250 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 251 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 252 #define PIXIS_LED 0x25 /* LED Register */ 253 254 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 255 256 /* old pixis referenced names */ 257 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 258 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 259 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 260 261 #define CONFIG_SYS_INIT_RAM_LOCK 1 262 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 263 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 264 265 #define CONFIG_SYS_GBL_DATA_OFFSET \ 266 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 267 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 268 269 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 270 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 271 272 #ifndef CONFIG_NAND_SPL 273 #define CONFIG_SYS_NAND_BASE 0xffa00000 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 276 #else 277 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 278 #endif 279 #else 280 #define CONFIG_SYS_NAND_BASE 0xfff00000 281 #ifdef CONFIG_PHYS_64BIT 282 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 283 #else 284 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 285 #endif 286 #endif 287 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 288 CONFIG_SYS_NAND_BASE + 0x40000, \ 289 CONFIG_SYS_NAND_BASE + 0x80000, \ 290 CONFIG_SYS_NAND_BASE + 0xC0000} 291 #define CONFIG_SYS_MAX_NAND_DEVICE 4 292 #define CONFIG_CMD_NAND 1 293 #define CONFIG_NAND_FSL_ELBC 1 294 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 295 296 /* NAND boot: 4K NAND loader config */ 297 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 298 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 299 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 300 #define CONFIG_SYS_NAND_U_BOOT_START \ 301 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 302 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 303 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 304 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 305 306 /* NAND flash config */ 307 #define CONFIG_SYS_NAND_BR_PRELIM \ 308 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 310 | BR_PS_8 /* Port Size = 8 bit */ \ 311 | BR_MS_FCM /* MSEL = FCM */ \ 312 | BR_V) /* valid */ 313 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 314 | OR_FCM_PGS /* Large Page*/ \ 315 | OR_FCM_CSCT \ 316 | OR_FCM_CST \ 317 | OR_FCM_CHT \ 318 | OR_FCM_SCY_1 \ 319 | OR_FCM_TRLX \ 320 | OR_FCM_EHTR) 321 322 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 323 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 324 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 325 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 326 327 #define CONFIG_SYS_BR4_PRELIM \ 328 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 329 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 330 | BR_PS_8 /* Port Size = 8 bit */ \ 331 | BR_MS_FCM /* MSEL = FCM */ \ 332 | BR_V) /* valid */ 333 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 334 #define CONFIG_SYS_BR5_PRELIM \ 335 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 336 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 337 | BR_PS_8 /* Port Size = 8 bit */ \ 338 | BR_MS_FCM /* MSEL = FCM */ \ 339 | BR_V) /* valid */ 340 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 341 342 #define CONFIG_SYS_BR6_PRELIM \ 343 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 344 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 345 | BR_PS_8 /* Port Size = 8 bit */ \ 346 | BR_MS_FCM /* MSEL = FCM */ \ 347 | BR_V) /* valid */ 348 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 349 350 /* Serial Port - controlled on board with jumper J8 351 * open - index 2 352 * shorted - index 1 353 */ 354 #define CONFIG_CONS_INDEX 1 355 #define CONFIG_SYS_NS16550_SERIAL 356 #define CONFIG_SYS_NS16550_REG_SIZE 1 357 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 358 #ifdef CONFIG_NAND_SPL 359 #define CONFIG_NS16550_MIN_FUNCTIONS 360 #endif 361 362 #define CONFIG_SYS_BAUDRATE_TABLE \ 363 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 364 365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 367 368 /* 369 * I2C 370 */ 371 #define CONFIG_SYS_I2C 372 #define CONFIG_SYS_I2C_FSL 373 #define CONFIG_SYS_FSL_I2C_SPEED 400000 374 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 375 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 376 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 377 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 378 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 379 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 380 381 /* 382 * I2C2 EEPROM 383 */ 384 #define CONFIG_ID_EEPROM 385 #ifdef CONFIG_ID_EEPROM 386 #define CONFIG_SYS_I2C_EEPROM_NXID 387 #endif 388 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 389 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 390 #define CONFIG_SYS_EEPROM_BUS_NUM 1 391 392 /* 393 * eSPI - Enhanced SPI 394 */ 395 #define CONFIG_HARD_SPI 396 397 #if defined(CONFIG_SPI_FLASH) 398 #define CONFIG_SF_DEFAULT_SPEED 10000000 399 #define CONFIG_SF_DEFAULT_MODE 0 400 #endif 401 402 /* 403 * General PCI 404 * Memory space is mapped 1-1, but I/O space must start from 0. 405 */ 406 407 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 410 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 411 #else 412 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 413 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 414 #endif 415 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 416 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 417 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 420 #else 421 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 422 #endif 423 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 424 425 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 426 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 427 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 430 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 431 #else 432 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 433 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 434 #endif 435 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 436 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 437 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 440 #else 441 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 442 #endif 443 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 444 445 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 446 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 447 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 450 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 451 #else 452 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 454 #endif 455 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 456 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 457 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 460 #else 461 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 462 #endif 463 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 464 465 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 466 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 467 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 471 #else 472 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 473 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 474 #endif 475 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 476 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 477 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 480 #else 481 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 482 #endif 483 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 484 485 #if defined(CONFIG_PCI) 486 /*PCIE video card used*/ 487 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 488 489 /*PCI video card used*/ 490 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 491 492 /* video */ 493 494 #if defined(CONFIG_VIDEO) 495 #define CONFIG_BIOSEMU 496 #define CONFIG_ATI_RADEON_FB 497 #define CONFIG_VIDEO_LOGO 498 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 499 #endif 500 501 #undef CONFIG_EEPRO100 502 #undef CONFIG_TULIP 503 504 #ifndef CONFIG_PCI_PNP 505 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 506 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 507 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 508 #endif 509 510 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 511 512 #endif /* CONFIG_PCI */ 513 514 /* SATA */ 515 #define CONFIG_LIBATA 516 #define CONFIG_FSL_SATA 517 518 #define CONFIG_SYS_SATA_MAX_DEVICE 2 519 #define CONFIG_SATA1 520 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 521 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 522 #define CONFIG_SATA2 523 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 524 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 525 526 #ifdef CONFIG_FSL_SATA 527 #define CONFIG_LBA48 528 #define CONFIG_CMD_SATA 529 #define CONFIG_DOS_PARTITION 530 #endif 531 532 #if defined(CONFIG_TSEC_ENET) 533 534 #define CONFIG_MII 1 /* MII PHY management */ 535 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 536 #define CONFIG_TSEC1 1 537 #define CONFIG_TSEC1_NAME "eTSEC1" 538 #define CONFIG_TSEC3 1 539 #define CONFIG_TSEC3_NAME "eTSEC3" 540 541 #define CONFIG_FSL_SGMII_RISER 1 542 #define SGMII_RISER_PHY_OFFSET 0x1c 543 544 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 545 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 546 547 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 548 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 549 550 #define TSEC1_PHYIDX 0 551 #define TSEC3_PHYIDX 0 552 553 #define CONFIG_ETHPRIME "eTSEC1" 554 555 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 556 557 #endif /* CONFIG_TSEC_ENET */ 558 559 /* 560 * Environment 561 */ 562 563 #if defined(CONFIG_SYS_RAMBOOT) 564 #if defined(CONFIG_RAMBOOT_SPIFLASH) 565 #define CONFIG_ENV_IS_IN_SPI_FLASH 566 #define CONFIG_ENV_SPI_BUS 0 567 #define CONFIG_ENV_SPI_CS 0 568 #define CONFIG_ENV_SPI_MAX_HZ 10000000 569 #define CONFIG_ENV_SPI_MODE 0 570 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 571 #define CONFIG_ENV_OFFSET 0xF0000 572 #define CONFIG_ENV_SECT_SIZE 0x10000 573 #elif defined(CONFIG_RAMBOOT_SDCARD) 574 #define CONFIG_ENV_IS_IN_MMC 575 #define CONFIG_FSL_FIXED_MMC_LOCATION 576 #define CONFIG_ENV_SIZE 0x2000 577 #define CONFIG_SYS_MMC_ENV_DEV 0 578 #else 579 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 580 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 581 #define CONFIG_ENV_SIZE 0x2000 582 #endif 583 #else 584 #define CONFIG_ENV_IS_IN_FLASH 1 585 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 586 #define CONFIG_ENV_SIZE 0x2000 587 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 588 #endif 589 590 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 591 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 592 593 /* 594 * Command line configuration. 595 */ 596 #define CONFIG_CMD_IRQ 597 #define CONFIG_CMD_IRQ 598 #define CONFIG_CMD_REGINFO 599 600 #if defined(CONFIG_PCI) 601 #define CONFIG_CMD_PCI 602 #endif 603 604 #undef CONFIG_WATCHDOG /* watchdog disabled */ 605 606 #ifdef CONFIG_MMC 607 #define CONFIG_FSL_ESDHC 608 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 609 #define CONFIG_GENERIC_MMC 610 #endif 611 612 /* 613 * USB 614 */ 615 #define CONFIG_HAS_FSL_MPH_USB 616 #ifdef CONFIG_HAS_FSL_MPH_USB 617 #define CONFIG_USB_EHCI 618 619 #ifdef CONFIG_USB_EHCI 620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 621 #define CONFIG_USB_EHCI_FSL 622 #endif 623 #endif 624 625 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 626 #define CONFIG_DOS_PARTITION 627 #endif 628 629 /* 630 * Miscellaneous configurable options 631 */ 632 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 633 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 634 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 635 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 636 #if defined(CONFIG_CMD_KGDB) 637 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 638 #else 639 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 640 #endif 641 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 642 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 643 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 644 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 645 646 /* 647 * For booting Linux, the board info and command line data 648 * have to be in the first 64 MB of memory, since this is 649 * the maximum mapped by the Linux kernel during initialization. 650 */ 651 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 652 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 653 654 #if defined(CONFIG_CMD_KGDB) 655 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 656 #endif 657 658 /* 659 * Environment Configuration 660 */ 661 662 /* The mac addresses for all ethernet interface */ 663 #if defined(CONFIG_TSEC_ENET) 664 #define CONFIG_HAS_ETH0 665 #define CONFIG_HAS_ETH1 666 #define CONFIG_HAS_ETH2 667 #define CONFIG_HAS_ETH3 668 #endif 669 670 #define CONFIG_IPADDR 192.168.1.254 671 672 #define CONFIG_HOSTNAME unknown 673 #define CONFIG_ROOTPATH "/opt/nfsroot" 674 #define CONFIG_BOOTFILE "uImage" 675 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 676 677 #define CONFIG_SERVERIP 192.168.1.1 678 #define CONFIG_GATEWAYIP 192.168.1.1 679 #define CONFIG_NETMASK 255.255.255.0 680 681 /* default location for tftp and bootm */ 682 #define CONFIG_LOADADDR 1000000 683 684 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 685 686 #define CONFIG_BAUDRATE 115200 687 688 #define CONFIG_EXTRA_ENV_SETTINGS \ 689 "netdev=eth0\0" \ 690 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 691 "tftpflash=tftpboot $loadaddr $uboot; " \ 692 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 693 " +$filesize; " \ 694 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 695 " +$filesize; " \ 696 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 697 " $filesize; " \ 698 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 699 " +$filesize; " \ 700 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 701 " $filesize\0" \ 702 "consoledev=ttyS0\0" \ 703 "ramdiskaddr=2000000\0" \ 704 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 705 "fdtaddr=1e00000\0" \ 706 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 707 "bdev=sda3\0" \ 708 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 709 710 #define CONFIG_HDBOOT \ 711 "setenv bootargs root=/dev/$bdev rw " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_NFSBOOTCOMMAND \ 718 "setenv bootargs root=/dev/nfs rw " \ 719 "nfsroot=$serverip:$rootpath " \ 720 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 721 "console=$consoledev,$baudrate $othbootargs;" \ 722 "tftp $loadaddr $bootfile;" \ 723 "tftp $fdtaddr $fdtfile;" \ 724 "bootm $loadaddr - $fdtaddr" 725 726 #define CONFIG_RAMBOOTCOMMAND \ 727 "setenv bootargs root=/dev/ram rw " \ 728 "console=$consoledev,$baudrate $othbootargs;" \ 729 "tftp $ramdiskaddr $ramdiskfile;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr $ramdiskaddr $fdtaddr" 733 734 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 735 736 #endif /* __CONFIG_H */ 737