1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 44 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 45 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 46 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 47 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 48 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 50 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 55 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 59 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 60 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_L2_CACHE /* toggle L2 cache */ 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 70 #define CONFIG_ENABLE_36BIT_PHYS 1 71 72 #ifdef CONFIG_PHYS_64BIT 73 #define CONFIG_ADDR_MAP 1 74 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 75 #endif 76 77 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 78 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 79 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 80 81 /* 82 * Config the L2 Cache as L2 SRAM 83 */ 84 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 85 #ifdef CONFIG_PHYS_64BIT 86 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 87 #else 88 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 89 #endif 90 #define CONFIG_SYS_L2_SIZE (512 << 10) 91 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 92 93 #define CONFIG_SYS_CCSRBAR 0xffe00000 94 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 95 96 #if defined(CONFIG_NAND_SPL) 97 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 98 #endif 99 100 /* DDR Setup */ 101 #define CONFIG_VERY_BIG_RAM 102 #define CONFIG_SYS_FSL_DDR2 103 #undef CONFIG_FSL_DDR_INTERACTIVE 104 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 105 #define CONFIG_DDR_SPD 106 107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 108 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 109 110 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 111 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 112 113 #define CONFIG_NUM_DDR_CONTROLLERS 1 114 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 115 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 116 117 /* I2C addresses of SPD EEPROMs */ 118 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 119 #define CONFIG_SYS_SPD_BUS_NUM 1 120 121 /* These are used when DDR doesn't use SPD. */ 122 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 123 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 124 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 125 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 126 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 127 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 128 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 129 #define CONFIG_SYS_DDR_MODE_1 0x00480432 130 #define CONFIG_SYS_DDR_MODE_2 0x00000000 131 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 132 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 133 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 134 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 135 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 136 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 137 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 138 139 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 140 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 141 #define CONFIG_SYS_DDR_SBE 0x00010000 142 143 /* Make sure required options are set */ 144 #ifndef CONFIG_SPD_EEPROM 145 #error ("CONFIG_SPD_EEPROM is required") 146 #endif 147 148 #undef CONFIG_CLOCKS_IN_MHZ 149 150 /* 151 * Memory map -- xxx -this is wrong, needs updating 152 * 153 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 154 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 155 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 156 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 157 * 158 * Localbus cacheable (TBD) 159 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 160 * 161 * Localbus non-cacheable 162 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 163 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 164 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 165 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 166 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 167 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 168 */ 169 170 /* 171 * Local Bus Definitions 172 */ 173 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 176 #else 177 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 178 #endif 179 180 #define CONFIG_FLASH_BR_PRELIM \ 181 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 182 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 183 184 #define CONFIG_SYS_BR1_PRELIM \ 185 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 186 | BR_PS_16 | BR_V) 187 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 188 189 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 190 CONFIG_SYS_FLASH_BASE_PHYS } 191 #define CONFIG_SYS_FLASH_QUIET_TEST 192 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 193 194 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 195 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 196 #undef CONFIG_SYS_FLASH_CHECKSUM 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 199 200 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 201 #define CONFIG_SYS_RAMBOOT 202 #define CONFIG_SYS_EXTRA_ENV_RELOC 203 #else 204 #undef CONFIG_SYS_RAMBOOT 205 #endif 206 207 #define CONFIG_FLASH_CFI_DRIVER 208 #define CONFIG_SYS_FLASH_CFI 209 #define CONFIG_SYS_FLASH_EMPTY_INFO 210 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 211 212 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 213 214 #define CONFIG_HWCONFIG /* enable hwconfig */ 215 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 216 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 217 #ifdef CONFIG_PHYS_64BIT 218 #define PIXIS_BASE_PHYS 0xfffdf0000ull 219 #else 220 #define PIXIS_BASE_PHYS PIXIS_BASE 221 #endif 222 223 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 224 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 225 226 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 227 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 228 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 229 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 230 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 231 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 232 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 233 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 234 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 235 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 236 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 237 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 238 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 239 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 240 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 241 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 242 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 243 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 244 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 245 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 246 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 247 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 248 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 249 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 250 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 251 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 252 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 253 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 254 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 255 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 256 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 257 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 258 #define PIXIS_LED 0x25 /* LED Register */ 259 260 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 261 262 /* old pixis referenced names */ 263 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 264 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 265 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 266 267 #define CONFIG_SYS_INIT_RAM_LOCK 1 268 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 269 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 270 271 #define CONFIG_SYS_GBL_DATA_OFFSET \ 272 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 273 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 274 275 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 276 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 277 278 #ifndef CONFIG_NAND_SPL 279 #define CONFIG_SYS_NAND_BASE 0xffa00000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 282 #else 283 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 284 #endif 285 #else 286 #define CONFIG_SYS_NAND_BASE 0xfff00000 287 #ifdef CONFIG_PHYS_64BIT 288 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 289 #else 290 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 291 #endif 292 #endif 293 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 294 CONFIG_SYS_NAND_BASE + 0x40000, \ 295 CONFIG_SYS_NAND_BASE + 0x80000, \ 296 CONFIG_SYS_NAND_BASE + 0xC0000} 297 #define CONFIG_SYS_MAX_NAND_DEVICE 4 298 #define CONFIG_CMD_NAND 1 299 #define CONFIG_NAND_FSL_ELBC 1 300 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 301 302 /* NAND boot: 4K NAND loader config */ 303 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 304 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 305 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 306 #define CONFIG_SYS_NAND_U_BOOT_START \ 307 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 308 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 309 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 310 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 311 312 /* NAND flash config */ 313 #define CONFIG_SYS_NAND_BR_PRELIM \ 314 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 315 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 316 | BR_PS_8 /* Port Size = 8 bit */ \ 317 | BR_MS_FCM /* MSEL = FCM */ \ 318 | BR_V) /* valid */ 319 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 320 | OR_FCM_PGS /* Large Page*/ \ 321 | OR_FCM_CSCT \ 322 | OR_FCM_CST \ 323 | OR_FCM_CHT \ 324 | OR_FCM_SCY_1 \ 325 | OR_FCM_TRLX \ 326 | OR_FCM_EHTR) 327 328 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 329 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 330 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 331 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 332 333 #define CONFIG_SYS_BR4_PRELIM \ 334 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 335 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 336 | BR_PS_8 /* Port Size = 8 bit */ \ 337 | BR_MS_FCM /* MSEL = FCM */ \ 338 | BR_V) /* valid */ 339 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 340 #define CONFIG_SYS_BR5_PRELIM \ 341 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 343 | BR_PS_8 /* Port Size = 8 bit */ \ 344 | BR_MS_FCM /* MSEL = FCM */ \ 345 | BR_V) /* valid */ 346 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 347 348 #define CONFIG_SYS_BR6_PRELIM \ 349 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 350 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 351 | BR_PS_8 /* Port Size = 8 bit */ \ 352 | BR_MS_FCM /* MSEL = FCM */ \ 353 | BR_V) /* valid */ 354 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 355 356 /* Serial Port - controlled on board with jumper J8 357 * open - index 2 358 * shorted - index 1 359 */ 360 #define CONFIG_CONS_INDEX 1 361 #define CONFIG_SYS_NS16550_SERIAL 362 #define CONFIG_SYS_NS16550_REG_SIZE 1 363 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 364 #ifdef CONFIG_NAND_SPL 365 #define CONFIG_NS16550_MIN_FUNCTIONS 366 #endif 367 368 #define CONFIG_SYS_BAUDRATE_TABLE \ 369 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 370 371 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 372 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 373 374 /* 375 * I2C 376 */ 377 #define CONFIG_SYS_I2C 378 #define CONFIG_SYS_I2C_FSL 379 #define CONFIG_SYS_FSL_I2C_SPEED 400000 380 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 381 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 382 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 383 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 384 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 385 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 386 387 /* 388 * I2C2 EEPROM 389 */ 390 #define CONFIG_ID_EEPROM 391 #ifdef CONFIG_ID_EEPROM 392 #define CONFIG_SYS_I2C_EEPROM_NXID 393 #endif 394 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 395 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 396 #define CONFIG_SYS_EEPROM_BUS_NUM 1 397 398 /* 399 * eSPI - Enhanced SPI 400 */ 401 #define CONFIG_HARD_SPI 402 403 #if defined(CONFIG_SPI_FLASH) 404 #define CONFIG_SF_DEFAULT_SPEED 10000000 405 #define CONFIG_SF_DEFAULT_MODE 0 406 #endif 407 408 /* 409 * General PCI 410 * Memory space is mapped 1-1, but I/O space must start from 0. 411 */ 412 413 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 416 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 417 #else 418 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 419 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 420 #endif 421 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 422 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 423 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 426 #else 427 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 428 #endif 429 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 432 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 433 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 436 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 437 #else 438 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 439 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 440 #endif 441 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 442 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 443 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 446 #else 447 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 448 #endif 449 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 450 451 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 452 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 453 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 456 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 457 #else 458 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 459 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 460 #endif 461 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 462 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 463 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 466 #else 467 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 468 #endif 469 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 470 471 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 472 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 473 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 476 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 477 #else 478 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 479 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 480 #endif 481 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 482 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 483 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 484 #ifdef CONFIG_PHYS_64BIT 485 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 486 #else 487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 488 #endif 489 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 490 491 #if defined(CONFIG_PCI) 492 /*PCIE video card used*/ 493 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 494 495 /*PCI video card used*/ 496 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 497 498 /* video */ 499 500 #if defined(CONFIG_VIDEO) 501 #define CONFIG_BIOSEMU 502 #define CONFIG_ATI_RADEON_FB 503 #define CONFIG_VIDEO_LOGO 504 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 505 #endif 506 507 #undef CONFIG_EEPRO100 508 #undef CONFIG_TULIP 509 510 #ifndef CONFIG_PCI_PNP 511 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 512 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 513 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 514 #endif 515 516 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 517 518 #endif /* CONFIG_PCI */ 519 520 /* SATA */ 521 #define CONFIG_LIBATA 522 #define CONFIG_FSL_SATA 523 524 #define CONFIG_SYS_SATA_MAX_DEVICE 2 525 #define CONFIG_SATA1 526 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 527 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 528 #define CONFIG_SATA2 529 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 530 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 531 532 #ifdef CONFIG_FSL_SATA 533 #define CONFIG_LBA48 534 #define CONFIG_CMD_SATA 535 #define CONFIG_DOS_PARTITION 536 #endif 537 538 #if defined(CONFIG_TSEC_ENET) 539 540 #define CONFIG_MII 1 /* MII PHY management */ 541 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 542 #define CONFIG_TSEC1 1 543 #define CONFIG_TSEC1_NAME "eTSEC1" 544 #define CONFIG_TSEC3 1 545 #define CONFIG_TSEC3_NAME "eTSEC3" 546 547 #define CONFIG_FSL_SGMII_RISER 1 548 #define SGMII_RISER_PHY_OFFSET 0x1c 549 550 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 551 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 552 553 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 554 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 555 556 #define TSEC1_PHYIDX 0 557 #define TSEC3_PHYIDX 0 558 559 #define CONFIG_ETHPRIME "eTSEC1" 560 561 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 562 563 #endif /* CONFIG_TSEC_ENET */ 564 565 /* 566 * Environment 567 */ 568 569 #if defined(CONFIG_SYS_RAMBOOT) 570 #if defined(CONFIG_RAMBOOT_SPIFLASH) 571 #define CONFIG_ENV_IS_IN_SPI_FLASH 572 #define CONFIG_ENV_SPI_BUS 0 573 #define CONFIG_ENV_SPI_CS 0 574 #define CONFIG_ENV_SPI_MAX_HZ 10000000 575 #define CONFIG_ENV_SPI_MODE 0 576 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 577 #define CONFIG_ENV_OFFSET 0xF0000 578 #define CONFIG_ENV_SECT_SIZE 0x10000 579 #elif defined(CONFIG_RAMBOOT_SDCARD) 580 #define CONFIG_ENV_IS_IN_MMC 581 #define CONFIG_FSL_FIXED_MMC_LOCATION 582 #define CONFIG_ENV_SIZE 0x2000 583 #define CONFIG_SYS_MMC_ENV_DEV 0 584 #else 585 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 586 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 587 #define CONFIG_ENV_SIZE 0x2000 588 #endif 589 #else 590 #define CONFIG_ENV_IS_IN_FLASH 1 591 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 592 #define CONFIG_ENV_SIZE 0x2000 593 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 594 #endif 595 596 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 597 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 598 599 /* 600 * Command line configuration. 601 */ 602 #define CONFIG_CMD_IRQ 603 #define CONFIG_CMD_IRQ 604 #define CONFIG_CMD_REGINFO 605 606 #if defined(CONFIG_PCI) 607 #define CONFIG_CMD_PCI 608 #endif 609 610 #undef CONFIG_WATCHDOG /* watchdog disabled */ 611 612 #define CONFIG_MMC 1 613 614 #ifdef CONFIG_MMC 615 #define CONFIG_FSL_ESDHC 616 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 617 #define CONFIG_GENERIC_MMC 618 #endif 619 620 /* 621 * USB 622 */ 623 #define CONFIG_HAS_FSL_MPH_USB 624 #ifdef CONFIG_HAS_FSL_MPH_USB 625 #define CONFIG_USB_EHCI 626 627 #ifdef CONFIG_USB_EHCI 628 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 629 #define CONFIG_USB_EHCI_FSL 630 #endif 631 #endif 632 633 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 634 #define CONFIG_DOS_PARTITION 635 #endif 636 637 /* 638 * Miscellaneous configurable options 639 */ 640 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 641 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 642 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 643 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 644 #if defined(CONFIG_CMD_KGDB) 645 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 646 #else 647 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 648 #endif 649 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 650 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 651 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 652 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 653 654 /* 655 * For booting Linux, the board info and command line data 656 * have to be in the first 64 MB of memory, since this is 657 * the maximum mapped by the Linux kernel during initialization. 658 */ 659 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 660 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 661 662 #if defined(CONFIG_CMD_KGDB) 663 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 664 #endif 665 666 /* 667 * Environment Configuration 668 */ 669 670 /* The mac addresses for all ethernet interface */ 671 #if defined(CONFIG_TSEC_ENET) 672 #define CONFIG_HAS_ETH0 673 #define CONFIG_HAS_ETH1 674 #define CONFIG_HAS_ETH2 675 #define CONFIG_HAS_ETH3 676 #endif 677 678 #define CONFIG_IPADDR 192.168.1.254 679 680 #define CONFIG_HOSTNAME unknown 681 #define CONFIG_ROOTPATH "/opt/nfsroot" 682 #define CONFIG_BOOTFILE "uImage" 683 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 684 685 #define CONFIG_SERVERIP 192.168.1.1 686 #define CONFIG_GATEWAYIP 192.168.1.1 687 #define CONFIG_NETMASK 255.255.255.0 688 689 /* default location for tftp and bootm */ 690 #define CONFIG_LOADADDR 1000000 691 692 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 693 694 #define CONFIG_BAUDRATE 115200 695 696 #define CONFIG_EXTRA_ENV_SETTINGS \ 697 "netdev=eth0\0" \ 698 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 699 "tftpflash=tftpboot $loadaddr $uboot; " \ 700 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 701 " +$filesize; " \ 702 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 703 " +$filesize; " \ 704 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 705 " $filesize; " \ 706 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 707 " +$filesize; " \ 708 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 709 " $filesize\0" \ 710 "consoledev=ttyS0\0" \ 711 "ramdiskaddr=2000000\0" \ 712 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 713 "fdtaddr=1e00000\0" \ 714 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 715 "bdev=sda3\0" \ 716 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 717 718 #define CONFIG_HDBOOT \ 719 "setenv bootargs root=/dev/$bdev rw " \ 720 "console=$consoledev,$baudrate $othbootargs;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr - $fdtaddr" 724 725 #define CONFIG_NFSBOOTCOMMAND \ 726 "setenv bootargs root=/dev/nfs rw " \ 727 "nfsroot=$serverip:$rootpath " \ 728 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 729 "console=$consoledev,$baudrate $othbootargs;" \ 730 "tftp $loadaddr $bootfile;" \ 731 "tftp $fdtaddr $fdtfile;" \ 732 "bootm $loadaddr - $fdtaddr" 733 734 #define CONFIG_RAMBOOTCOMMAND \ 735 "setenv bootargs root=/dev/ram rw " \ 736 "console=$consoledev,$baudrate $othbootargs;" \ 737 "tftp $ramdiskaddr $ramdiskfile;" \ 738 "tftp $loadaddr $bootfile;" \ 739 "tftp $fdtaddr $fdtfile;" \ 740 "bootm $loadaddr $ramdiskaddr $fdtaddr" 741 742 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 743 744 #endif /* __CONFIG_H */ 745