1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 #define CONFIG_MPC8536 1 44 #define CONFIG_MPC8536DS 1 45 46 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 47 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 48 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 49 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 50 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 51 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 52 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 53 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 54 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 55 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 56 57 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 58 59 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 60 #define CONFIG_ENV_OVERWRITE 61 62 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 63 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 64 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 65 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE /* toggle L2 cache */ 70 #define CONFIG_BTB /* toggle branch predition */ 71 72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 73 74 #define CONFIG_ENABLE_36BIT_PHYS 1 75 76 #ifdef CONFIG_PHYS_64BIT 77 #define CONFIG_ADDR_MAP 1 78 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 79 #endif 80 81 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 82 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 83 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 84 85 /* 86 * Config the L2 Cache as L2 SRAM 87 */ 88 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 89 #ifdef CONFIG_PHYS_64BIT 90 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 91 #else 92 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 93 #endif 94 #define CONFIG_SYS_L2_SIZE (512 << 10) 95 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 96 97 #define CONFIG_SYS_CCSRBAR 0xffe00000 98 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 99 100 #if defined(CONFIG_NAND_SPL) 101 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 102 #endif 103 104 /* DDR Setup */ 105 #define CONFIG_VERY_BIG_RAM 106 #define CONFIG_SYS_FSL_DDR2 107 #undef CONFIG_FSL_DDR_INTERACTIVE 108 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 109 #define CONFIG_DDR_SPD 110 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 112 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 113 114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 116 117 #define CONFIG_NUM_DDR_CONTROLLERS 1 118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 119 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 120 121 /* I2C addresses of SPD EEPROMs */ 122 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 123 #define CONFIG_SYS_SPD_BUS_NUM 1 124 125 /* These are used when DDR doesn't use SPD. */ 126 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 127 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 128 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 129 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 130 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 131 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 132 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 133 #define CONFIG_SYS_DDR_MODE_1 0x00480432 134 #define CONFIG_SYS_DDR_MODE_2 0x00000000 135 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 136 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 137 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 138 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 139 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 140 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 141 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 142 143 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 144 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 145 #define CONFIG_SYS_DDR_SBE 0x00010000 146 147 /* Make sure required options are set */ 148 #ifndef CONFIG_SPD_EEPROM 149 #error ("CONFIG_SPD_EEPROM is required") 150 #endif 151 152 #undef CONFIG_CLOCKS_IN_MHZ 153 154 /* 155 * Memory map -- xxx -this is wrong, needs updating 156 * 157 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 158 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 159 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 160 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 161 * 162 * Localbus cacheable (TBD) 163 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 164 * 165 * Localbus non-cacheable 166 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 167 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 168 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 169 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 170 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 171 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 172 */ 173 174 /* 175 * Local Bus Definitions 176 */ 177 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 178 #ifdef CONFIG_PHYS_64BIT 179 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 180 #else 181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 182 #endif 183 184 #define CONFIG_FLASH_BR_PRELIM \ 185 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 186 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 187 188 #define CONFIG_SYS_BR1_PRELIM \ 189 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 190 | BR_PS_16 | BR_V) 191 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 192 193 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 194 CONFIG_SYS_FLASH_BASE_PHYS } 195 #define CONFIG_SYS_FLASH_QUIET_TEST 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 197 198 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 199 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 200 #undef CONFIG_SYS_FLASH_CHECKSUM 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 203 204 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 205 #define CONFIG_SYS_RAMBOOT 206 #define CONFIG_SYS_EXTRA_ENV_RELOC 207 #else 208 #undef CONFIG_SYS_RAMBOOT 209 #endif 210 211 #define CONFIG_FLASH_CFI_DRIVER 212 #define CONFIG_SYS_FLASH_CFI 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 215 216 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 217 218 #define CONFIG_HWCONFIG /* enable hwconfig */ 219 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 220 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 221 #ifdef CONFIG_PHYS_64BIT 222 #define PIXIS_BASE_PHYS 0xfffdf0000ull 223 #else 224 #define PIXIS_BASE_PHYS PIXIS_BASE 225 #endif 226 227 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 228 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 229 230 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 231 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 232 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 233 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 234 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 235 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 236 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 237 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 238 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 239 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 240 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 241 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 242 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 243 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 244 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 245 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 246 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 247 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 248 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 249 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 250 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 251 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 252 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 253 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 254 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 255 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 256 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 257 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 258 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 259 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 260 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 261 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 262 #define PIXIS_LED 0x25 /* LED Register */ 263 264 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 265 266 /* old pixis referenced names */ 267 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 268 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 269 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 270 271 #define CONFIG_SYS_INIT_RAM_LOCK 1 272 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 273 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 274 275 #define CONFIG_SYS_GBL_DATA_OFFSET \ 276 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 277 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 278 279 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 280 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 281 282 #ifndef CONFIG_NAND_SPL 283 #define CONFIG_SYS_NAND_BASE 0xffa00000 284 #ifdef CONFIG_PHYS_64BIT 285 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 286 #else 287 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 288 #endif 289 #else 290 #define CONFIG_SYS_NAND_BASE 0xfff00000 291 #ifdef CONFIG_PHYS_64BIT 292 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 293 #else 294 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 295 #endif 296 #endif 297 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 298 CONFIG_SYS_NAND_BASE + 0x40000, \ 299 CONFIG_SYS_NAND_BASE + 0x80000, \ 300 CONFIG_SYS_NAND_BASE + 0xC0000} 301 #define CONFIG_SYS_MAX_NAND_DEVICE 4 302 #define CONFIG_CMD_NAND 1 303 #define CONFIG_NAND_FSL_ELBC 1 304 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 305 306 /* NAND boot: 4K NAND loader config */ 307 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 308 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 309 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 310 #define CONFIG_SYS_NAND_U_BOOT_START \ 311 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 312 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 313 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 314 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 315 316 /* NAND flash config */ 317 #define CONFIG_SYS_NAND_BR_PRELIM \ 318 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 319 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 320 | BR_PS_8 /* Port Size = 8 bit */ \ 321 | BR_MS_FCM /* MSEL = FCM */ \ 322 | BR_V) /* valid */ 323 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 324 | OR_FCM_PGS /* Large Page*/ \ 325 | OR_FCM_CSCT \ 326 | OR_FCM_CST \ 327 | OR_FCM_CHT \ 328 | OR_FCM_SCY_1 \ 329 | OR_FCM_TRLX \ 330 | OR_FCM_EHTR) 331 332 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 333 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 334 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 335 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 336 337 #define CONFIG_SYS_BR4_PRELIM \ 338 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 339 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 340 | BR_PS_8 /* Port Size = 8 bit */ \ 341 | BR_MS_FCM /* MSEL = FCM */ \ 342 | BR_V) /* valid */ 343 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 344 #define CONFIG_SYS_BR5_PRELIM \ 345 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 346 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 347 | BR_PS_8 /* Port Size = 8 bit */ \ 348 | BR_MS_FCM /* MSEL = FCM */ \ 349 | BR_V) /* valid */ 350 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 351 352 #define CONFIG_SYS_BR6_PRELIM \ 353 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 354 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 355 | BR_PS_8 /* Port Size = 8 bit */ \ 356 | BR_MS_FCM /* MSEL = FCM */ \ 357 | BR_V) /* valid */ 358 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 359 360 /* Serial Port - controlled on board with jumper J8 361 * open - index 2 362 * shorted - index 1 363 */ 364 #define CONFIG_CONS_INDEX 1 365 #define CONFIG_SYS_NS16550_SERIAL 366 #define CONFIG_SYS_NS16550_REG_SIZE 1 367 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 368 #ifdef CONFIG_NAND_SPL 369 #define CONFIG_NS16550_MIN_FUNCTIONS 370 #endif 371 372 #define CONFIG_SYS_BAUDRATE_TABLE \ 373 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 374 375 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 376 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 377 378 /* 379 * I2C 380 */ 381 #define CONFIG_SYS_I2C 382 #define CONFIG_SYS_I2C_FSL 383 #define CONFIG_SYS_FSL_I2C_SPEED 400000 384 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 385 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 386 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 387 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 388 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 389 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 390 391 /* 392 * I2C2 EEPROM 393 */ 394 #define CONFIG_ID_EEPROM 395 #ifdef CONFIG_ID_EEPROM 396 #define CONFIG_SYS_I2C_EEPROM_NXID 397 #endif 398 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 399 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 400 #define CONFIG_SYS_EEPROM_BUS_NUM 1 401 402 /* 403 * eSPI - Enhanced SPI 404 */ 405 #define CONFIG_HARD_SPI 406 407 #if defined(CONFIG_SPI_FLASH) 408 #define CONFIG_SF_DEFAULT_SPEED 10000000 409 #define CONFIG_SF_DEFAULT_MODE 0 410 #endif 411 412 /* 413 * General PCI 414 * Memory space is mapped 1-1, but I/O space must start from 0. 415 */ 416 417 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 420 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 421 #else 422 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 423 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 424 #endif 425 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 426 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 427 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 430 #else 431 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 432 #endif 433 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 434 435 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 436 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 437 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 441 #else 442 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 443 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 444 #endif 445 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 446 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 447 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 450 #else 451 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 452 #endif 453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 454 455 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 456 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 457 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 460 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 461 #else 462 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 463 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 464 #endif 465 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 466 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 467 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 470 #else 471 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 472 #endif 473 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 474 475 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 476 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 477 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 480 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 481 #else 482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 484 #endif 485 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 486 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 487 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 488 #ifdef CONFIG_PHYS_64BIT 489 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 490 #else 491 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 492 #endif 493 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 494 495 #if defined(CONFIG_PCI) 496 497 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 498 499 /*PCIE video card used*/ 500 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 501 502 /*PCI video card used*/ 503 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 504 505 /* video */ 506 507 #if defined(CONFIG_VIDEO) 508 #define CONFIG_BIOSEMU 509 #define CONFIG_ATI_RADEON_FB 510 #define CONFIG_VIDEO_LOGO 511 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 512 #endif 513 514 #undef CONFIG_EEPRO100 515 #undef CONFIG_TULIP 516 517 #ifndef CONFIG_PCI_PNP 518 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 519 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 520 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 521 #endif 522 523 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 524 525 #endif /* CONFIG_PCI */ 526 527 /* SATA */ 528 #define CONFIG_LIBATA 529 #define CONFIG_FSL_SATA 530 531 #define CONFIG_SYS_SATA_MAX_DEVICE 2 532 #define CONFIG_SATA1 533 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 534 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 535 #define CONFIG_SATA2 536 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 537 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 538 539 #ifdef CONFIG_FSL_SATA 540 #define CONFIG_LBA48 541 #define CONFIG_CMD_SATA 542 #define CONFIG_DOS_PARTITION 543 #endif 544 545 #if defined(CONFIG_TSEC_ENET) 546 547 #define CONFIG_MII 1 /* MII PHY management */ 548 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 549 #define CONFIG_TSEC1 1 550 #define CONFIG_TSEC1_NAME "eTSEC1" 551 #define CONFIG_TSEC3 1 552 #define CONFIG_TSEC3_NAME "eTSEC3" 553 554 #define CONFIG_FSL_SGMII_RISER 1 555 #define SGMII_RISER_PHY_OFFSET 0x1c 556 557 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 558 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 559 560 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 561 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 562 563 #define TSEC1_PHYIDX 0 564 #define TSEC3_PHYIDX 0 565 566 #define CONFIG_ETHPRIME "eTSEC1" 567 568 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 569 570 #endif /* CONFIG_TSEC_ENET */ 571 572 /* 573 * Environment 574 */ 575 576 #if defined(CONFIG_SYS_RAMBOOT) 577 #if defined(CONFIG_RAMBOOT_SPIFLASH) 578 #define CONFIG_ENV_IS_IN_SPI_FLASH 579 #define CONFIG_ENV_SPI_BUS 0 580 #define CONFIG_ENV_SPI_CS 0 581 #define CONFIG_ENV_SPI_MAX_HZ 10000000 582 #define CONFIG_ENV_SPI_MODE 0 583 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 584 #define CONFIG_ENV_OFFSET 0xF0000 585 #define CONFIG_ENV_SECT_SIZE 0x10000 586 #elif defined(CONFIG_RAMBOOT_SDCARD) 587 #define CONFIG_ENV_IS_IN_MMC 588 #define CONFIG_FSL_FIXED_MMC_LOCATION 589 #define CONFIG_ENV_SIZE 0x2000 590 #define CONFIG_SYS_MMC_ENV_DEV 0 591 #else 592 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 593 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 594 #define CONFIG_ENV_SIZE 0x2000 595 #endif 596 #else 597 #define CONFIG_ENV_IS_IN_FLASH 1 598 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 599 #define CONFIG_ENV_SIZE 0x2000 600 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 601 #endif 602 603 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 604 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 605 606 /* 607 * Command line configuration. 608 */ 609 #define CONFIG_CMD_IRQ 610 #define CONFIG_CMD_IRQ 611 #define CONFIG_CMD_REGINFO 612 613 #if defined(CONFIG_PCI) 614 #define CONFIG_CMD_PCI 615 #endif 616 617 #undef CONFIG_WATCHDOG /* watchdog disabled */ 618 619 #define CONFIG_MMC 1 620 621 #ifdef CONFIG_MMC 622 #define CONFIG_FSL_ESDHC 623 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 624 #define CONFIG_GENERIC_MMC 625 #endif 626 627 /* 628 * USB 629 */ 630 #define CONFIG_HAS_FSL_MPH_USB 631 #ifdef CONFIG_HAS_FSL_MPH_USB 632 #define CONFIG_USB_EHCI 633 634 #ifdef CONFIG_USB_EHCI 635 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 636 #define CONFIG_USB_EHCI_FSL 637 #endif 638 #endif 639 640 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 641 #define CONFIG_DOS_PARTITION 642 #endif 643 644 /* 645 * Miscellaneous configurable options 646 */ 647 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 648 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 649 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 650 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 651 #if defined(CONFIG_CMD_KGDB) 652 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 653 #else 654 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 655 #endif 656 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 657 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 658 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 659 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 660 661 /* 662 * For booting Linux, the board info and command line data 663 * have to be in the first 64 MB of memory, since this is 664 * the maximum mapped by the Linux kernel during initialization. 665 */ 666 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 667 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 668 669 #if defined(CONFIG_CMD_KGDB) 670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 671 #endif 672 673 /* 674 * Environment Configuration 675 */ 676 677 /* The mac addresses for all ethernet interface */ 678 #if defined(CONFIG_TSEC_ENET) 679 #define CONFIG_HAS_ETH0 680 #define CONFIG_HAS_ETH1 681 #define CONFIG_HAS_ETH2 682 #define CONFIG_HAS_ETH3 683 #endif 684 685 #define CONFIG_IPADDR 192.168.1.254 686 687 #define CONFIG_HOSTNAME unknown 688 #define CONFIG_ROOTPATH "/opt/nfsroot" 689 #define CONFIG_BOOTFILE "uImage" 690 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 691 692 #define CONFIG_SERVERIP 192.168.1.1 693 #define CONFIG_GATEWAYIP 192.168.1.1 694 #define CONFIG_NETMASK 255.255.255.0 695 696 /* default location for tftp and bootm */ 697 #define CONFIG_LOADADDR 1000000 698 699 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 700 701 #define CONFIG_BAUDRATE 115200 702 703 #define CONFIG_EXTRA_ENV_SETTINGS \ 704 "netdev=eth0\0" \ 705 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 706 "tftpflash=tftpboot $loadaddr $uboot; " \ 707 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 708 " +$filesize; " \ 709 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 710 " +$filesize; " \ 711 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 712 " $filesize; " \ 713 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 714 " +$filesize; " \ 715 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 716 " $filesize\0" \ 717 "consoledev=ttyS0\0" \ 718 "ramdiskaddr=2000000\0" \ 719 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 720 "fdtaddr=1e00000\0" \ 721 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 722 "bdev=sda3\0" \ 723 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 724 725 #define CONFIG_HDBOOT \ 726 "setenv bootargs root=/dev/$bdev rw " \ 727 "console=$consoledev,$baudrate $othbootargs;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr - $fdtaddr" 731 732 #define CONFIG_NFSBOOTCOMMAND \ 733 "setenv bootargs root=/dev/nfs rw " \ 734 "nfsroot=$serverip:$rootpath " \ 735 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 736 "console=$consoledev,$baudrate $othbootargs;" \ 737 "tftp $loadaddr $bootfile;" \ 738 "tftp $fdtaddr $fdtfile;" \ 739 "bootm $loadaddr - $fdtaddr" 740 741 #define CONFIG_RAMBOOTCOMMAND \ 742 "setenv bootargs root=/dev/ram rw " \ 743 "console=$consoledev,$baudrate $othbootargs;" \ 744 "tftp $ramdiskaddr $ramdiskfile;" \ 745 "tftp $loadaddr $bootfile;" \ 746 "tftp $fdtaddr $fdtfile;" \ 747 "bootm $loadaddr $ramdiskaddr $fdtaddr" 748 749 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 750 751 #endif /* __CONFIG_H */ 752