1 /* 2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8536ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 1 18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 20 #endif 21 22 #ifdef CONFIG_SPIFLASH 23 #define CONFIG_RAMBOOT_SPIFLASH 1 24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 26 #endif 27 28 #ifndef CONFIG_SYS_TEXT_BASE 29 #define CONFIG_SYS_TEXT_BASE 0xeff40000 30 #endif 31 32 #ifndef CONFIG_RESET_VECTOR_ADDRESS 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 34 #endif 35 36 #ifndef CONFIG_SYS_MONITOR_BASE 37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 1 /* BOOKE */ 42 #define CONFIG_E500 1 /* BOOKE e500 family */ 43 44 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 45 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ 46 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 47 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 48 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 50 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 51 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 52 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 53 54 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 55 56 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 57 #define CONFIG_ENV_OVERWRITE 58 59 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 60 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 61 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 62 63 /* 64 * These can be toggled for performance analysis, otherwise use default. 65 */ 66 #define CONFIG_L2_CACHE /* toggle L2 cache */ 67 #define CONFIG_BTB /* toggle branch predition */ 68 69 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 70 71 #define CONFIG_ENABLE_36BIT_PHYS 1 72 73 #ifdef CONFIG_PHYS_64BIT 74 #define CONFIG_ADDR_MAP 1 75 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 76 #endif 77 78 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ 79 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ 80 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 81 82 /* 83 * Config the L2 Cache as L2 SRAM 84 */ 85 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 86 #ifdef CONFIG_PHYS_64BIT 87 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 88 #else 89 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 90 #endif 91 #define CONFIG_SYS_L2_SIZE (512 << 10) 92 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 93 94 #define CONFIG_SYS_CCSRBAR 0xffe00000 95 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 96 97 #if defined(CONFIG_NAND_SPL) 98 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 99 #endif 100 101 /* DDR Setup */ 102 #define CONFIG_VERY_BIG_RAM 103 #define CONFIG_SYS_FSL_DDR2 104 #undef CONFIG_FSL_DDR_INTERACTIVE 105 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 106 #define CONFIG_DDR_SPD 107 108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 109 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 110 111 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 112 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 113 114 #define CONFIG_NUM_DDR_CONTROLLERS 1 115 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 116 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 117 118 /* I2C addresses of SPD EEPROMs */ 119 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 120 #define CONFIG_SYS_SPD_BUS_NUM 1 121 122 /* These are used when DDR doesn't use SPD. */ 123 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 124 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 125 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 126 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 127 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 128 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 129 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 130 #define CONFIG_SYS_DDR_MODE_1 0x00480432 131 #define CONFIG_SYS_DDR_MODE_2 0x00000000 132 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 133 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 134 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 135 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 136 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 137 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 138 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 139 140 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 141 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 142 #define CONFIG_SYS_DDR_SBE 0x00010000 143 144 /* Make sure required options are set */ 145 #ifndef CONFIG_SPD_EEPROM 146 #error ("CONFIG_SPD_EEPROM is required") 147 #endif 148 149 #undef CONFIG_CLOCKS_IN_MHZ 150 151 /* 152 * Memory map -- xxx -this is wrong, needs updating 153 * 154 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 155 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 156 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 157 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 158 * 159 * Localbus cacheable (TBD) 160 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 161 * 162 * Localbus non-cacheable 163 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable 164 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 165 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 166 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 167 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 168 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 169 */ 170 171 /* 172 * Local Bus Definitions 173 */ 174 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 177 #else 178 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 179 #endif 180 181 #define CONFIG_FLASH_BR_PRELIM \ 182 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 183 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 184 185 #define CONFIG_SYS_BR1_PRELIM \ 186 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ 187 | BR_PS_16 | BR_V) 188 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 189 190 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ 191 CONFIG_SYS_FLASH_BASE_PHYS } 192 #define CONFIG_SYS_FLASH_QUIET_TEST 193 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 194 195 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 197 #undef CONFIG_SYS_FLASH_CHECKSUM 198 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 200 201 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) 202 #define CONFIG_SYS_RAMBOOT 203 #define CONFIG_SYS_EXTRA_ENV_RELOC 204 #else 205 #undef CONFIG_SYS_RAMBOOT 206 #endif 207 208 #define CONFIG_FLASH_CFI_DRIVER 209 #define CONFIG_SYS_FLASH_CFI 210 #define CONFIG_SYS_FLASH_EMPTY_INFO 211 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 212 213 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 214 215 #define CONFIG_HWCONFIG /* enable hwconfig */ 216 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 217 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 218 #ifdef CONFIG_PHYS_64BIT 219 #define PIXIS_BASE_PHYS 0xfffdf0000ull 220 #else 221 #define PIXIS_BASE_PHYS PIXIS_BASE 222 #endif 223 224 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 225 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 226 227 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 228 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 229 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 230 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 231 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 232 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 233 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 234 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 235 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 236 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 237 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 238 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 239 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 240 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 241 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 242 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ 243 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 244 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ 245 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ 246 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ 247 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ 248 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ 249 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 250 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 251 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 252 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ 253 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ 254 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ 255 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ 256 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ 257 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ 258 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 259 #define PIXIS_LED 0x25 /* LED Register */ 260 261 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ 262 263 /* old pixis referenced names */ 264 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 265 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 266 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e 267 268 #define CONFIG_SYS_INIT_RAM_LOCK 1 269 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 270 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 271 272 #define CONFIG_SYS_GBL_DATA_OFFSET \ 273 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 274 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 275 276 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 277 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 278 279 #ifndef CONFIG_NAND_SPL 280 #define CONFIG_SYS_NAND_BASE 0xffa00000 281 #ifdef CONFIG_PHYS_64BIT 282 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 283 #else 284 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 285 #endif 286 #else 287 #define CONFIG_SYS_NAND_BASE 0xfff00000 288 #ifdef CONFIG_PHYS_64BIT 289 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 290 #else 291 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 292 #endif 293 #endif 294 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 295 CONFIG_SYS_NAND_BASE + 0x40000, \ 296 CONFIG_SYS_NAND_BASE + 0x80000, \ 297 CONFIG_SYS_NAND_BASE + 0xC0000} 298 #define CONFIG_SYS_MAX_NAND_DEVICE 4 299 #define CONFIG_CMD_NAND 1 300 #define CONFIG_NAND_FSL_ELBC 1 301 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 302 303 /* NAND boot: 4K NAND loader config */ 304 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 305 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 306 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 307 #define CONFIG_SYS_NAND_U_BOOT_START \ 308 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 309 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 310 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 311 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 312 313 /* NAND flash config */ 314 #define CONFIG_SYS_NAND_BR_PRELIM \ 315 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 316 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 317 | BR_PS_8 /* Port Size = 8 bit */ \ 318 | BR_MS_FCM /* MSEL = FCM */ \ 319 | BR_V) /* valid */ 320 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 321 | OR_FCM_PGS /* Large Page*/ \ 322 | OR_FCM_CSCT \ 323 | OR_FCM_CST \ 324 | OR_FCM_CHT \ 325 | OR_FCM_SCY_1 \ 326 | OR_FCM_TRLX \ 327 | OR_FCM_EHTR) 328 329 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 330 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 331 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 332 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 333 334 #define CONFIG_SYS_BR4_PRELIM \ 335 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 336 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 337 | BR_PS_8 /* Port Size = 8 bit */ \ 338 | BR_MS_FCM /* MSEL = FCM */ \ 339 | BR_V) /* valid */ 340 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 341 #define CONFIG_SYS_BR5_PRELIM \ 342 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ 343 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 344 | BR_PS_8 /* Port Size = 8 bit */ \ 345 | BR_MS_FCM /* MSEL = FCM */ \ 346 | BR_V) /* valid */ 347 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 348 349 #define CONFIG_SYS_BR6_PRELIM \ 350 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ 351 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 352 | BR_PS_8 /* Port Size = 8 bit */ \ 353 | BR_MS_FCM /* MSEL = FCM */ \ 354 | BR_V) /* valid */ 355 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 356 357 /* Serial Port - controlled on board with jumper J8 358 * open - index 2 359 * shorted - index 1 360 */ 361 #define CONFIG_CONS_INDEX 1 362 #define CONFIG_SYS_NS16550_SERIAL 363 #define CONFIG_SYS_NS16550_REG_SIZE 1 364 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 365 #ifdef CONFIG_NAND_SPL 366 #define CONFIG_NS16550_MIN_FUNCTIONS 367 #endif 368 369 #define CONFIG_SYS_BAUDRATE_TABLE \ 370 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 371 372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 374 375 /* 376 * I2C 377 */ 378 #define CONFIG_SYS_I2C 379 #define CONFIG_SYS_I2C_FSL 380 #define CONFIG_SYS_FSL_I2C_SPEED 400000 381 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 382 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 383 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 384 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 385 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 386 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 387 388 /* 389 * I2C2 EEPROM 390 */ 391 #define CONFIG_ID_EEPROM 392 #ifdef CONFIG_ID_EEPROM 393 #define CONFIG_SYS_I2C_EEPROM_NXID 394 #endif 395 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 396 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 397 #define CONFIG_SYS_EEPROM_BUS_NUM 1 398 399 /* 400 * eSPI - Enhanced SPI 401 */ 402 #define CONFIG_HARD_SPI 403 404 #if defined(CONFIG_SPI_FLASH) 405 #define CONFIG_SF_DEFAULT_SPEED 10000000 406 #define CONFIG_SF_DEFAULT_MODE 0 407 #endif 408 409 /* 410 * General PCI 411 * Memory space is mapped 1-1, but I/O space must start from 0. 412 */ 413 414 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 417 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 418 #else 419 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 420 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 421 #endif 422 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 423 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 424 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull 427 #else 428 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 429 #endif 430 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ 431 432 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 433 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 434 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull 438 #else 439 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 440 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 441 #endif 442 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ 443 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 444 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull 447 #else 448 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 449 #endif 450 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 451 452 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 453 #define CONFIG_SYS_PCIE2_NAME "Slot 2" 454 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 457 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull 458 #else 459 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 460 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 461 #endif 462 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ 463 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 464 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 465 #ifdef CONFIG_PHYS_64BIT 466 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull 467 #else 468 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 469 #endif 470 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 471 472 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 473 #define CONFIG_SYS_PCIE3_NAME "Slot 3" 474 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 475 #ifdef CONFIG_PHYS_64BIT 476 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 477 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 478 #else 479 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 480 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 481 #endif 482 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 483 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 484 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 485 #ifdef CONFIG_PHYS_64BIT 486 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull 487 #else 488 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 489 #endif 490 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 491 492 #if defined(CONFIG_PCI) 493 /*PCIE video card used*/ 494 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT 495 496 /*PCI video card used*/ 497 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ 498 499 /* video */ 500 501 #if defined(CONFIG_VIDEO) 502 #define CONFIG_BIOSEMU 503 #define CONFIG_ATI_RADEON_FB 504 #define CONFIG_VIDEO_LOGO 505 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT 506 #endif 507 508 #undef CONFIG_EEPRO100 509 #undef CONFIG_TULIP 510 511 #ifndef CONFIG_PCI_PNP 512 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 513 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 514 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 515 #endif 516 517 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 518 519 #endif /* CONFIG_PCI */ 520 521 /* SATA */ 522 #define CONFIG_LIBATA 523 #define CONFIG_FSL_SATA 524 525 #define CONFIG_SYS_SATA_MAX_DEVICE 2 526 #define CONFIG_SATA1 527 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 528 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 529 #define CONFIG_SATA2 530 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 531 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 532 533 #ifdef CONFIG_FSL_SATA 534 #define CONFIG_LBA48 535 #define CONFIG_CMD_SATA 536 #define CONFIG_DOS_PARTITION 537 #endif 538 539 #if defined(CONFIG_TSEC_ENET) 540 541 #define CONFIG_MII 1 /* MII PHY management */ 542 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 543 #define CONFIG_TSEC1 1 544 #define CONFIG_TSEC1_NAME "eTSEC1" 545 #define CONFIG_TSEC3 1 546 #define CONFIG_TSEC3_NAME "eTSEC3" 547 548 #define CONFIG_FSL_SGMII_RISER 1 549 #define SGMII_RISER_PHY_OFFSET 0x1c 550 551 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ 552 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ 553 554 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 555 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 556 557 #define TSEC1_PHYIDX 0 558 #define TSEC3_PHYIDX 0 559 560 #define CONFIG_ETHPRIME "eTSEC1" 561 562 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 563 564 #endif /* CONFIG_TSEC_ENET */ 565 566 /* 567 * Environment 568 */ 569 570 #if defined(CONFIG_SYS_RAMBOOT) 571 #if defined(CONFIG_RAMBOOT_SPIFLASH) 572 #define CONFIG_ENV_IS_IN_SPI_FLASH 573 #define CONFIG_ENV_SPI_BUS 0 574 #define CONFIG_ENV_SPI_CS 0 575 #define CONFIG_ENV_SPI_MAX_HZ 10000000 576 #define CONFIG_ENV_SPI_MODE 0 577 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 578 #define CONFIG_ENV_OFFSET 0xF0000 579 #define CONFIG_ENV_SECT_SIZE 0x10000 580 #elif defined(CONFIG_RAMBOOT_SDCARD) 581 #define CONFIG_ENV_IS_IN_MMC 582 #define CONFIG_FSL_FIXED_MMC_LOCATION 583 #define CONFIG_ENV_SIZE 0x2000 584 #define CONFIG_SYS_MMC_ENV_DEV 0 585 #else 586 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 587 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 588 #define CONFIG_ENV_SIZE 0x2000 589 #endif 590 #else 591 #define CONFIG_ENV_IS_IN_FLASH 1 592 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 593 #define CONFIG_ENV_SIZE 0x2000 594 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 595 #endif 596 597 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 598 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 599 600 /* 601 * Command line configuration. 602 */ 603 #define CONFIG_CMD_IRQ 604 #define CONFIG_CMD_IRQ 605 #define CONFIG_CMD_REGINFO 606 607 #if defined(CONFIG_PCI) 608 #define CONFIG_CMD_PCI 609 #endif 610 611 #undef CONFIG_WATCHDOG /* watchdog disabled */ 612 613 #define CONFIG_MMC 1 614 615 #ifdef CONFIG_MMC 616 #define CONFIG_FSL_ESDHC 617 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 618 #define CONFIG_GENERIC_MMC 619 #endif 620 621 /* 622 * USB 623 */ 624 #define CONFIG_HAS_FSL_MPH_USB 625 #ifdef CONFIG_HAS_FSL_MPH_USB 626 #define CONFIG_USB_EHCI 627 628 #ifdef CONFIG_USB_EHCI 629 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 630 #define CONFIG_USB_EHCI_FSL 631 #endif 632 #endif 633 634 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 635 #define CONFIG_DOS_PARTITION 636 #endif 637 638 /* 639 * Miscellaneous configurable options 640 */ 641 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 642 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 643 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 644 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 645 #if defined(CONFIG_CMD_KGDB) 646 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 647 #else 648 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 649 #endif 650 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 651 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 652 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 653 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 654 655 /* 656 * For booting Linux, the board info and command line data 657 * have to be in the first 64 MB of memory, since this is 658 * the maximum mapped by the Linux kernel during initialization. 659 */ 660 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 661 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 662 663 #if defined(CONFIG_CMD_KGDB) 664 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 665 #endif 666 667 /* 668 * Environment Configuration 669 */ 670 671 /* The mac addresses for all ethernet interface */ 672 #if defined(CONFIG_TSEC_ENET) 673 #define CONFIG_HAS_ETH0 674 #define CONFIG_HAS_ETH1 675 #define CONFIG_HAS_ETH2 676 #define CONFIG_HAS_ETH3 677 #endif 678 679 #define CONFIG_IPADDR 192.168.1.254 680 681 #define CONFIG_HOSTNAME unknown 682 #define CONFIG_ROOTPATH "/opt/nfsroot" 683 #define CONFIG_BOOTFILE "uImage" 684 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 685 686 #define CONFIG_SERVERIP 192.168.1.1 687 #define CONFIG_GATEWAYIP 192.168.1.1 688 #define CONFIG_NETMASK 255.255.255.0 689 690 /* default location for tftp and bootm */ 691 #define CONFIG_LOADADDR 1000000 692 693 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 694 695 #define CONFIG_BAUDRATE 115200 696 697 #define CONFIG_EXTRA_ENV_SETTINGS \ 698 "netdev=eth0\0" \ 699 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 700 "tftpflash=tftpboot $loadaddr $uboot; " \ 701 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 702 " +$filesize; " \ 703 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 704 " +$filesize; " \ 705 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 706 " $filesize; " \ 707 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 708 " +$filesize; " \ 709 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 710 " $filesize\0" \ 711 "consoledev=ttyS0\0" \ 712 "ramdiskaddr=2000000\0" \ 713 "ramdiskfile=8536ds/ramdisk.uboot\0" \ 714 "fdtaddr=1e00000\0" \ 715 "fdtfile=8536ds/mpc8536ds.dtb\0" \ 716 "bdev=sda3\0" \ 717 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 718 719 #define CONFIG_HDBOOT \ 720 "setenv bootargs root=/dev/$bdev rw " \ 721 "console=$consoledev,$baudrate $othbootargs;" \ 722 "tftp $loadaddr $bootfile;" \ 723 "tftp $fdtaddr $fdtfile;" \ 724 "bootm $loadaddr - $fdtaddr" 725 726 #define CONFIG_NFSBOOTCOMMAND \ 727 "setenv bootargs root=/dev/nfs rw " \ 728 "nfsroot=$serverip:$rootpath " \ 729 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 730 "console=$consoledev,$baudrate $othbootargs;" \ 731 "tftp $loadaddr $bootfile;" \ 732 "tftp $fdtaddr $fdtfile;" \ 733 "bootm $loadaddr - $fdtaddr" 734 735 #define CONFIG_RAMBOOTCOMMAND \ 736 "setenv bootargs root=/dev/ram rw " \ 737 "console=$consoledev,$baudrate $othbootargs;" \ 738 "tftp $ramdiskaddr $ramdiskfile;" \ 739 "tftp $loadaddr $bootfile;" \ 740 "tftp $fdtaddr $fdtfile;" \ 741 "bootm $loadaddr $ramdiskaddr $fdtaddr" 742 743 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 744 745 #endif /* __CONFIG_H */ 746