1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 17 #define CONFIG_MPC837XERDB 1 18 19 #define CONFIG_SYS_TEXT_BASE 0xFE000000 20 21 #define CONFIG_PCI 1 22 23 #define CONFIG_BOARD_EARLY_INIT_F 24 #define CONFIG_MISC_INIT_R 25 #define CONFIG_HWCONFIG 26 27 /* 28 * On-board devices 29 */ 30 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 31 #define CONFIG_VSC7385_ENET 32 33 /* 34 * System Clock Setup 35 */ 36 #ifdef CONFIG_PCISLAVE 37 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 38 #else 39 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 40 #define CONFIG_PCIE 41 #endif 42 43 #ifndef CONFIG_SYS_CLK_FREQ 44 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 45 #endif 46 47 /* 48 * Hardware Reset Configuration Word 49 */ 50 #define CONFIG_SYS_HRCW_LOW (\ 51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 53 HRCWL_SVCOD_DIV_2 |\ 54 HRCWL_CSB_TO_CLKIN_5X1 |\ 55 HRCWL_CORE_TO_CSB_2X1) 56 57 #ifdef CONFIG_PCISLAVE 58 #define CONFIG_SYS_HRCW_HIGH (\ 59 HRCWH_PCI_AGENT |\ 60 HRCWH_PCI1_ARBITER_DISABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0XFFF00100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_RL_EXT_LEGACY |\ 67 HRCWH_TSEC1M_IN_RGMII |\ 68 HRCWH_TSEC2M_IN_RGMII |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LDP_CLEAR) 71 #else 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_PCI_HOST |\ 74 HRCWH_PCI1_ARBITER_ENABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0X00000100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_RL_EXT_LEGACY |\ 81 HRCWH_TSEC1M_IN_RGMII |\ 82 HRCWH_TSEC2M_IN_RGMII |\ 83 HRCWH_BIG_ENDIAN |\ 84 HRCWH_LDP_CLEAR) 85 #endif 86 87 /* System performance - define the value i.e. CONFIG_SYS_XXX 88 */ 89 90 /* Arbiter Configuration Register */ 91 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 92 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 93 94 /* System Priority Control Regsiter */ 95 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 96 97 /* System Clock Configuration Register */ 98 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 99 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 100 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 101 102 /* 103 * System IO Config 104 */ 105 #define CONFIG_SYS_SICRH 0x08200000 106 #define CONFIG_SYS_SICRL 0x00000000 107 108 /* 109 * Output Buffer Impedance 110 */ 111 #define CONFIG_SYS_OBIR 0x30100000 112 113 /* 114 * IMMR new address 115 */ 116 #define CONFIG_SYS_IMMR 0xE0000000 117 118 /* 119 * Device configurations 120 */ 121 122 /* Vitesse 7385 */ 123 124 #ifdef CONFIG_VSC7385_ENET 125 126 #define CONFIG_TSEC2 127 128 /* The flash address and size of the VSC7385 firmware image */ 129 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 130 #define CONFIG_VSC7385_IMAGE_SIZE 8192 131 132 #endif 133 134 /* 135 * DDR Setup 136 */ 137 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 139 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 140 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 141 #define CONFIG_SYS_83XX_DDR_USES_CS0 142 143 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 144 145 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 146 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 147 148 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 149 150 /* 151 * Manually set up DDR parameters 152 */ 153 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 154 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 155 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 156 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 157 | CSCONFIG_ROW_BIT_13 \ 158 | CSCONFIG_COL_BIT_10) 159 160 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 161 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 162 | (0 << TIMING_CFG0_WRT_SHIFT) \ 163 | (0 << TIMING_CFG0_RRT_SHIFT) \ 164 | (0 << TIMING_CFG0_WWT_SHIFT) \ 165 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 166 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 167 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 168 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 169 /* 0x00260802 */ /* DDR400 */ 170 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 171 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 172 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 173 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 174 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 175 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 176 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 177 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 178 /* 0x3937d322 */ 179 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 180 | (5 << TIMING_CFG2_CPO_SHIFT) \ 181 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 182 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 183 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 184 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 185 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 186 /* 0x02984cc8 */ 187 188 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 189 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 190 /* 0x06090100 */ 191 192 #if defined(CONFIG_DDR_2T_TIMING) 193 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 194 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 195 | SDRAM_CFG_32_BE \ 196 | SDRAM_CFG_2T_EN) 197 /* 0x43088000 */ 198 #else 199 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 200 | SDRAM_CFG_SDRAM_TYPE_DDR2) 201 /* 0x43000000 */ 202 #endif 203 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 204 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 205 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 206 /* 0x04400442 */ /* DDR400 */ 207 #define CONFIG_SYS_DDR_MODE2 0x00000000 208 209 /* 210 * Memory test 211 */ 212 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 213 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 214 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 215 216 /* 217 * The reserved memory 218 */ 219 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 220 221 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 222 #define CONFIG_SYS_RAMBOOT 223 #else 224 #undef CONFIG_SYS_RAMBOOT 225 #endif 226 227 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 228 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 229 230 /* 231 * Initial RAM Base Address Setup 232 */ 233 #define CONFIG_SYS_INIT_RAM_LOCK 1 234 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 235 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 236 #define CONFIG_SYS_GBL_DATA_OFFSET \ 237 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 238 239 /* 240 * Local Bus Configuration & Clock Setup 241 */ 242 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 243 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 244 #define CONFIG_SYS_LBC_LBCR 0x00000000 245 #define CONFIG_FSL_ELBC 1 246 247 /* 248 * FLASH on the Local Bus 249 */ 250 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 251 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 252 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 253 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 254 255 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 256 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 257 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 258 259 /* Window base at flash base */ 260 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 261 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 262 263 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 264 | BR_PS_16 /* 16 bit port */ \ 265 | BR_MS_GPCM /* MSEL = GPCM */ \ 266 | BR_V) /* valid */ 267 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 268 | OR_GPCM_XACS \ 269 | OR_GPCM_SCY_9 \ 270 | OR_GPCM_EHTR_SET \ 271 | OR_GPCM_EAD) 272 /* 0xFF800191 */ 273 274 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 275 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 276 277 #undef CONFIG_SYS_FLASH_CHECKSUM 278 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 279 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 280 281 /* 282 * NAND Flash on the Local Bus 283 */ 284 #define CONFIG_SYS_NAND_BASE 0xE0600000 285 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 286 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 287 | BR_PS_8 /* 8 bit port */ \ 288 | BR_MS_FCM /* MSEL = FCM */ \ 289 | BR_V) /* valid */ 290 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 291 | OR_FCM_CSCT \ 292 | OR_FCM_CST \ 293 | OR_FCM_CHT \ 294 | OR_FCM_SCY_1 \ 295 | OR_FCM_TRLX \ 296 | OR_FCM_EHTR) 297 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 298 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 299 300 /* Vitesse 7385 */ 301 302 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 303 304 #ifdef CONFIG_VSC7385_ENET 305 306 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 307 | BR_PS_8 \ 308 | BR_MS_GPCM \ 309 | BR_V) 310 /* 0xF0000801 */ 311 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 312 | OR_GPCM_CSNT \ 313 | OR_GPCM_XACS \ 314 | OR_GPCM_SCY_15 \ 315 | OR_GPCM_SETA \ 316 | OR_GPCM_TRLX_SET \ 317 | OR_GPCM_EHTR_SET \ 318 | OR_GPCM_EAD) 319 /* 0xfffe09ff */ 320 321 /* Access Base */ 322 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 323 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 324 325 #endif 326 327 /* 328 * Serial Port 329 */ 330 #define CONFIG_CONS_INDEX 1 331 #define CONFIG_SYS_NS16550_SERIAL 332 #define CONFIG_SYS_NS16550_REG_SIZE 1 333 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 334 335 #define CONFIG_SYS_BAUDRATE_TABLE \ 336 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 337 338 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 339 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 340 341 /* SERDES */ 342 #define CONFIG_FSL_SERDES 343 #define CONFIG_FSL_SERDES1 0xe3000 344 #define CONFIG_FSL_SERDES2 0xe3100 345 346 /* I2C */ 347 #define CONFIG_SYS_I2C 348 #define CONFIG_SYS_I2C_FSL 349 #define CONFIG_SYS_FSL_I2C_SPEED 400000 350 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 351 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 352 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 353 354 /* 355 * Config on-board RTC 356 */ 357 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 358 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 359 360 /* 361 * General PCI 362 * Addresses are mapped 1-1. 363 */ 364 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 365 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 366 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 368 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 369 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 370 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 371 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 372 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 373 374 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 375 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 376 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 377 378 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 379 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 380 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 381 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 382 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 383 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 384 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 385 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 386 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 387 388 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 389 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 390 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 391 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 392 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 393 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 394 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 395 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 396 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 397 398 #ifdef CONFIG_PCI 399 #define CONFIG_PCI_INDIRECT_BRIDGE 400 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 401 402 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 403 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 404 #endif /* CONFIG_PCI */ 405 406 /* 407 * TSEC 408 */ 409 #ifdef CONFIG_TSEC_ENET 410 411 #define CONFIG_GMII /* MII PHY management */ 412 413 #define CONFIG_TSEC1 414 415 #ifdef CONFIG_TSEC1 416 #define CONFIG_HAS_ETH0 417 #define CONFIG_TSEC1_NAME "TSEC0" 418 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 419 #define TSEC1_PHY_ADDR 2 420 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 421 #define TSEC1_PHYIDX 0 422 #endif 423 424 #ifdef CONFIG_TSEC2 425 #define CONFIG_HAS_ETH1 426 #define CONFIG_TSEC2_NAME "TSEC1" 427 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 428 #define TSEC2_PHY_ADDR 0x1c 429 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 430 #define TSEC2_PHYIDX 0 431 #endif 432 433 /* Options are: TSEC[0-1] */ 434 #define CONFIG_ETHPRIME "TSEC0" 435 436 #endif 437 438 /* 439 * SATA 440 */ 441 #define CONFIG_LIBATA 442 #define CONFIG_FSL_SATA 443 444 #define CONFIG_SYS_SATA_MAX_DEVICE 2 445 #define CONFIG_SATA1 446 #define CONFIG_SYS_SATA1_OFFSET 0x18000 447 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 448 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 449 #define CONFIG_SATA2 450 #define CONFIG_SYS_SATA2_OFFSET 0x19000 451 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 452 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 453 454 #ifdef CONFIG_FSL_SATA 455 #define CONFIG_LBA48 456 #define CONFIG_CMD_SATA 457 #define CONFIG_DOS_PARTITION 458 #endif 459 460 /* 461 * Environment 462 */ 463 #ifndef CONFIG_SYS_RAMBOOT 464 #define CONFIG_ENV_IS_IN_FLASH 1 465 #define CONFIG_ENV_ADDR \ 466 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 467 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 468 #define CONFIG_ENV_SIZE 0x4000 469 #else 470 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 471 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 472 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 473 #define CONFIG_ENV_SIZE 0x2000 474 #endif 475 476 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 477 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 478 479 /* 480 * BOOTP options 481 */ 482 #define CONFIG_BOOTP_BOOTFILESIZE 483 #define CONFIG_BOOTP_BOOTPATH 484 #define CONFIG_BOOTP_GATEWAY 485 #define CONFIG_BOOTP_HOSTNAME 486 487 /* 488 * Command line configuration. 489 */ 490 #define CONFIG_CMD_DATE 491 492 #if defined(CONFIG_PCI) 493 #define CONFIG_CMD_PCI 494 #endif 495 496 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 497 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 498 499 #undef CONFIG_WATCHDOG /* watchdog disabled */ 500 501 #define CONFIG_MMC 1 502 503 #ifdef CONFIG_MMC 504 #define CONFIG_FSL_ESDHC 505 #define CONFIG_FSL_ESDHC_PIN_MUX 506 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 507 #define CONFIG_GENERIC_MMC 508 #define CONFIG_DOS_PARTITION 509 #endif 510 511 /* 512 * Miscellaneous configurable options 513 */ 514 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 515 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 516 517 #if defined(CONFIG_CMD_KGDB) 518 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 519 #else 520 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 521 #endif 522 523 /* Print Buffer Size */ 524 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 525 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 526 /* Boot Argument Buffer Size */ 527 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 528 529 /* 530 * For booting Linux, the board info and command line data 531 * have to be in the first 256 MB of memory, since this is 532 * the maximum mapped by the Linux kernel during initialization. 533 */ 534 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 535 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 536 537 /* 538 * Core HID Setup 539 */ 540 #define CONFIG_SYS_HID0_INIT 0x000000000 541 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 542 | HID0_ENABLE_INSTRUCTION_CACHE) 543 #define CONFIG_SYS_HID2 HID2_HBE 544 545 /* 546 * MMU Setup 547 */ 548 549 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 550 551 /* DDR: cache cacheable */ 552 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 553 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 554 555 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 556 | BATL_PP_RW \ 557 | BATL_MEMCOHERENCE) 558 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 559 | BATU_BL_256M \ 560 | BATU_VS \ 561 | BATU_VP) 562 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 563 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 564 565 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 566 | BATL_PP_RW \ 567 | BATL_MEMCOHERENCE) 568 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 569 | BATU_BL_256M \ 570 | BATU_VS \ 571 | BATU_VP) 572 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 573 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 574 575 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 576 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 577 | BATL_PP_RW \ 578 | BATL_CACHEINHIBIT \ 579 | BATL_GUARDEDSTORAGE) 580 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 581 | BATU_BL_8M \ 582 | BATU_VS \ 583 | BATU_VP) 584 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 585 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 586 587 /* L2 Switch: cache-inhibit and guarded */ 588 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ 589 | BATL_PP_RW \ 590 | BATL_CACHEINHIBIT \ 591 | BATL_GUARDEDSTORAGE) 592 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ 593 | BATU_BL_128K \ 594 | BATU_VS \ 595 | BATU_VP) 596 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 597 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 598 599 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 600 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 601 | BATL_PP_RW \ 602 | BATL_MEMCOHERENCE) 603 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 604 | BATU_BL_32M \ 605 | BATU_VS \ 606 | BATU_VP) 607 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 608 | BATL_PP_RW \ 609 | BATL_CACHEINHIBIT \ 610 | BATL_GUARDEDSTORAGE) 611 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 612 613 /* Stack in dcache: cacheable, no memory coherence */ 614 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 615 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 616 | BATU_BL_128K \ 617 | BATU_VS \ 618 | BATU_VP) 619 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 620 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 621 622 #ifdef CONFIG_PCI 623 /* PCI MEM space: cacheable */ 624 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 625 | BATL_PP_RW \ 626 | BATL_MEMCOHERENCE) 627 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 628 | BATU_BL_256M \ 629 | BATU_VS \ 630 | BATU_VP) 631 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 632 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 633 /* PCI MMIO space: cache-inhibit and guarded */ 634 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 635 | BATL_PP_RW \ 636 | BATL_CACHEINHIBIT \ 637 | BATL_GUARDEDSTORAGE) 638 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 639 | BATU_BL_256M \ 640 | BATU_VS \ 641 | BATU_VP) 642 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 643 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 644 #else 645 #define CONFIG_SYS_IBAT6L (0) 646 #define CONFIG_SYS_IBAT6U (0) 647 #define CONFIG_SYS_IBAT7L (0) 648 #define CONFIG_SYS_IBAT7U (0) 649 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 650 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 651 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 652 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 653 #endif 654 655 #if defined(CONFIG_CMD_KGDB) 656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 657 #endif 658 659 /* 660 * Environment Configuration 661 */ 662 #define CONFIG_ENV_OVERWRITE 663 664 #define CONFIG_HAS_FSL_DR_USB 665 #define CONFIG_USB_EHCI 666 #define CONFIG_USB_EHCI_FSL 667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 668 669 #define CONFIG_NETDEV "eth1" 670 671 #define CONFIG_HOSTNAME mpc837x_rdb 672 #define CONFIG_ROOTPATH "/nfsroot" 673 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 674 #define CONFIG_BOOTFILE "uImage" 675 /* U-Boot image on TFTP server */ 676 #define CONFIG_UBOOTPATH "u-boot.bin" 677 #define CONFIG_FDTFILE "mpc8379_rdb.dtb" 678 679 /* default location for tftp and bootm */ 680 #define CONFIG_LOADADDR 800000 681 #define CONFIG_BAUDRATE 115200 682 683 #define CONFIG_EXTRA_ENV_SETTINGS \ 684 "netdev=" CONFIG_NETDEV "\0" \ 685 "uboot=" CONFIG_UBOOTPATH "\0" \ 686 "tftpflash=tftp $loadaddr $uboot;" \ 687 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 688 " +$filesize; " \ 689 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 690 " +$filesize; " \ 691 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 692 " $filesize; " \ 693 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 694 " +$filesize; " \ 695 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 696 " $filesize\0" \ 697 "fdtaddr=780000\0" \ 698 "fdtfile=" CONFIG_FDTFILE "\0" \ 699 "ramdiskaddr=1000000\0" \ 700 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 701 "console=ttyS0\0" \ 702 "setbootargs=setenv bootargs " \ 703 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 704 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 705 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 706 "$netdev:off " \ 707 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 708 709 #define CONFIG_NFSBOOTCOMMAND \ 710 "setenv rootdev /dev/nfs;" \ 711 "run setbootargs;" \ 712 "run setipargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_RAMBOOTCOMMAND \ 718 "setenv rootdev /dev/ram;" \ 719 "run setbootargs;" \ 720 "tftp $ramdiskaddr $ramdiskfile;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr $ramdiskaddr $fdtaddr" 724 725 #endif /* __CONFIG_H */ 726