1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_E300 1 /* E300 family */ 29 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 30 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 31 #define CONFIG_MPC837XERDB 1 32 33 #define CONFIG_SYS_TEXT_BASE 0xFE000000 34 35 #define CONFIG_PCI 1 36 37 #define CONFIG_BOARD_EARLY_INIT_F 38 #define CONFIG_MISC_INIT_R 39 #define CONFIG_HWCONFIG 40 41 /* 42 * On-board devices 43 */ 44 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 45 #define CONFIG_VSC7385_ENET 46 47 /* 48 * System Clock Setup 49 */ 50 #ifdef CONFIG_PCISLAVE 51 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 52 #else 53 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 54 #define CONFIG_PCIE 55 #endif 56 57 #ifndef CONFIG_SYS_CLK_FREQ 58 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 59 #endif 60 61 /* 62 * Hardware Reset Configuration Word 63 */ 64 #define CONFIG_SYS_HRCW_LOW (\ 65 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 66 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 67 HRCWL_SVCOD_DIV_2 |\ 68 HRCWL_CSB_TO_CLKIN_5X1 |\ 69 HRCWL_CORE_TO_CSB_2X1) 70 71 #ifdef CONFIG_PCISLAVE 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_PCI_AGENT |\ 74 HRCWH_PCI1_ARBITER_DISABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0XFFF00100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_RL_EXT_LEGACY |\ 81 HRCWH_TSEC1M_IN_RGMII |\ 82 HRCWH_TSEC2M_IN_RGMII |\ 83 HRCWH_BIG_ENDIAN |\ 84 HRCWH_LDP_CLEAR) 85 #else 86 #define CONFIG_SYS_HRCW_HIGH (\ 87 HRCWH_PCI_HOST |\ 88 HRCWH_PCI1_ARBITER_ENABLE |\ 89 HRCWH_CORE_ENABLE |\ 90 HRCWH_FROM_0X00000100 |\ 91 HRCWH_BOOTSEQ_DISABLE |\ 92 HRCWH_SW_WATCHDOG_DISABLE |\ 93 HRCWH_ROM_LOC_LOCAL_16BIT |\ 94 HRCWH_RL_EXT_LEGACY |\ 95 HRCWH_TSEC1M_IN_RGMII |\ 96 HRCWH_TSEC2M_IN_RGMII |\ 97 HRCWH_BIG_ENDIAN |\ 98 HRCWH_LDP_CLEAR) 99 #endif 100 101 /* System performance - define the value i.e. CONFIG_SYS_XXX 102 */ 103 104 /* Arbiter Configuration Register */ 105 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 106 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 107 108 /* System Priority Control Regsiter */ 109 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 110 111 /* System Clock Configuration Register */ 112 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 113 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 114 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 115 116 /* 117 * System IO Config 118 */ 119 #define CONFIG_SYS_SICRH 0x08200000 120 #define CONFIG_SYS_SICRL 0x00000000 121 122 /* 123 * Output Buffer Impedance 124 */ 125 #define CONFIG_SYS_OBIR 0x30100000 126 127 /* 128 * IMMR new address 129 */ 130 #define CONFIG_SYS_IMMR 0xE0000000 131 132 /* 133 * Device configurations 134 */ 135 136 /* Vitesse 7385 */ 137 138 #ifdef CONFIG_VSC7385_ENET 139 140 #define CONFIG_TSEC2 141 142 /* The flash address and size of the VSC7385 firmware image */ 143 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 144 #define CONFIG_VSC7385_IMAGE_SIZE 8192 145 146 #endif 147 148 /* 149 * DDR Setup 150 */ 151 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 152 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 153 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 154 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 155 #define CONFIG_SYS_83XX_DDR_USES_CS0 156 157 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 158 159 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 160 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 161 162 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 163 164 /* 165 * Manually set up DDR parameters 166 */ 167 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 168 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 169 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 170 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 171 | CSCONFIG_ROW_BIT_13 \ 172 | CSCONFIG_COL_BIT_10) 173 174 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 175 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 176 | (0 << TIMING_CFG0_WRT_SHIFT) \ 177 | (0 << TIMING_CFG0_RRT_SHIFT) \ 178 | (0 << TIMING_CFG0_WWT_SHIFT) \ 179 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 180 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 181 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 182 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 183 /* 0x00260802 */ /* DDR400 */ 184 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 185 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 186 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 187 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 188 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 189 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 190 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 191 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 192 /* 0x3937d322 */ 193 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 194 | (5 << TIMING_CFG2_CPO_SHIFT) \ 195 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 196 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 197 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 198 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 199 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 200 /* 0x02984cc8 */ 201 202 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 203 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 204 /* 0x06090100 */ 205 206 #if defined(CONFIG_DDR_2T_TIMING) 207 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 208 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 209 | SDRAM_CFG_32_BE \ 210 | SDRAM_CFG_2T_EN) 211 /* 0x43088000 */ 212 #else 213 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 214 | SDRAM_CFG_SDRAM_TYPE_DDR2) 215 /* 0x43000000 */ 216 #endif 217 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 218 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 219 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 220 /* 0x04400442 */ /* DDR400 */ 221 #define CONFIG_SYS_DDR_MODE2 0x00000000 222 223 /* 224 * Memory test 225 */ 226 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 227 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 228 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 229 230 /* 231 * The reserved memory 232 */ 233 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 234 235 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 236 #define CONFIG_SYS_RAMBOOT 237 #else 238 #undef CONFIG_SYS_RAMBOOT 239 #endif 240 241 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 242 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 243 244 /* 245 * Initial RAM Base Address Setup 246 */ 247 #define CONFIG_SYS_INIT_RAM_LOCK 1 248 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 249 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 250 #define CONFIG_SYS_GBL_DATA_OFFSET \ 251 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 252 253 /* 254 * Local Bus Configuration & Clock Setup 255 */ 256 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 257 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 258 #define CONFIG_SYS_LBC_LBCR 0x00000000 259 #define CONFIG_FSL_ELBC 1 260 261 /* 262 * FLASH on the Local Bus 263 */ 264 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 265 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 266 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 267 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 268 269 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 270 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 271 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 272 273 /* Window base at flash base */ 274 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 275 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 276 277 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 278 | BR_PS_16 /* 16 bit port */ \ 279 | BR_MS_GPCM /* MSEL = GPCM */ \ 280 | BR_V) /* valid */ 281 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 282 | OR_GPCM_XACS \ 283 | OR_GPCM_SCY_9 \ 284 | OR_GPCM_EHTR_SET \ 285 | OR_GPCM_EAD) 286 /* 0xFF800191 */ 287 288 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 289 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 290 291 #undef CONFIG_SYS_FLASH_CHECKSUM 292 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 293 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 294 295 /* 296 * NAND Flash on the Local Bus 297 */ 298 #define CONFIG_SYS_NAND_BASE 0xE0600000 299 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 300 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 301 | BR_PS_8 /* 8 bit port */ \ 302 | BR_MS_FCM /* MSEL = FCM */ \ 303 | BR_V) /* valid */ 304 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 305 | OR_FCM_CSCT \ 306 | OR_FCM_CST \ 307 | OR_FCM_CHT \ 308 | OR_FCM_SCY_1 \ 309 | OR_FCM_TRLX \ 310 | OR_FCM_EHTR) 311 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 312 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 313 314 /* Vitesse 7385 */ 315 316 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 317 318 #ifdef CONFIG_VSC7385_ENET 319 320 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 321 | BR_PS_8 \ 322 | BR_MS_GPCM \ 323 | BR_V) 324 /* 0xF0000801 */ 325 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 326 | OR_GPCM_CSNT \ 327 | OR_GPCM_XACS \ 328 | OR_GPCM_SCY_15 \ 329 | OR_GPCM_SETA \ 330 | OR_GPCM_TRLX_SET \ 331 | OR_GPCM_EHTR_SET \ 332 | OR_GPCM_EAD) 333 /* 0xfffe09ff */ 334 335 /* Access Base */ 336 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 337 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 338 339 #endif 340 341 /* 342 * Serial Port 343 */ 344 #define CONFIG_CONS_INDEX 1 345 #define CONFIG_SYS_NS16550 346 #define CONFIG_SYS_NS16550_SERIAL 347 #define CONFIG_SYS_NS16550_REG_SIZE 1 348 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 349 350 #define CONFIG_SYS_BAUDRATE_TABLE \ 351 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 352 353 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 354 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 355 356 /* SERDES */ 357 #define CONFIG_FSL_SERDES 358 #define CONFIG_FSL_SERDES1 0xe3000 359 #define CONFIG_FSL_SERDES2 0xe3100 360 361 /* Use the HUSH parser */ 362 #define CONFIG_SYS_HUSH_PARSER 363 #ifdef CONFIG_SYS_HUSH_PARSER 364 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 365 #endif 366 367 /* Pass open firmware flat tree */ 368 #define CONFIG_OF_LIBFDT 1 369 #define CONFIG_OF_BOARD_SETUP 1 370 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 371 372 /* I2C */ 373 #define CONFIG_HARD_I2C /* I2C with hardware support */ 374 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 375 #define CONFIG_FSL_I2C 376 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 377 #define CONFIG_SYS_I2C_SLAVE 0x7F 378 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 379 #define CONFIG_SYS_I2C_OFFSET 0x3000 380 #define CONFIG_SYS_I2C2_OFFSET 0x3100 381 382 /* 383 * Config on-board RTC 384 */ 385 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 386 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 387 388 /* 389 * General PCI 390 * Addresses are mapped 1-1. 391 */ 392 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 393 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 394 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 395 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 396 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 397 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 398 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 399 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 400 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 401 402 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 403 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 404 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 405 406 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 407 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 408 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 409 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 410 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 411 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 412 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 413 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 414 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 415 416 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 417 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 418 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 419 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 421 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 422 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 423 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 424 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 425 426 #ifdef CONFIG_PCI 427 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 428 429 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 430 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 431 #endif /* CONFIG_PCI */ 432 433 /* 434 * TSEC 435 */ 436 #ifdef CONFIG_TSEC_ENET 437 438 #define CONFIG_GMII /* MII PHY management */ 439 440 #define CONFIG_TSEC1 441 442 #ifdef CONFIG_TSEC1 443 #define CONFIG_HAS_ETH0 444 #define CONFIG_TSEC1_NAME "TSEC0" 445 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 446 #define TSEC1_PHY_ADDR 2 447 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 448 #define TSEC1_PHYIDX 0 449 #endif 450 451 #ifdef CONFIG_TSEC2 452 #define CONFIG_HAS_ETH1 453 #define CONFIG_TSEC2_NAME "TSEC1" 454 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 455 #define TSEC2_PHY_ADDR 0x1c 456 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 457 #define TSEC2_PHYIDX 0 458 #endif 459 460 /* Options are: TSEC[0-1] */ 461 #define CONFIG_ETHPRIME "TSEC0" 462 463 #endif 464 465 /* 466 * SATA 467 */ 468 #define CONFIG_LIBATA 469 #define CONFIG_FSL_SATA 470 471 #define CONFIG_SYS_SATA_MAX_DEVICE 2 472 #define CONFIG_SATA1 473 #define CONFIG_SYS_SATA1_OFFSET 0x18000 474 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 475 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 476 #define CONFIG_SATA2 477 #define CONFIG_SYS_SATA2_OFFSET 0x19000 478 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 479 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 480 481 #ifdef CONFIG_FSL_SATA 482 #define CONFIG_LBA48 483 #define CONFIG_CMD_SATA 484 #define CONFIG_DOS_PARTITION 485 #define CONFIG_CMD_EXT2 486 #endif 487 488 /* 489 * Environment 490 */ 491 #ifndef CONFIG_SYS_RAMBOOT 492 #define CONFIG_ENV_IS_IN_FLASH 1 493 #define CONFIG_ENV_ADDR \ 494 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 495 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 496 #define CONFIG_ENV_SIZE 0x4000 497 #else 498 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 499 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 500 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 501 #define CONFIG_ENV_SIZE 0x2000 502 #endif 503 504 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 505 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 506 507 /* 508 * BOOTP options 509 */ 510 #define CONFIG_BOOTP_BOOTFILESIZE 511 #define CONFIG_BOOTP_BOOTPATH 512 #define CONFIG_BOOTP_GATEWAY 513 #define CONFIG_BOOTP_HOSTNAME 514 515 516 /* 517 * Command line configuration. 518 */ 519 #include <config_cmd_default.h> 520 521 #define CONFIG_CMD_PING 522 #define CONFIG_CMD_I2C 523 #define CONFIG_CMD_MII 524 #define CONFIG_CMD_DATE 525 526 #if defined(CONFIG_PCI) 527 #define CONFIG_CMD_PCI 528 #endif 529 530 #if defined(CONFIG_SYS_RAMBOOT) 531 #undef CONFIG_CMD_SAVEENV 532 #undef CONFIG_CMD_LOADS 533 #endif 534 535 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 536 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 537 538 #undef CONFIG_WATCHDOG /* watchdog disabled */ 539 540 #define CONFIG_MMC 1 541 542 #ifdef CONFIG_MMC 543 #define CONFIG_FSL_ESDHC 544 #define CONFIG_FSL_ESDHC_PIN_MUX 545 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 546 #define CONFIG_CMD_MMC 547 #define CONFIG_GENERIC_MMC 548 #define CONFIG_CMD_EXT2 549 #define CONFIG_CMD_FAT 550 #define CONFIG_DOS_PARTITION 551 #endif 552 553 /* 554 * Miscellaneous configurable options 555 */ 556 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 557 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 558 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 559 560 #if defined(CONFIG_CMD_KGDB) 561 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 562 #else 563 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 564 #endif 565 566 /* Print Buffer Size */ 567 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 568 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 569 /* Boot Argument Buffer Size */ 570 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 571 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 572 573 /* 574 * For booting Linux, the board info and command line data 575 * have to be in the first 256 MB of memory, since this is 576 * the maximum mapped by the Linux kernel during initialization. 577 */ 578 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 579 580 /* 581 * Core HID Setup 582 */ 583 #define CONFIG_SYS_HID0_INIT 0x000000000 584 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 585 | HID0_ENABLE_INSTRUCTION_CACHE) 586 #define CONFIG_SYS_HID2 HID2_HBE 587 588 /* 589 * MMU Setup 590 */ 591 592 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 593 594 /* DDR: cache cacheable */ 595 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 596 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 597 598 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 599 | BATL_PP_RW \ 600 | BATL_MEMCOHERENCE) 601 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 602 | BATU_BL_256M \ 603 | BATU_VS \ 604 | BATU_VP) 605 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 606 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 607 608 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 609 | BATL_PP_RW \ 610 | BATL_MEMCOHERENCE) 611 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 612 | BATU_BL_256M \ 613 | BATU_VS \ 614 | BATU_VP) 615 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 616 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 617 618 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 619 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 620 | BATL_PP_RW \ 621 | BATL_CACHEINHIBIT \ 622 | BATL_GUARDEDSTORAGE) 623 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 624 | BATU_BL_8M \ 625 | BATU_VS \ 626 | BATU_VP) 627 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 628 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 629 630 /* L2 Switch: cache-inhibit and guarded */ 631 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ 632 | BATL_PP_RW \ 633 | BATL_CACHEINHIBIT \ 634 | BATL_GUARDEDSTORAGE) 635 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ 636 | BATU_BL_128K \ 637 | BATU_VS \ 638 | BATU_VP) 639 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 640 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 641 642 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 643 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 644 | BATL_PP_RW \ 645 | BATL_MEMCOHERENCE) 646 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 647 | BATU_BL_32M \ 648 | BATU_VS \ 649 | BATU_VP) 650 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 651 | BATL_PP_RW \ 652 | BATL_CACHEINHIBIT \ 653 | BATL_GUARDEDSTORAGE) 654 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 655 656 /* Stack in dcache: cacheable, no memory coherence */ 657 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 658 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 659 | BATU_BL_128K \ 660 | BATU_VS \ 661 | BATU_VP) 662 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 663 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 664 665 #ifdef CONFIG_PCI 666 /* PCI MEM space: cacheable */ 667 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 668 | BATL_PP_RW \ 669 | BATL_MEMCOHERENCE) 670 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 671 | BATU_BL_256M \ 672 | BATU_VS \ 673 | BATU_VP) 674 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 675 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 676 /* PCI MMIO space: cache-inhibit and guarded */ 677 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 678 | BATL_PP_RW \ 679 | BATL_CACHEINHIBIT \ 680 | BATL_GUARDEDSTORAGE) 681 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 682 | BATU_BL_256M \ 683 | BATU_VS \ 684 | BATU_VP) 685 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 686 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 687 #else 688 #define CONFIG_SYS_IBAT6L (0) 689 #define CONFIG_SYS_IBAT6U (0) 690 #define CONFIG_SYS_IBAT7L (0) 691 #define CONFIG_SYS_IBAT7U (0) 692 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 693 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 694 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 695 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 696 #endif 697 698 #if defined(CONFIG_CMD_KGDB) 699 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 700 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 701 #endif 702 703 /* 704 * Environment Configuration 705 */ 706 #define CONFIG_ENV_OVERWRITE 707 708 #define CONFIG_HAS_FSL_DR_USB 709 710 #define CONFIG_NETDEV "eth1" 711 712 #define CONFIG_HOSTNAME mpc837x_rdb 713 #define CONFIG_ROOTPATH "/nfsroot" 714 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 715 #define CONFIG_BOOTFILE "uImage" 716 /* U-Boot image on TFTP server */ 717 #define CONFIG_UBOOTPATH "u-boot.bin" 718 #define CONFIG_FDTFILE "mpc8379_rdb.dtb" 719 720 /* default location for tftp and bootm */ 721 #define CONFIG_LOADADDR 800000 722 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 723 #define CONFIG_BAUDRATE 115200 724 725 #define XMK_STR(x) #x 726 #define MK_STR(x) XMK_STR(x) 727 728 #define CONFIG_EXTRA_ENV_SETTINGS \ 729 "netdev=" CONFIG_NETDEV "\0" \ 730 "uboot=" CONFIG_UBOOTPATH "\0" \ 731 "tftpflash=tftp $loadaddr $uboot;" \ 732 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 733 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 734 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 735 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 736 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 737 "fdtaddr=780000\0" \ 738 "fdtfile=" CONFIG_FDTFILE "\0" \ 739 "ramdiskaddr=1000000\0" \ 740 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 741 "console=ttyS0\0" \ 742 "setbootargs=setenv bootargs " \ 743 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 744 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 745 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 746 "$netdev:off " \ 747 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 748 749 #define CONFIG_NFSBOOTCOMMAND \ 750 "setenv rootdev /dev/nfs;" \ 751 "run setbootargs;" \ 752 "run setipargs;" \ 753 "tftp $loadaddr $bootfile;" \ 754 "tftp $fdtaddr $fdtfile;" \ 755 "bootm $loadaddr - $fdtaddr" 756 757 #define CONFIG_RAMBOOTCOMMAND \ 758 "setenv rootdev /dev/ram;" \ 759 "run setbootargs;" \ 760 "tftp $ramdiskaddr $ramdiskfile;" \ 761 "tftp $loadaddr $bootfile;" \ 762 "tftp $fdtaddr $fdtfile;" \ 763 "bootm $loadaddr $ramdiskaddr $fdtaddr" 764 765 #undef MK_STR 766 #undef XMK_STR 767 768 #endif /* __CONFIG_H */ 769