1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 17 #define CONFIG_MPC837XERDB 1 18 19 #define CONFIG_SYS_TEXT_BASE 0xFE000000 20 21 #define CONFIG_MISC_INIT_R 22 #define CONFIG_HWCONFIG 23 24 /* 25 * On-board devices 26 */ 27 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 28 #define CONFIG_VSC7385_ENET 29 30 /* 31 * System Clock Setup 32 */ 33 #ifdef CONFIG_PCISLAVE 34 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 35 #else 36 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 37 #define CONFIG_PCIE 38 #endif 39 40 #ifndef CONFIG_SYS_CLK_FREQ 41 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 42 #endif 43 44 /* 45 * Hardware Reset Configuration Word 46 */ 47 #define CONFIG_SYS_HRCW_LOW (\ 48 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 49 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 50 HRCWL_SVCOD_DIV_2 |\ 51 HRCWL_CSB_TO_CLKIN_5X1 |\ 52 HRCWL_CORE_TO_CSB_2X1) 53 54 #ifdef CONFIG_PCISLAVE 55 #define CONFIG_SYS_HRCW_HIGH (\ 56 HRCWH_PCI_AGENT |\ 57 HRCWH_PCI1_ARBITER_DISABLE |\ 58 HRCWH_CORE_ENABLE |\ 59 HRCWH_FROM_0XFFF00100 |\ 60 HRCWH_BOOTSEQ_DISABLE |\ 61 HRCWH_SW_WATCHDOG_DISABLE |\ 62 HRCWH_ROM_LOC_LOCAL_16BIT |\ 63 HRCWH_RL_EXT_LEGACY |\ 64 HRCWH_TSEC1M_IN_RGMII |\ 65 HRCWH_TSEC2M_IN_RGMII |\ 66 HRCWH_BIG_ENDIAN |\ 67 HRCWH_LDP_CLEAR) 68 #else 69 #define CONFIG_SYS_HRCW_HIGH (\ 70 HRCWH_PCI_HOST |\ 71 HRCWH_PCI1_ARBITER_ENABLE |\ 72 HRCWH_CORE_ENABLE |\ 73 HRCWH_FROM_0X00000100 |\ 74 HRCWH_BOOTSEQ_DISABLE |\ 75 HRCWH_SW_WATCHDOG_DISABLE |\ 76 HRCWH_ROM_LOC_LOCAL_16BIT |\ 77 HRCWH_RL_EXT_LEGACY |\ 78 HRCWH_TSEC1M_IN_RGMII |\ 79 HRCWH_TSEC2M_IN_RGMII |\ 80 HRCWH_BIG_ENDIAN |\ 81 HRCWH_LDP_CLEAR) 82 #endif 83 84 /* System performance - define the value i.e. CONFIG_SYS_XXX 85 */ 86 87 /* Arbiter Configuration Register */ 88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 90 91 /* System Priority Control Regsiter */ 92 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 93 94 /* System Clock Configuration Register */ 95 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 96 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 97 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 98 99 /* 100 * System IO Config 101 */ 102 #define CONFIG_SYS_SICRH 0x08200000 103 #define CONFIG_SYS_SICRL 0x00000000 104 105 /* 106 * Output Buffer Impedance 107 */ 108 #define CONFIG_SYS_OBIR 0x30100000 109 110 /* 111 * IMMR new address 112 */ 113 #define CONFIG_SYS_IMMR 0xE0000000 114 115 /* 116 * Device configurations 117 */ 118 119 /* Vitesse 7385 */ 120 121 #ifdef CONFIG_VSC7385_ENET 122 123 #define CONFIG_TSEC2 124 125 /* The flash address and size of the VSC7385 firmware image */ 126 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 127 #define CONFIG_VSC7385_IMAGE_SIZE 8192 128 129 #endif 130 131 /* 132 * DDR Setup 133 */ 134 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 136 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 137 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 138 #define CONFIG_SYS_83XX_DDR_USES_CS0 139 140 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 141 142 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 143 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 144 145 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 146 147 /* 148 * Manually set up DDR parameters 149 */ 150 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 151 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 152 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 153 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 154 | CSCONFIG_ROW_BIT_13 \ 155 | CSCONFIG_COL_BIT_10) 156 157 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 158 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 159 | (0 << TIMING_CFG0_WRT_SHIFT) \ 160 | (0 << TIMING_CFG0_RRT_SHIFT) \ 161 | (0 << TIMING_CFG0_WWT_SHIFT) \ 162 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 163 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 164 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 165 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 166 /* 0x00260802 */ /* DDR400 */ 167 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 168 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 169 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 170 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 171 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 172 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 173 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 174 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 175 /* 0x3937d322 */ 176 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 177 | (5 << TIMING_CFG2_CPO_SHIFT) \ 178 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 179 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 180 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 181 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 182 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 183 /* 0x02984cc8 */ 184 185 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 186 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 187 /* 0x06090100 */ 188 189 #if defined(CONFIG_DDR_2T_TIMING) 190 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 191 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 192 | SDRAM_CFG_32_BE \ 193 | SDRAM_CFG_2T_EN) 194 /* 0x43088000 */ 195 #else 196 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 197 | SDRAM_CFG_SDRAM_TYPE_DDR2) 198 /* 0x43000000 */ 199 #endif 200 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 201 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 202 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 203 /* 0x04400442 */ /* DDR400 */ 204 #define CONFIG_SYS_DDR_MODE2 0x00000000 205 206 /* 207 * Memory test 208 */ 209 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 210 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 211 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 212 213 /* 214 * The reserved memory 215 */ 216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 217 218 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 219 #define CONFIG_SYS_RAMBOOT 220 #else 221 #undef CONFIG_SYS_RAMBOOT 222 #endif 223 224 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 225 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 226 227 /* 228 * Initial RAM Base Address Setup 229 */ 230 #define CONFIG_SYS_INIT_RAM_LOCK 1 231 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 232 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 233 #define CONFIG_SYS_GBL_DATA_OFFSET \ 234 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 235 236 /* 237 * Local Bus Configuration & Clock Setup 238 */ 239 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 240 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 241 #define CONFIG_SYS_LBC_LBCR 0x00000000 242 #define CONFIG_FSL_ELBC 1 243 244 /* 245 * FLASH on the Local Bus 246 */ 247 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 248 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 249 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 250 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 251 252 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 253 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 254 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 255 256 /* Window base at flash base */ 257 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 258 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 259 260 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 261 | BR_PS_16 /* 16 bit port */ \ 262 | BR_MS_GPCM /* MSEL = GPCM */ \ 263 | BR_V) /* valid */ 264 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 265 | OR_GPCM_XACS \ 266 | OR_GPCM_SCY_9 \ 267 | OR_GPCM_EHTR_SET \ 268 | OR_GPCM_EAD) 269 /* 0xFF800191 */ 270 271 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 272 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 273 274 #undef CONFIG_SYS_FLASH_CHECKSUM 275 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 276 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 277 278 /* 279 * NAND Flash on the Local Bus 280 */ 281 #define CONFIG_SYS_NAND_BASE 0xE0600000 282 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 283 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 284 | BR_PS_8 /* 8 bit port */ \ 285 | BR_MS_FCM /* MSEL = FCM */ \ 286 | BR_V) /* valid */ 287 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 288 | OR_FCM_CSCT \ 289 | OR_FCM_CST \ 290 | OR_FCM_CHT \ 291 | OR_FCM_SCY_1 \ 292 | OR_FCM_TRLX \ 293 | OR_FCM_EHTR) 294 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 295 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 296 297 /* Vitesse 7385 */ 298 299 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 300 301 #ifdef CONFIG_VSC7385_ENET 302 303 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 304 | BR_PS_8 \ 305 | BR_MS_GPCM \ 306 | BR_V) 307 /* 0xF0000801 */ 308 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 309 | OR_GPCM_CSNT \ 310 | OR_GPCM_XACS \ 311 | OR_GPCM_SCY_15 \ 312 | OR_GPCM_SETA \ 313 | OR_GPCM_TRLX_SET \ 314 | OR_GPCM_EHTR_SET \ 315 | OR_GPCM_EAD) 316 /* 0xfffe09ff */ 317 318 /* Access Base */ 319 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 320 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 321 322 #endif 323 324 /* 325 * Serial Port 326 */ 327 #define CONFIG_CONS_INDEX 1 328 #define CONFIG_SYS_NS16550_SERIAL 329 #define CONFIG_SYS_NS16550_REG_SIZE 1 330 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 331 332 #define CONFIG_SYS_BAUDRATE_TABLE \ 333 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 334 335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 337 338 /* SERDES */ 339 #define CONFIG_FSL_SERDES 340 #define CONFIG_FSL_SERDES1 0xe3000 341 #define CONFIG_FSL_SERDES2 0xe3100 342 343 /* I2C */ 344 #define CONFIG_SYS_I2C 345 #define CONFIG_SYS_I2C_FSL 346 #define CONFIG_SYS_FSL_I2C_SPEED 400000 347 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 348 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 349 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 350 351 /* 352 * Config on-board RTC 353 */ 354 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 355 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 356 357 /* 358 * General PCI 359 * Addresses are mapped 1-1. 360 */ 361 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 362 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 363 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 364 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 365 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 366 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 368 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 369 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 370 371 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 372 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 373 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 374 375 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 376 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 377 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 378 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 379 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 380 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 381 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 382 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 383 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 384 385 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 386 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 387 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 388 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 389 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 390 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 391 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 392 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 393 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 394 395 #ifdef CONFIG_PCI 396 #define CONFIG_PCI_INDIRECT_BRIDGE 397 398 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 399 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 400 #endif /* CONFIG_PCI */ 401 402 /* 403 * TSEC 404 */ 405 #ifdef CONFIG_TSEC_ENET 406 407 #define CONFIG_GMII /* MII PHY management */ 408 409 #define CONFIG_TSEC1 410 411 #ifdef CONFIG_TSEC1 412 #define CONFIG_HAS_ETH0 413 #define CONFIG_TSEC1_NAME "TSEC0" 414 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 415 #define TSEC1_PHY_ADDR 2 416 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC1_PHYIDX 0 418 #endif 419 420 #ifdef CONFIG_TSEC2 421 #define CONFIG_HAS_ETH1 422 #define CONFIG_TSEC2_NAME "TSEC1" 423 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 424 #define TSEC2_PHY_ADDR 0x1c 425 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 #define TSEC2_PHYIDX 0 427 #endif 428 429 /* Options are: TSEC[0-1] */ 430 #define CONFIG_ETHPRIME "TSEC0" 431 432 #endif 433 434 /* 435 * SATA 436 */ 437 #define CONFIG_LIBATA 438 #define CONFIG_FSL_SATA 439 440 #define CONFIG_SYS_SATA_MAX_DEVICE 2 441 #define CONFIG_SATA1 442 #define CONFIG_SYS_SATA1_OFFSET 0x18000 443 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 444 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 445 #define CONFIG_SATA2 446 #define CONFIG_SYS_SATA2_OFFSET 0x19000 447 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 448 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 449 450 #ifdef CONFIG_FSL_SATA 451 #define CONFIG_LBA48 452 #endif 453 454 /* 455 * Environment 456 */ 457 #ifndef CONFIG_SYS_RAMBOOT 458 #define CONFIG_ENV_ADDR \ 459 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 460 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 461 #define CONFIG_ENV_SIZE 0x4000 462 #else 463 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 464 #define CONFIG_ENV_SIZE 0x2000 465 #endif 466 467 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 468 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 469 470 /* 471 * BOOTP options 472 */ 473 #define CONFIG_BOOTP_BOOTFILESIZE 474 #define CONFIG_BOOTP_BOOTPATH 475 #define CONFIG_BOOTP_GATEWAY 476 #define CONFIG_BOOTP_HOSTNAME 477 478 /* 479 * Command line configuration. 480 */ 481 482 #if defined(CONFIG_PCI) 483 #define CONFIG_CMD_PCI 484 #endif 485 486 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 487 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 488 489 #undef CONFIG_WATCHDOG /* watchdog disabled */ 490 491 #ifdef CONFIG_MMC 492 #define CONFIG_FSL_ESDHC 493 #define CONFIG_FSL_ESDHC_PIN_MUX 494 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 495 #endif 496 497 /* 498 * Miscellaneous configurable options 499 */ 500 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 501 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 502 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 505 #else 506 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 507 #endif 508 509 /* Print Buffer Size */ 510 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 511 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 512 /* Boot Argument Buffer Size */ 513 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 514 515 /* 516 * For booting Linux, the board info and command line data 517 * have to be in the first 256 MB of memory, since this is 518 * the maximum mapped by the Linux kernel during initialization. 519 */ 520 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 521 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 522 523 /* 524 * Core HID Setup 525 */ 526 #define CONFIG_SYS_HID0_INIT 0x000000000 527 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 528 | HID0_ENABLE_INSTRUCTION_CACHE) 529 #define CONFIG_SYS_HID2 HID2_HBE 530 531 /* 532 * MMU Setup 533 */ 534 535 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 536 537 /* DDR: cache cacheable */ 538 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 539 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 540 541 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 542 | BATL_PP_RW \ 543 | BATL_MEMCOHERENCE) 544 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 545 | BATU_BL_256M \ 546 | BATU_VS \ 547 | BATU_VP) 548 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 549 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 550 551 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 552 | BATL_PP_RW \ 553 | BATL_MEMCOHERENCE) 554 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 555 | BATU_BL_256M \ 556 | BATU_VS \ 557 | BATU_VP) 558 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 559 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 560 561 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 562 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 563 | BATL_PP_RW \ 564 | BATL_CACHEINHIBIT \ 565 | BATL_GUARDEDSTORAGE) 566 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 567 | BATU_BL_8M \ 568 | BATU_VS \ 569 | BATU_VP) 570 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 571 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 572 573 /* L2 Switch: cache-inhibit and guarded */ 574 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ 575 | BATL_PP_RW \ 576 | BATL_CACHEINHIBIT \ 577 | BATL_GUARDEDSTORAGE) 578 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ 579 | BATU_BL_128K \ 580 | BATU_VS \ 581 | BATU_VP) 582 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 583 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 584 585 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 586 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 587 | BATL_PP_RW \ 588 | BATL_MEMCOHERENCE) 589 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 590 | BATU_BL_32M \ 591 | BATU_VS \ 592 | BATU_VP) 593 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 594 | BATL_PP_RW \ 595 | BATL_CACHEINHIBIT \ 596 | BATL_GUARDEDSTORAGE) 597 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 598 599 /* Stack in dcache: cacheable, no memory coherence */ 600 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 601 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 602 | BATU_BL_128K \ 603 | BATU_VS \ 604 | BATU_VP) 605 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 606 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 607 608 #ifdef CONFIG_PCI 609 /* PCI MEM space: cacheable */ 610 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 611 | BATL_PP_RW \ 612 | BATL_MEMCOHERENCE) 613 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 614 | BATU_BL_256M \ 615 | BATU_VS \ 616 | BATU_VP) 617 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 618 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 619 /* PCI MMIO space: cache-inhibit and guarded */ 620 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 621 | BATL_PP_RW \ 622 | BATL_CACHEINHIBIT \ 623 | BATL_GUARDEDSTORAGE) 624 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 625 | BATU_BL_256M \ 626 | BATU_VS \ 627 | BATU_VP) 628 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 629 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 630 #else 631 #define CONFIG_SYS_IBAT6L (0) 632 #define CONFIG_SYS_IBAT6U (0) 633 #define CONFIG_SYS_IBAT7L (0) 634 #define CONFIG_SYS_IBAT7U (0) 635 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 636 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 637 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 638 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 639 #endif 640 641 #if defined(CONFIG_CMD_KGDB) 642 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 643 #endif 644 645 /* 646 * Environment Configuration 647 */ 648 #define CONFIG_ENV_OVERWRITE 649 650 #define CONFIG_HAS_FSL_DR_USB 651 #define CONFIG_USB_EHCI_FSL 652 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 653 654 #define CONFIG_NETDEV "eth1" 655 656 #define CONFIG_HOSTNAME mpc837x_rdb 657 #define CONFIG_ROOTPATH "/nfsroot" 658 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 659 #define CONFIG_BOOTFILE "uImage" 660 /* U-Boot image on TFTP server */ 661 #define CONFIG_UBOOTPATH "u-boot.bin" 662 #define CONFIG_FDTFILE "mpc8379_rdb.dtb" 663 664 /* default location for tftp and bootm */ 665 #define CONFIG_LOADADDR 800000 666 667 #define CONFIG_EXTRA_ENV_SETTINGS \ 668 "netdev=" CONFIG_NETDEV "\0" \ 669 "uboot=" CONFIG_UBOOTPATH "\0" \ 670 "tftpflash=tftp $loadaddr $uboot;" \ 671 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 672 " +$filesize; " \ 673 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 674 " +$filesize; " \ 675 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 676 " $filesize; " \ 677 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 678 " +$filesize; " \ 679 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 680 " $filesize\0" \ 681 "fdtaddr=780000\0" \ 682 "fdtfile=" CONFIG_FDTFILE "\0" \ 683 "ramdiskaddr=1000000\0" \ 684 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 685 "console=ttyS0\0" \ 686 "setbootargs=setenv bootargs " \ 687 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 688 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 689 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 690 "$netdev:off " \ 691 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 692 693 #define CONFIG_NFSBOOTCOMMAND \ 694 "setenv rootdev /dev/nfs;" \ 695 "run setbootargs;" \ 696 "run setipargs;" \ 697 "tftp $loadaddr $bootfile;" \ 698 "tftp $fdtaddr $fdtfile;" \ 699 "bootm $loadaddr - $fdtaddr" 700 701 #define CONFIG_RAMBOOTCOMMAND \ 702 "setenv rootdev /dev/ram;" \ 703 "run setbootargs;" \ 704 "tftp $ramdiskaddr $ramdiskfile;" \ 705 "tftp $loadaddr $bootfile;" \ 706 "tftp $fdtaddr $fdtfile;" \ 707 "bootm $loadaddr $ramdiskaddr $fdtaddr" 708 709 #endif /* __CONFIG_H */ 710