1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 17 #define CONFIG_MPC837XERDB 1 18 19 #define CONFIG_MISC_INIT_R 20 #define CONFIG_HWCONFIG 21 22 /* 23 * On-board devices 24 */ 25 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 26 #define CONFIG_VSC7385_ENET 27 28 /* 29 * System Clock Setup 30 */ 31 #ifdef CONFIG_PCISLAVE 32 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 33 #else 34 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 35 #define CONFIG_PCIE 36 #endif 37 38 #ifndef CONFIG_SYS_CLK_FREQ 39 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 40 #endif 41 42 /* 43 * Hardware Reset Configuration Word 44 */ 45 #define CONFIG_SYS_HRCW_LOW (\ 46 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 47 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 48 HRCWL_SVCOD_DIV_2 |\ 49 HRCWL_CSB_TO_CLKIN_5X1 |\ 50 HRCWL_CORE_TO_CSB_2X1) 51 52 #ifdef CONFIG_PCISLAVE 53 #define CONFIG_SYS_HRCW_HIGH (\ 54 HRCWH_PCI_AGENT |\ 55 HRCWH_PCI1_ARBITER_DISABLE |\ 56 HRCWH_CORE_ENABLE |\ 57 HRCWH_FROM_0XFFF00100 |\ 58 HRCWH_BOOTSEQ_DISABLE |\ 59 HRCWH_SW_WATCHDOG_DISABLE |\ 60 HRCWH_ROM_LOC_LOCAL_16BIT |\ 61 HRCWH_RL_EXT_LEGACY |\ 62 HRCWH_TSEC1M_IN_RGMII |\ 63 HRCWH_TSEC2M_IN_RGMII |\ 64 HRCWH_BIG_ENDIAN |\ 65 HRCWH_LDP_CLEAR) 66 #else 67 #define CONFIG_SYS_HRCW_HIGH (\ 68 HRCWH_PCI_HOST |\ 69 HRCWH_PCI1_ARBITER_ENABLE |\ 70 HRCWH_CORE_ENABLE |\ 71 HRCWH_FROM_0X00000100 |\ 72 HRCWH_BOOTSEQ_DISABLE |\ 73 HRCWH_SW_WATCHDOG_DISABLE |\ 74 HRCWH_ROM_LOC_LOCAL_16BIT |\ 75 HRCWH_RL_EXT_LEGACY |\ 76 HRCWH_TSEC1M_IN_RGMII |\ 77 HRCWH_TSEC2M_IN_RGMII |\ 78 HRCWH_BIG_ENDIAN |\ 79 HRCWH_LDP_CLEAR) 80 #endif 81 82 /* System performance - define the value i.e. CONFIG_SYS_XXX 83 */ 84 85 /* Arbiter Configuration Register */ 86 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 87 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 88 89 /* System Priority Control Regsiter */ 90 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 91 92 /* System Clock Configuration Register */ 93 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 94 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 95 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 96 97 /* 98 * System IO Config 99 */ 100 #define CONFIG_SYS_SICRH 0x08200000 101 #define CONFIG_SYS_SICRL 0x00000000 102 103 /* 104 * Output Buffer Impedance 105 */ 106 #define CONFIG_SYS_OBIR 0x30100000 107 108 /* 109 * IMMR new address 110 */ 111 #define CONFIG_SYS_IMMR 0xE0000000 112 113 /* 114 * Device configurations 115 */ 116 117 /* Vitesse 7385 */ 118 119 #ifdef CONFIG_VSC7385_ENET 120 121 #define CONFIG_TSEC2 122 123 /* The flash address and size of the VSC7385 firmware image */ 124 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 125 #define CONFIG_VSC7385_IMAGE_SIZE 8192 126 127 #endif 128 129 /* 130 * DDR Setup 131 */ 132 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 133 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 134 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 135 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 136 #define CONFIG_SYS_83XX_DDR_USES_CS0 137 138 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 139 140 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 141 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 142 143 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 144 145 /* 146 * Manually set up DDR parameters 147 */ 148 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 149 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 150 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 151 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 152 | CSCONFIG_ROW_BIT_13 \ 153 | CSCONFIG_COL_BIT_10) 154 155 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 156 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 157 | (0 << TIMING_CFG0_WRT_SHIFT) \ 158 | (0 << TIMING_CFG0_RRT_SHIFT) \ 159 | (0 << TIMING_CFG0_WWT_SHIFT) \ 160 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 161 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 162 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 163 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 164 /* 0x00260802 */ /* DDR400 */ 165 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 166 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 167 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 168 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 169 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 170 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 171 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 172 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 173 /* 0x3937d322 */ 174 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 175 | (5 << TIMING_CFG2_CPO_SHIFT) \ 176 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 177 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 178 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 179 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 180 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 181 /* 0x02984cc8 */ 182 183 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 184 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 185 /* 0x06090100 */ 186 187 #if defined(CONFIG_DDR_2T_TIMING) 188 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 189 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 190 | SDRAM_CFG_32_BE \ 191 | SDRAM_CFG_2T_EN) 192 /* 0x43088000 */ 193 #else 194 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 195 | SDRAM_CFG_SDRAM_TYPE_DDR2) 196 /* 0x43000000 */ 197 #endif 198 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 199 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 200 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 201 /* 0x04400442 */ /* DDR400 */ 202 #define CONFIG_SYS_DDR_MODE2 0x00000000 203 204 /* 205 * Memory test 206 */ 207 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 208 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 209 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 210 211 /* 212 * The reserved memory 213 */ 214 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 215 216 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 217 #define CONFIG_SYS_RAMBOOT 218 #else 219 #undef CONFIG_SYS_RAMBOOT 220 #endif 221 222 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 223 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 224 225 /* 226 * Initial RAM Base Address Setup 227 */ 228 #define CONFIG_SYS_INIT_RAM_LOCK 1 229 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 230 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 231 #define CONFIG_SYS_GBL_DATA_OFFSET \ 232 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 233 234 /* 235 * Local Bus Configuration & Clock Setup 236 */ 237 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 238 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 239 #define CONFIG_SYS_LBC_LBCR 0x00000000 240 #define CONFIG_FSL_ELBC 1 241 242 /* 243 * FLASH on the Local Bus 244 */ 245 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 246 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 247 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 248 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 249 250 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 251 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 252 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 253 254 /* Window base at flash base */ 255 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 256 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 257 258 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 259 | BR_PS_16 /* 16 bit port */ \ 260 | BR_MS_GPCM /* MSEL = GPCM */ \ 261 | BR_V) /* valid */ 262 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 263 | OR_GPCM_XACS \ 264 | OR_GPCM_SCY_9 \ 265 | OR_GPCM_EHTR_SET \ 266 | OR_GPCM_EAD) 267 /* 0xFF800191 */ 268 269 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 270 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 271 272 #undef CONFIG_SYS_FLASH_CHECKSUM 273 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 274 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 275 276 /* 277 * NAND Flash on the Local Bus 278 */ 279 #define CONFIG_SYS_NAND_BASE 0xE0600000 280 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 281 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 282 | BR_PS_8 /* 8 bit port */ \ 283 | BR_MS_FCM /* MSEL = FCM */ \ 284 | BR_V) /* valid */ 285 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 286 | OR_FCM_CSCT \ 287 | OR_FCM_CST \ 288 | OR_FCM_CHT \ 289 | OR_FCM_SCY_1 \ 290 | OR_FCM_TRLX \ 291 | OR_FCM_EHTR) 292 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 293 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 294 295 /* Vitesse 7385 */ 296 297 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 298 299 #ifdef CONFIG_VSC7385_ENET 300 301 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 302 | BR_PS_8 \ 303 | BR_MS_GPCM \ 304 | BR_V) 305 /* 0xF0000801 */ 306 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 307 | OR_GPCM_CSNT \ 308 | OR_GPCM_XACS \ 309 | OR_GPCM_SCY_15 \ 310 | OR_GPCM_SETA \ 311 | OR_GPCM_TRLX_SET \ 312 | OR_GPCM_EHTR_SET \ 313 | OR_GPCM_EAD) 314 /* 0xfffe09ff */ 315 316 /* Access Base */ 317 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 318 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 319 320 #endif 321 322 /* 323 * Serial Port 324 */ 325 #define CONFIG_SYS_NS16550_SERIAL 326 #define CONFIG_SYS_NS16550_REG_SIZE 1 327 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 328 329 #define CONFIG_SYS_BAUDRATE_TABLE \ 330 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 331 332 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 333 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 334 335 /* SERDES */ 336 #define CONFIG_FSL_SERDES 337 #define CONFIG_FSL_SERDES1 0xe3000 338 #define CONFIG_FSL_SERDES2 0xe3100 339 340 /* I2C */ 341 #define CONFIG_SYS_I2C 342 #define CONFIG_SYS_I2C_FSL 343 #define CONFIG_SYS_FSL_I2C_SPEED 400000 344 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 345 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 346 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 347 348 /* 349 * Config on-board RTC 350 */ 351 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 352 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 353 354 /* 355 * General PCI 356 * Addresses are mapped 1-1. 357 */ 358 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 359 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 360 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 361 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 362 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 363 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 364 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 365 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 366 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 367 368 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 369 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 370 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 371 372 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 373 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 374 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 375 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 376 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 377 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 378 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 379 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 380 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 381 382 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 383 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 384 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 385 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 386 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 387 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 388 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 389 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 390 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 391 392 #ifdef CONFIG_PCI 393 #define CONFIG_PCI_INDIRECT_BRIDGE 394 395 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 396 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 397 #endif /* CONFIG_PCI */ 398 399 /* 400 * TSEC 401 */ 402 #ifdef CONFIG_TSEC_ENET 403 404 #define CONFIG_GMII /* MII PHY management */ 405 406 #define CONFIG_TSEC1 407 408 #ifdef CONFIG_TSEC1 409 #define CONFIG_HAS_ETH0 410 #define CONFIG_TSEC1_NAME "TSEC0" 411 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 412 #define TSEC1_PHY_ADDR 2 413 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 414 #define TSEC1_PHYIDX 0 415 #endif 416 417 #ifdef CONFIG_TSEC2 418 #define CONFIG_HAS_ETH1 419 #define CONFIG_TSEC2_NAME "TSEC1" 420 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 421 #define TSEC2_PHY_ADDR 0x1c 422 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC2_PHYIDX 0 424 #endif 425 426 /* Options are: TSEC[0-1] */ 427 #define CONFIG_ETHPRIME "TSEC0" 428 429 #endif 430 431 /* 432 * SATA 433 */ 434 #define CONFIG_SYS_SATA_MAX_DEVICE 2 435 #define CONFIG_SATA1 436 #define CONFIG_SYS_SATA1_OFFSET 0x18000 437 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 438 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 439 #define CONFIG_SATA2 440 #define CONFIG_SYS_SATA2_OFFSET 0x19000 441 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 442 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 443 444 #ifdef CONFIG_FSL_SATA 445 #define CONFIG_LBA48 446 #endif 447 448 /* 449 * Environment 450 */ 451 #ifndef CONFIG_SYS_RAMBOOT 452 #define CONFIG_ENV_ADDR \ 453 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 454 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 455 #define CONFIG_ENV_SIZE 0x4000 456 #else 457 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 458 #define CONFIG_ENV_SIZE 0x2000 459 #endif 460 461 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 462 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 463 464 /* 465 * BOOTP options 466 */ 467 #define CONFIG_BOOTP_BOOTFILESIZE 468 469 /* 470 * Command line configuration. 471 */ 472 473 #undef CONFIG_WATCHDOG /* watchdog disabled */ 474 475 #ifdef CONFIG_MMC 476 #define CONFIG_FSL_ESDHC 477 #define CONFIG_FSL_ESDHC_PIN_MUX 478 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 479 #endif 480 481 /* 482 * Miscellaneous configurable options 483 */ 484 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 485 486 /* 487 * For booting Linux, the board info and command line data 488 * have to be in the first 256 MB of memory, since this is 489 * the maximum mapped by the Linux kernel during initialization. 490 */ 491 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 492 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 493 494 /* 495 * Core HID Setup 496 */ 497 #define CONFIG_SYS_HID0_INIT 0x000000000 498 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 499 | HID0_ENABLE_INSTRUCTION_CACHE) 500 #define CONFIG_SYS_HID2 HID2_HBE 501 502 /* 503 * MMU Setup 504 */ 505 506 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 507 508 /* DDR: cache cacheable */ 509 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 510 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 511 512 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 513 | BATL_PP_RW \ 514 | BATL_MEMCOHERENCE) 515 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 516 | BATU_BL_256M \ 517 | BATU_VS \ 518 | BATU_VP) 519 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 520 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 521 522 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 523 | BATL_PP_RW \ 524 | BATL_MEMCOHERENCE) 525 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 526 | BATU_BL_256M \ 527 | BATU_VS \ 528 | BATU_VP) 529 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 530 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 531 532 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 533 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 534 | BATL_PP_RW \ 535 | BATL_CACHEINHIBIT \ 536 | BATL_GUARDEDSTORAGE) 537 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 538 | BATU_BL_8M \ 539 | BATU_VS \ 540 | BATU_VP) 541 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 542 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 543 544 /* L2 Switch: cache-inhibit and guarded */ 545 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ 546 | BATL_PP_RW \ 547 | BATL_CACHEINHIBIT \ 548 | BATL_GUARDEDSTORAGE) 549 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ 550 | BATU_BL_128K \ 551 | BATU_VS \ 552 | BATU_VP) 553 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 554 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 555 556 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 557 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 558 | BATL_PP_RW \ 559 | BATL_MEMCOHERENCE) 560 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 561 | BATU_BL_32M \ 562 | BATU_VS \ 563 | BATU_VP) 564 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 565 | BATL_PP_RW \ 566 | BATL_CACHEINHIBIT \ 567 | BATL_GUARDEDSTORAGE) 568 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 569 570 /* Stack in dcache: cacheable, no memory coherence */ 571 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 572 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 573 | BATU_BL_128K \ 574 | BATU_VS \ 575 | BATU_VP) 576 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 577 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 578 579 #ifdef CONFIG_PCI 580 /* PCI MEM space: cacheable */ 581 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 582 | BATL_PP_RW \ 583 | BATL_MEMCOHERENCE) 584 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 585 | BATU_BL_256M \ 586 | BATU_VS \ 587 | BATU_VP) 588 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 589 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 590 /* PCI MMIO space: cache-inhibit and guarded */ 591 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 592 | BATL_PP_RW \ 593 | BATL_CACHEINHIBIT \ 594 | BATL_GUARDEDSTORAGE) 595 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 596 | BATU_BL_256M \ 597 | BATU_VS \ 598 | BATU_VP) 599 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 600 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 601 #else 602 #define CONFIG_SYS_IBAT6L (0) 603 #define CONFIG_SYS_IBAT6U (0) 604 #define CONFIG_SYS_IBAT7L (0) 605 #define CONFIG_SYS_IBAT7U (0) 606 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 607 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 608 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 609 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 610 #endif 611 612 #if defined(CONFIG_CMD_KGDB) 613 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 614 #endif 615 616 /* 617 * Environment Configuration 618 */ 619 #define CONFIG_ENV_OVERWRITE 620 621 #define CONFIG_HAS_FSL_DR_USB 622 #define CONFIG_USB_EHCI_FSL 623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 624 625 #define CONFIG_NETDEV "eth1" 626 627 #define CONFIG_HOSTNAME mpc837x_rdb 628 #define CONFIG_ROOTPATH "/nfsroot" 629 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 630 #define CONFIG_BOOTFILE "uImage" 631 /* U-Boot image on TFTP server */ 632 #define CONFIG_UBOOTPATH "u-boot.bin" 633 #define CONFIG_FDTFILE "mpc8379_rdb.dtb" 634 635 /* default location for tftp and bootm */ 636 #define CONFIG_LOADADDR 800000 637 638 #define CONFIG_EXTRA_ENV_SETTINGS \ 639 "netdev=" CONFIG_NETDEV "\0" \ 640 "uboot=" CONFIG_UBOOTPATH "\0" \ 641 "tftpflash=tftp $loadaddr $uboot;" \ 642 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 643 " +$filesize; " \ 644 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 645 " +$filesize; " \ 646 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 647 " $filesize; " \ 648 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 649 " +$filesize; " \ 650 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 651 " $filesize\0" \ 652 "fdtaddr=780000\0" \ 653 "fdtfile=" CONFIG_FDTFILE "\0" \ 654 "ramdiskaddr=1000000\0" \ 655 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 656 "console=ttyS0\0" \ 657 "setbootargs=setenv bootargs " \ 658 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 659 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 660 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 661 "$netdev:off " \ 662 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 663 664 #define CONFIG_NFSBOOTCOMMAND \ 665 "setenv rootdev /dev/nfs;" \ 666 "run setbootargs;" \ 667 "run setipargs;" \ 668 "tftp $loadaddr $bootfile;" \ 669 "tftp $fdtaddr $fdtfile;" \ 670 "bootm $loadaddr - $fdtaddr" 671 672 #define CONFIG_RAMBOOTCOMMAND \ 673 "setenv rootdev /dev/ram;" \ 674 "run setbootargs;" \ 675 "tftp $ramdiskaddr $ramdiskfile;" \ 676 "tftp $loadaddr $bootfile;" \ 677 "tftp $fdtaddr $fdtfile;" \ 678 "bootm $loadaddr $ramdiskaddr $fdtaddr" 679 680 #endif /* __CONFIG_H */ 681