1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21 
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24 
25 /*
26  * High Level Configuration Options
27  */
28 #define CONFIG_E300		1 /* E300 family */
29 #define CONFIG_MPC83xx		1 /* MPC83xx family */
30 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
31 #define CONFIG_MPC837XERDB	1
32 
33 #define CONFIG_PCI	1
34 
35 #define CONFIG_BOARD_EARLY_INIT_F
36 #define CONFIG_MISC_INIT_R
37 #define CONFIG_HWCONFIG
38 
39 /*
40  * On-board devices
41  */
42 #define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
43 #define CONFIG_VSC7385_ENET
44 
45 /*
46  * System Clock Setup
47  */
48 #ifdef CONFIG_PCISLAVE
49 #define CONFIG_83XX_PCICLK	66666667 /* in HZ */
50 #else
51 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
52 #define CONFIG_PCIE
53 #endif
54 
55 #ifndef CONFIG_SYS_CLK_FREQ
56 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
57 #endif
58 
59 /*
60  * Hardware Reset Configuration Word
61  */
62 #define CONFIG_SYS_HRCW_LOW (\
63 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
64 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
65 	HRCWL_SVCOD_DIV_2 |\
66 	HRCWL_CSB_TO_CLKIN_5X1 |\
67 	HRCWL_CORE_TO_CSB_2X1)
68 
69 #ifdef CONFIG_PCISLAVE
70 #define CONFIG_SYS_HRCW_HIGH (\
71 	HRCWH_PCI_AGENT |\
72 	HRCWH_PCI1_ARBITER_DISABLE |\
73 	HRCWH_CORE_ENABLE |\
74 	HRCWH_FROM_0XFFF00100 |\
75 	HRCWH_BOOTSEQ_DISABLE |\
76 	HRCWH_SW_WATCHDOG_DISABLE |\
77 	HRCWH_ROM_LOC_LOCAL_16BIT |\
78 	HRCWH_RL_EXT_LEGACY |\
79 	HRCWH_TSEC1M_IN_RGMII |\
80 	HRCWH_TSEC2M_IN_RGMII |\
81 	HRCWH_BIG_ENDIAN |\
82 	HRCWH_LDP_CLEAR)
83 #else
84 #define CONFIG_SYS_HRCW_HIGH (\
85 	HRCWH_PCI_HOST |\
86 	HRCWH_PCI1_ARBITER_ENABLE |\
87 	HRCWH_CORE_ENABLE |\
88 	HRCWH_FROM_0X00000100 |\
89 	HRCWH_BOOTSEQ_DISABLE |\
90 	HRCWH_SW_WATCHDOG_DISABLE |\
91 	HRCWH_ROM_LOC_LOCAL_16BIT |\
92 	HRCWH_RL_EXT_LEGACY |\
93 	HRCWH_TSEC1M_IN_RGMII |\
94 	HRCWH_TSEC2M_IN_RGMII |\
95 	HRCWH_BIG_ENDIAN |\
96 	HRCWH_LDP_CLEAR)
97 #endif
98 
99 /* System performance - define the value i.e. CONFIG_SYS_XXX
100 */
101 
102 /* Arbiter Configuration Register */
103 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
104 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
105 
106 /* System Priority Control Regsiter */
107 #define CONFIG_SYS_SPCR_TSECEP		3	/* eTSEC1&2 emergency priority (0-3) */
108 
109 /* System Clock Configuration Register */
110 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
111 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
112 #define CONFIG_SYS_SCCR_SATACM		SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
113 
114 /*
115  * System IO Config
116  */
117 #define CONFIG_SYS_SICRH		0x08200000
118 #define CONFIG_SYS_SICRL		0x00000000
119 
120 /*
121  * Output Buffer Impedance
122  */
123 #define CONFIG_SYS_OBIR		0x30100000
124 
125 /*
126  * IMMR new address
127  */
128 #define CONFIG_SYS_IMMR		0xE0000000
129 
130 /*
131  * Device configurations
132  */
133 
134 /* Vitesse 7385 */
135 
136 #ifdef CONFIG_VSC7385_ENET
137 
138 #define CONFIG_TSEC2
139 
140 /* The flash address and size of the VSC7385 firmware image */
141 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
142 #define CONFIG_VSC7385_IMAGE_SIZE	8192
143 
144 #endif
145 
146 /*
147  * DDR Setup
148  */
149 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
150 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
151 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
152 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
153 #define CONFIG_SYS_83XX_DDR_USES_CS0
154 
155 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
156 
157 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
158 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
159 
160 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
161 
162 /*
163  * Manually set up DDR parameters
164  */
165 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
166 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
167 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
168 				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
169 
170 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
171 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
172 				| (0 << TIMING_CFG0_WRT_SHIFT) \
173 				| (0 << TIMING_CFG0_RRT_SHIFT) \
174 				| (0 << TIMING_CFG0_WWT_SHIFT) \
175 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
176 				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
177 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
178 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
179 				/* 0x00220802 */
180 				/* 0x00260802 */ /* DDR400 */
181 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
182 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
183 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
184 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
185 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
186 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
187 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
188 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
189 				/* 0x3935d322 */
190 				/* 0x3937d322 */
191 #define CONFIG_SYS_DDR_TIMING_2	0x02984cc8
192 
193 #define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
194 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
195 				/* 0x06090100 */
196 
197 #if defined(CONFIG_DDR_2T_TIMING)
198 #define CONFIG_SYS_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
199 				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
200 				| SDRAM_CFG_2T_EN \
201 				| SDRAM_CFG_DBW_32)
202 #else
203 #define CONFIG_SYS_DDR_SDRAM_CFG		(SDRAM_CFG_SREN \
204 				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
205 				/* 0x43000000 */
206 #endif
207 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
208 #define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
209 				| (0x0442 << SDRAM_MODE_SD_SHIFT))
210 				/* 0x04400442 */ /* DDR400 */
211 #define CONFIG_SYS_DDR_MODE2		0x00000000
212 
213 /*
214  * Memory test
215  */
216 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
217 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
218 #define CONFIG_SYS_MEMTEST_END		0x0ef70010
219 
220 /*
221  * The reserved memory
222  */
223 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
224 
225 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_RAMBOOT
227 #else
228 #undef	CONFIG_SYS_RAMBOOT
229 #endif
230 
231 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
232 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
233 
234 /*
235  * Initial RAM Base Address Setup
236  */
237 #define CONFIG_SYS_INIT_RAM_LOCK	1
238 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
239 #define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
240 #define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
241 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
242 
243 /*
244  * Local Bus Configuration & Clock Setup
245  */
246 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
247 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
248 #define CONFIG_SYS_LBC_LBCR		0x00000000
249 
250 /*
251  * FLASH on the Local Bus
252  */
253 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
254 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
255 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
256 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
257 
258 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
259 #define CONFIG_SYS_FLASH_EMPTY_INFO			/* display empty sectors */
260 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */
261 
262 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
263 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
264 
265 #define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
266 				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
267 				BR_V) /* valid */
268 #define CONFIG_SYS_OR0_PRELIM		(0xFF800000		/* 8 MByte */ \
269 				| OR_GPCM_XACS \
270 				| OR_GPCM_SCY_9 \
271 				| OR_GPCM_EHTR \
272 				| OR_GPCM_EAD)
273 				/* 0xFF806FF7	TODO SLOW 8 MB flash size */
274 
275 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
276 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
277 
278 #undef	CONFIG_SYS_FLASH_CHECKSUM
279 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
280 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
281 
282 /*
283  * NAND Flash on the Local Bus
284  */
285 #define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
286 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_NAND_BASE | \
287 				 (2 << BR_DECC_SHIFT) |	/* Use HW ECC */ \
288 				 BR_PS_8 |		/* Port Size = 8 bit */ \
289 				 BR_MS_FCM |		/* MSEL = FCM */ \
290 				 BR_V)			/* valid */
291 #define CONFIG_SYS_OR1_PRELIM		(0xFFFF8000 |		/* length 32K */ \
292 				 OR_FCM_CSCT | \
293 				 OR_FCM_CST | \
294 				 OR_FCM_CHT | \
295 				 OR_FCM_SCY_1 | \
296 				 OR_FCM_TRLX | \
297 				 OR_FCM_EHTR)
298 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
299 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
300 
301 /* Vitesse 7385 */
302 
303 #define CONFIG_SYS_VSC7385_BASE	0xF0000000
304 
305 #ifdef CONFIG_VSC7385_ENET
306 
307 #define CONFIG_SYS_BR2_PRELIM		0xf0000801		/* Base address */
308 #define CONFIG_SYS_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
309 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE	/* Access Base */
310 #define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
311 
312 #endif
313 
314 /*
315  * Serial Port
316  */
317 #define CONFIG_CONS_INDEX	1
318 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
319 #define CONFIG_SYS_NS16550
320 #define CONFIG_SYS_NS16550_SERIAL
321 #define CONFIG_SYS_NS16550_REG_SIZE	1
322 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
323 
324 #define CONFIG_SYS_BAUDRATE_TABLE \
325 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
326 
327 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
328 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
329 
330 /* SERDES */
331 #define CONFIG_FSL_SERDES
332 #define CONFIG_FSL_SERDES1	0xe3000
333 #define CONFIG_FSL_SERDES2	0xe3100
334 
335 /* Use the HUSH parser */
336 #define CONFIG_SYS_HUSH_PARSER
337 #ifdef	CONFIG_SYS_HUSH_PARSER
338 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
339 #endif
340 
341 /* Pass open firmware flat tree */
342 #define CONFIG_OF_LIBFDT	1
343 #define CONFIG_OF_BOARD_SETUP	1
344 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
345 
346 /* I2C */
347 #define CONFIG_HARD_I2C		/* I2C with hardware support */
348 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
349 #define CONFIG_FSL_I2C
350 #define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
351 #define CONFIG_SYS_I2C_SLAVE		0x7F
352 #define CONFIG_SYS_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
353 #define CONFIG_SYS_I2C_OFFSET		0x3000
354 #define CONFIG_SYS_I2C2_OFFSET		0x3100
355 
356 /*
357  * Config on-board RTC
358  */
359 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
360 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
361 
362 /*
363  * General PCI
364  * Addresses are mapped 1-1.
365  */
366 #define CONFIG_SYS_PCI_MEM_BASE	0x80000000
367 #define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
368 #define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
369 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
370 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
371 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
372 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
373 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
374 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
375 
376 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
377 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
378 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
379 
380 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
381 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
382 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
383 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
384 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
385 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
386 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
387 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
388 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
389 
390 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
391 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
392 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
393 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
394 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
395 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
396 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
397 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
398 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
399 
400 #ifdef CONFIG_PCI
401 #define CONFIG_NET_MULTI
402 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
403 
404 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
405 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
406 #endif	/* CONFIG_PCI */
407 
408 /*
409  * TSEC
410  */
411 #ifdef CONFIG_TSEC_ENET
412 
413 #define CONFIG_NET_MULTI
414 #define CONFIG_GMII			/* MII PHY management */
415 
416 #define CONFIG_TSEC1
417 
418 #ifdef CONFIG_TSEC1
419 #define CONFIG_HAS_ETH0
420 #define CONFIG_TSEC1_NAME		"TSEC0"
421 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
422 #define TSEC1_PHY_ADDR			2
423 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
424 #define TSEC1_PHYIDX			0
425 #endif
426 
427 #ifdef CONFIG_TSEC2
428 #define CONFIG_HAS_ETH1
429 #define CONFIG_TSEC2_NAME		"TSEC1"
430 #define CONFIG_SYS_TSEC2_OFFSET		0x25000
431 #define TSEC2_PHY_ADDR			0x1c
432 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
433 #define TSEC2_PHYIDX			0
434 #endif
435 
436 /* Options are: TSEC[0-1] */
437 #define CONFIG_ETHPRIME			"TSEC0"
438 
439 #endif
440 
441 /*
442  * SATA
443  */
444 #define CONFIG_LIBATA
445 #define CONFIG_FSL_SATA
446 
447 #define CONFIG_SYS_SATA_MAX_DEVICE	2
448 #define CONFIG_SATA1
449 #define CONFIG_SYS_SATA1_OFFSET	0x18000
450 #define CONFIG_SYS_SATA1		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
451 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
452 #define CONFIG_SATA2
453 #define CONFIG_SYS_SATA2_OFFSET	0x19000
454 #define CONFIG_SYS_SATA2		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
455 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
456 
457 #ifdef CONFIG_FSL_SATA
458 #define CONFIG_LBA48
459 #define CONFIG_CMD_SATA
460 #define CONFIG_DOS_PARTITION
461 #define CONFIG_CMD_EXT2
462 #endif
463 
464 /*
465  * Environment
466  */
467 #ifndef CONFIG_SYS_RAMBOOT
468 	#define CONFIG_ENV_IS_IN_FLASH	1
469 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
470 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
471 	#define CONFIG_ENV_SIZE		0x4000
472 #else
473 	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
474 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
475 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
476 	#define CONFIG_ENV_SIZE		0x2000
477 #endif
478 
479 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
480 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
481 
482 /*
483  * BOOTP options
484  */
485 #define CONFIG_BOOTP_BOOTFILESIZE
486 #define CONFIG_BOOTP_BOOTPATH
487 #define CONFIG_BOOTP_GATEWAY
488 #define CONFIG_BOOTP_HOSTNAME
489 
490 
491 /*
492  * Command line configuration.
493  */
494 #include <config_cmd_default.h>
495 
496 #define CONFIG_CMD_PING
497 #define CONFIG_CMD_I2C
498 #define CONFIG_CMD_MII
499 #define CONFIG_CMD_DATE
500 
501 #if defined(CONFIG_PCI)
502 #define CONFIG_CMD_PCI
503 #endif
504 
505 #if defined(CONFIG_SYS_RAMBOOT)
506 #undef CONFIG_CMD_SAVEENV
507 #undef CONFIG_CMD_LOADS
508 #endif
509 
510 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
511 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
512 
513 #undef CONFIG_WATCHDOG		/* watchdog disabled */
514 
515 #define CONFIG_MMC     1
516 
517 #ifdef CONFIG_MMC
518 #define CONFIG_FSL_ESDHC
519 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
520 #define CONFIG_CMD_MMC
521 #define CONFIG_GENERIC_MMC
522 #define CONFIG_CMD_EXT2
523 #define CONFIG_CMD_FAT
524 #define CONFIG_DOS_PARTITION
525 #endif
526 
527 /*
528  * Miscellaneous configurable options
529  */
530 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
531 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
532 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
533 
534 #if defined(CONFIG_CMD_KGDB)
535 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
536 #else
537 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
538 #endif
539 
540 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
541 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
542 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
543 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
544 
545 /*
546  * For booting Linux, the board info and command line data
547  * have to be in the first 8 MB of memory, since this is
548  * the maximum mapped by the Linux kernel during initialization.
549  */
550 #define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
551 
552 /*
553  * Core HID Setup
554  */
555 #define CONFIG_SYS_HID0_INIT	0x000000000
556 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
557 				 HID0_ENABLE_INSTRUCTION_CACHE)
558 #define CONFIG_SYS_HID2		HID2_HBE
559 
560 /*
561  * MMU Setup
562  */
563 
564 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
565 
566 /* DDR: cache cacheable */
567 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
568 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
569 
570 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
571 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
572 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
573 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
574 
575 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
576 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
577 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
578 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
579 
580 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
581 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
582 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
583 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
584 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
585 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
586 
587 /* L2 Switch: cache-inhibit and guarded */
588 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
589 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
590 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
591 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
592 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
593 
594 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
595 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
596 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
597 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
598 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
599 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
600 
601 /* Stack in dcache: cacheable, no memory coherence */
602 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
603 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
604 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
605 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
606 
607 #ifdef CONFIG_PCI
608 /* PCI MEM space: cacheable */
609 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
610 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
611 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
612 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
613 /* PCI MMIO space: cache-inhibit and guarded */
614 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
615 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
616 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
617 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
618 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
619 #else
620 #define CONFIG_SYS_IBAT6L	(0)
621 #define CONFIG_SYS_IBAT6U	(0)
622 #define CONFIG_SYS_IBAT7L	(0)
623 #define CONFIG_SYS_IBAT7U	(0)
624 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
625 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
626 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
627 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
628 #endif
629 
630 /*
631  * Internal Definitions
632  *
633  * Boot Flags
634  */
635 #define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
636 #define BOOTFLAG_WARM	0x02 /* Software reboot */
637 
638 #if defined(CONFIG_CMD_KGDB)
639 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
640 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
641 #endif
642 
643 /*
644  * Environment Configuration
645  */
646 #define CONFIG_ENV_OVERWRITE
647 
648 #define CONFIG_HAS_FSL_DR_USB
649 
650 #define CONFIG_NETDEV		eth1
651 
652 #define CONFIG_HOSTNAME		mpc837x_rdb
653 #define CONFIG_ROOTPATH		/nfsroot
654 #define CONFIG_RAMDISKFILE	rootfs.ext2.gz.uboot
655 #define CONFIG_BOOTFILE		uImage
656 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
657 #define CONFIG_FDTFILE		mpc8379_rdb.dtb
658 
659 #define CONFIG_LOADADDR		800000	/* default location for tftp and bootm */
660 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
661 #define CONFIG_BAUDRATE		115200
662 
663 #define XMK_STR(x)	#x
664 #define MK_STR(x)	XMK_STR(x)
665 
666 #define CONFIG_EXTRA_ENV_SETTINGS \
667 	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
668 	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
669 	"tftpflash=tftp $loadaddr $uboot;"				\
670 		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
671 		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
672 		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
673 		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
674 		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
675 	"fdtaddr=780000\0"						\
676 	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
677 	"ramdiskaddr=1000000\0"						\
678 	"ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0"			\
679 	"console=ttyS0\0"						\
680 	"setbootargs=setenv bootargs "					\
681 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
682 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
683 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
684 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
685 
686 #define CONFIG_NFSBOOTCOMMAND						\
687 	"setenv rootdev /dev/nfs;"					\
688 	"run setbootargs;"						\
689 	"run setipargs;"						\
690 	"tftp $loadaddr $bootfile;"					\
691 	"tftp $fdtaddr $fdtfile;"					\
692 	"bootm $loadaddr - $fdtaddr"
693 
694 #define CONFIG_RAMBOOTCOMMAND						\
695 	"setenv rootdev /dev/ram;"					\
696 	"run setbootargs;"						\
697 	"tftp $ramdiskaddr $ramdiskfile;"				\
698 	"tftp $loadaddr $bootfile;"					\
699 	"tftp $fdtaddr $fdtfile;"					\
700 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
701 
702 #undef MK_STR
703 #undef XMK_STR
704 
705 #endif	/* __CONFIG_H */
706