1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 17 #define CONFIG_MPC837XERDB 1 18 19 #define CONFIG_SYS_TEXT_BASE 0xFE000000 20 21 #define CONFIG_BOARD_EARLY_INIT_F 22 #define CONFIG_MISC_INIT_R 23 #define CONFIG_HWCONFIG 24 25 /* 26 * On-board devices 27 */ 28 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 29 #define CONFIG_VSC7385_ENET 30 31 /* 32 * System Clock Setup 33 */ 34 #ifdef CONFIG_PCISLAVE 35 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 36 #else 37 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 38 #define CONFIG_PCIE 39 #endif 40 41 #ifndef CONFIG_SYS_CLK_FREQ 42 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 43 #endif 44 45 /* 46 * Hardware Reset Configuration Word 47 */ 48 #define CONFIG_SYS_HRCW_LOW (\ 49 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 50 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 51 HRCWL_SVCOD_DIV_2 |\ 52 HRCWL_CSB_TO_CLKIN_5X1 |\ 53 HRCWL_CORE_TO_CSB_2X1) 54 55 #ifdef CONFIG_PCISLAVE 56 #define CONFIG_SYS_HRCW_HIGH (\ 57 HRCWH_PCI_AGENT |\ 58 HRCWH_PCI1_ARBITER_DISABLE |\ 59 HRCWH_CORE_ENABLE |\ 60 HRCWH_FROM_0XFFF00100 |\ 61 HRCWH_BOOTSEQ_DISABLE |\ 62 HRCWH_SW_WATCHDOG_DISABLE |\ 63 HRCWH_ROM_LOC_LOCAL_16BIT |\ 64 HRCWH_RL_EXT_LEGACY |\ 65 HRCWH_TSEC1M_IN_RGMII |\ 66 HRCWH_TSEC2M_IN_RGMII |\ 67 HRCWH_BIG_ENDIAN |\ 68 HRCWH_LDP_CLEAR) 69 #else 70 #define CONFIG_SYS_HRCW_HIGH (\ 71 HRCWH_PCI_HOST |\ 72 HRCWH_PCI1_ARBITER_ENABLE |\ 73 HRCWH_CORE_ENABLE |\ 74 HRCWH_FROM_0X00000100 |\ 75 HRCWH_BOOTSEQ_DISABLE |\ 76 HRCWH_SW_WATCHDOG_DISABLE |\ 77 HRCWH_ROM_LOC_LOCAL_16BIT |\ 78 HRCWH_RL_EXT_LEGACY |\ 79 HRCWH_TSEC1M_IN_RGMII |\ 80 HRCWH_TSEC2M_IN_RGMII |\ 81 HRCWH_BIG_ENDIAN |\ 82 HRCWH_LDP_CLEAR) 83 #endif 84 85 /* System performance - define the value i.e. CONFIG_SYS_XXX 86 */ 87 88 /* Arbiter Configuration Register */ 89 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 90 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 91 92 /* System Priority Control Regsiter */ 93 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 94 95 /* System Clock Configuration Register */ 96 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 97 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 98 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 99 100 /* 101 * System IO Config 102 */ 103 #define CONFIG_SYS_SICRH 0x08200000 104 #define CONFIG_SYS_SICRL 0x00000000 105 106 /* 107 * Output Buffer Impedance 108 */ 109 #define CONFIG_SYS_OBIR 0x30100000 110 111 /* 112 * IMMR new address 113 */ 114 #define CONFIG_SYS_IMMR 0xE0000000 115 116 /* 117 * Device configurations 118 */ 119 120 /* Vitesse 7385 */ 121 122 #ifdef CONFIG_VSC7385_ENET 123 124 #define CONFIG_TSEC2 125 126 /* The flash address and size of the VSC7385 firmware image */ 127 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 128 #define CONFIG_VSC7385_IMAGE_SIZE 8192 129 130 #endif 131 132 /* 133 * DDR Setup 134 */ 135 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 136 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 137 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 138 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 139 #define CONFIG_SYS_83XX_DDR_USES_CS0 140 141 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 142 143 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 144 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 145 146 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 147 148 /* 149 * Manually set up DDR parameters 150 */ 151 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 152 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 153 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 154 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 155 | CSCONFIG_ROW_BIT_13 \ 156 | CSCONFIG_COL_BIT_10) 157 158 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 159 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 160 | (0 << TIMING_CFG0_WRT_SHIFT) \ 161 | (0 << TIMING_CFG0_RRT_SHIFT) \ 162 | (0 << TIMING_CFG0_WWT_SHIFT) \ 163 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 164 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 165 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 166 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 167 /* 0x00260802 */ /* DDR400 */ 168 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 169 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 170 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 171 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 172 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 173 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 174 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 175 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 176 /* 0x3937d322 */ 177 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 178 | (5 << TIMING_CFG2_CPO_SHIFT) \ 179 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 180 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 181 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 182 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 183 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 184 /* 0x02984cc8 */ 185 186 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ 187 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 188 /* 0x06090100 */ 189 190 #if defined(CONFIG_DDR_2T_TIMING) 191 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 192 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 193 | SDRAM_CFG_32_BE \ 194 | SDRAM_CFG_2T_EN) 195 /* 0x43088000 */ 196 #else 197 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 198 | SDRAM_CFG_SDRAM_TYPE_DDR2) 199 /* 0x43000000 */ 200 #endif 201 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 202 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ 203 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 204 /* 0x04400442 */ /* DDR400 */ 205 #define CONFIG_SYS_DDR_MODE2 0x00000000 206 207 /* 208 * Memory test 209 */ 210 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 211 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 212 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 213 214 /* 215 * The reserved memory 216 */ 217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 218 219 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 220 #define CONFIG_SYS_RAMBOOT 221 #else 222 #undef CONFIG_SYS_RAMBOOT 223 #endif 224 225 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 226 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 227 228 /* 229 * Initial RAM Base Address Setup 230 */ 231 #define CONFIG_SYS_INIT_RAM_LOCK 1 232 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 233 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 234 #define CONFIG_SYS_GBL_DATA_OFFSET \ 235 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 236 237 /* 238 * Local Bus Configuration & Clock Setup 239 */ 240 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 241 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 242 #define CONFIG_SYS_LBC_LBCR 0x00000000 243 #define CONFIG_FSL_ELBC 1 244 245 /* 246 * FLASH on the Local Bus 247 */ 248 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 249 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 250 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 251 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 252 253 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 254 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 255 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 256 257 /* Window base at flash base */ 258 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 259 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 260 261 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 262 | BR_PS_16 /* 16 bit port */ \ 263 | BR_MS_GPCM /* MSEL = GPCM */ \ 264 | BR_V) /* valid */ 265 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 266 | OR_GPCM_XACS \ 267 | OR_GPCM_SCY_9 \ 268 | OR_GPCM_EHTR_SET \ 269 | OR_GPCM_EAD) 270 /* 0xFF800191 */ 271 272 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 273 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 274 275 #undef CONFIG_SYS_FLASH_CHECKSUM 276 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 277 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 278 279 /* 280 * NAND Flash on the Local Bus 281 */ 282 #define CONFIG_SYS_NAND_BASE 0xE0600000 283 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ 284 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 285 | BR_PS_8 /* 8 bit port */ \ 286 | BR_MS_FCM /* MSEL = FCM */ \ 287 | BR_V) /* valid */ 288 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 289 | OR_FCM_CSCT \ 290 | OR_FCM_CST \ 291 | OR_FCM_CHT \ 292 | OR_FCM_SCY_1 \ 293 | OR_FCM_TRLX \ 294 | OR_FCM_EHTR) 295 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 296 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 297 298 /* Vitesse 7385 */ 299 300 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 301 302 #ifdef CONFIG_VSC7385_ENET 303 304 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ 305 | BR_PS_8 \ 306 | BR_MS_GPCM \ 307 | BR_V) 308 /* 0xF0000801 */ 309 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 310 | OR_GPCM_CSNT \ 311 | OR_GPCM_XACS \ 312 | OR_GPCM_SCY_15 \ 313 | OR_GPCM_SETA \ 314 | OR_GPCM_TRLX_SET \ 315 | OR_GPCM_EHTR_SET \ 316 | OR_GPCM_EAD) 317 /* 0xfffe09ff */ 318 319 /* Access Base */ 320 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE 321 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 322 323 #endif 324 325 /* 326 * Serial Port 327 */ 328 #define CONFIG_CONS_INDEX 1 329 #define CONFIG_SYS_NS16550_SERIAL 330 #define CONFIG_SYS_NS16550_REG_SIZE 1 331 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 332 333 #define CONFIG_SYS_BAUDRATE_TABLE \ 334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 335 336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 338 339 /* SERDES */ 340 #define CONFIG_FSL_SERDES 341 #define CONFIG_FSL_SERDES1 0xe3000 342 #define CONFIG_FSL_SERDES2 0xe3100 343 344 /* I2C */ 345 #define CONFIG_SYS_I2C 346 #define CONFIG_SYS_I2C_FSL 347 #define CONFIG_SYS_FSL_I2C_SPEED 400000 348 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 349 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 350 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 351 352 /* 353 * Config on-board RTC 354 */ 355 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 356 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 357 358 /* 359 * General PCI 360 * Addresses are mapped 1-1. 361 */ 362 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 363 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 364 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 365 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 366 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 367 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 368 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 369 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 370 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 371 372 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 373 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 374 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 375 376 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 377 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 378 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 379 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 380 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 381 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 382 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 383 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 384 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 385 386 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 387 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 388 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 389 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 390 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 391 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 392 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 393 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 394 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 395 396 #ifdef CONFIG_PCI 397 #define CONFIG_PCI_INDIRECT_BRIDGE 398 399 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 400 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 401 #endif /* CONFIG_PCI */ 402 403 /* 404 * TSEC 405 */ 406 #ifdef CONFIG_TSEC_ENET 407 408 #define CONFIG_GMII /* MII PHY management */ 409 410 #define CONFIG_TSEC1 411 412 #ifdef CONFIG_TSEC1 413 #define CONFIG_HAS_ETH0 414 #define CONFIG_TSEC1_NAME "TSEC0" 415 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 416 #define TSEC1_PHY_ADDR 2 417 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 #define TSEC1_PHYIDX 0 419 #endif 420 421 #ifdef CONFIG_TSEC2 422 #define CONFIG_HAS_ETH1 423 #define CONFIG_TSEC2_NAME "TSEC1" 424 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 425 #define TSEC2_PHY_ADDR 0x1c 426 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 #define TSEC2_PHYIDX 0 428 #endif 429 430 /* Options are: TSEC[0-1] */ 431 #define CONFIG_ETHPRIME "TSEC0" 432 433 #endif 434 435 /* 436 * SATA 437 */ 438 #define CONFIG_LIBATA 439 #define CONFIG_FSL_SATA 440 441 #define CONFIG_SYS_SATA_MAX_DEVICE 2 442 #define CONFIG_SATA1 443 #define CONFIG_SYS_SATA1_OFFSET 0x18000 444 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 445 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 446 #define CONFIG_SATA2 447 #define CONFIG_SYS_SATA2_OFFSET 0x19000 448 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 449 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 450 451 #ifdef CONFIG_FSL_SATA 452 #define CONFIG_LBA48 453 #define CONFIG_CMD_SATA 454 #define CONFIG_DOS_PARTITION 455 #endif 456 457 /* 458 * Environment 459 */ 460 #ifndef CONFIG_SYS_RAMBOOT 461 #define CONFIG_ENV_IS_IN_FLASH 1 462 #define CONFIG_ENV_ADDR \ 463 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 464 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 465 #define CONFIG_ENV_SIZE 0x4000 466 #else 467 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 468 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 469 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 470 #define CONFIG_ENV_SIZE 0x2000 471 #endif 472 473 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 474 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 475 476 /* 477 * BOOTP options 478 */ 479 #define CONFIG_BOOTP_BOOTFILESIZE 480 #define CONFIG_BOOTP_BOOTPATH 481 #define CONFIG_BOOTP_GATEWAY 482 #define CONFIG_BOOTP_HOSTNAME 483 484 /* 485 * Command line configuration. 486 */ 487 #define CONFIG_CMD_DATE 488 489 #if defined(CONFIG_PCI) 490 #define CONFIG_CMD_PCI 491 #endif 492 493 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 494 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 495 496 #undef CONFIG_WATCHDOG /* watchdog disabled */ 497 498 #ifdef CONFIG_MMC 499 #define CONFIG_FSL_ESDHC 500 #define CONFIG_FSL_ESDHC_PIN_MUX 501 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 502 #define CONFIG_GENERIC_MMC 503 #define CONFIG_DOS_PARTITION 504 #endif 505 506 /* 507 * Miscellaneous configurable options 508 */ 509 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 510 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 511 512 #if defined(CONFIG_CMD_KGDB) 513 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 514 #else 515 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 516 #endif 517 518 /* Print Buffer Size */ 519 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 520 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 521 /* Boot Argument Buffer Size */ 522 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 523 524 /* 525 * For booting Linux, the board info and command line data 526 * have to be in the first 256 MB of memory, since this is 527 * the maximum mapped by the Linux kernel during initialization. 528 */ 529 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 530 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 531 532 /* 533 * Core HID Setup 534 */ 535 #define CONFIG_SYS_HID0_INIT 0x000000000 536 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ 537 | HID0_ENABLE_INSTRUCTION_CACHE) 538 #define CONFIG_SYS_HID2 HID2_HBE 539 540 /* 541 * MMU Setup 542 */ 543 544 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 545 546 /* DDR: cache cacheable */ 547 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 548 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 549 550 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 551 | BATL_PP_RW \ 552 | BATL_MEMCOHERENCE) 553 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 554 | BATU_BL_256M \ 555 | BATU_VS \ 556 | BATU_VP) 557 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 558 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 559 560 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 561 | BATL_PP_RW \ 562 | BATL_MEMCOHERENCE) 563 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 564 | BATU_BL_256M \ 565 | BATU_VS \ 566 | BATU_VP) 567 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 568 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 569 570 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 571 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 572 | BATL_PP_RW \ 573 | BATL_CACHEINHIBIT \ 574 | BATL_GUARDEDSTORAGE) 575 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 576 | BATU_BL_8M \ 577 | BATU_VS \ 578 | BATU_VP) 579 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 580 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 581 582 /* L2 Switch: cache-inhibit and guarded */ 583 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ 584 | BATL_PP_RW \ 585 | BATL_CACHEINHIBIT \ 586 | BATL_GUARDEDSTORAGE) 587 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ 588 | BATU_BL_128K \ 589 | BATU_VS \ 590 | BATU_VP) 591 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 592 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 593 594 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 595 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 596 | BATL_PP_RW \ 597 | BATL_MEMCOHERENCE) 598 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 599 | BATU_BL_32M \ 600 | BATU_VS \ 601 | BATU_VP) 602 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 603 | BATL_PP_RW \ 604 | BATL_CACHEINHIBIT \ 605 | BATL_GUARDEDSTORAGE) 606 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 607 608 /* Stack in dcache: cacheable, no memory coherence */ 609 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 610 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 611 | BATU_BL_128K \ 612 | BATU_VS \ 613 | BATU_VP) 614 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 615 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 616 617 #ifdef CONFIG_PCI 618 /* PCI MEM space: cacheable */ 619 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 620 | BATL_PP_RW \ 621 | BATL_MEMCOHERENCE) 622 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 623 | BATU_BL_256M \ 624 | BATU_VS \ 625 | BATU_VP) 626 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 627 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 628 /* PCI MMIO space: cache-inhibit and guarded */ 629 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 630 | BATL_PP_RW \ 631 | BATL_CACHEINHIBIT \ 632 | BATL_GUARDEDSTORAGE) 633 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 634 | BATU_BL_256M \ 635 | BATU_VS \ 636 | BATU_VP) 637 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 638 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 639 #else 640 #define CONFIG_SYS_IBAT6L (0) 641 #define CONFIG_SYS_IBAT6U (0) 642 #define CONFIG_SYS_IBAT7L (0) 643 #define CONFIG_SYS_IBAT7U (0) 644 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 645 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 646 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 647 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 648 #endif 649 650 #if defined(CONFIG_CMD_KGDB) 651 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 652 #endif 653 654 /* 655 * Environment Configuration 656 */ 657 #define CONFIG_ENV_OVERWRITE 658 659 #define CONFIG_HAS_FSL_DR_USB 660 #define CONFIG_USB_EHCI 661 #define CONFIG_USB_EHCI_FSL 662 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 663 664 #define CONFIG_NETDEV "eth1" 665 666 #define CONFIG_HOSTNAME mpc837x_rdb 667 #define CONFIG_ROOTPATH "/nfsroot" 668 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" 669 #define CONFIG_BOOTFILE "uImage" 670 /* U-Boot image on TFTP server */ 671 #define CONFIG_UBOOTPATH "u-boot.bin" 672 #define CONFIG_FDTFILE "mpc8379_rdb.dtb" 673 674 /* default location for tftp and bootm */ 675 #define CONFIG_LOADADDR 800000 676 #define CONFIG_BAUDRATE 115200 677 678 #define CONFIG_EXTRA_ENV_SETTINGS \ 679 "netdev=" CONFIG_NETDEV "\0" \ 680 "uboot=" CONFIG_UBOOTPATH "\0" \ 681 "tftpflash=tftp $loadaddr $uboot;" \ 682 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 683 " +$filesize; " \ 684 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 685 " +$filesize; " \ 686 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 687 " $filesize; " \ 688 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 689 " +$filesize; " \ 690 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 691 " $filesize\0" \ 692 "fdtaddr=780000\0" \ 693 "fdtfile=" CONFIG_FDTFILE "\0" \ 694 "ramdiskaddr=1000000\0" \ 695 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ 696 "console=ttyS0\0" \ 697 "setbootargs=setenv bootargs " \ 698 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 699 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 700 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 701 "$netdev:off " \ 702 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 703 704 #define CONFIG_NFSBOOTCOMMAND \ 705 "setenv rootdev /dev/nfs;" \ 706 "run setbootargs;" \ 707 "run setipargs;" \ 708 "tftp $loadaddr $bootfile;" \ 709 "tftp $fdtaddr $fdtfile;" \ 710 "bootm $loadaddr - $fdtaddr" 711 712 #define CONFIG_RAMBOOTCOMMAND \ 713 "setenv rootdev /dev/ram;" \ 714 "run setbootargs;" \ 715 "tftp $ramdiskaddr $ramdiskfile;" \ 716 "tftp $loadaddr $bootfile;" \ 717 "tftp $fdtaddr $fdtfile;" \ 718 "bootm $loadaddr $ramdiskaddr $fdtaddr" 719 720 #endif /* __CONFIG_H */ 721