1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Kevin Lam <kevin.lam@freescale.com> 4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef __CONFIG_H 23 #define __CONFIG_H 24 25 /* 26 * High Level Configuration Options 27 */ 28 #define CONFIG_E300 1 /* E300 family */ 29 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 30 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ 31 #define CONFIG_MPC837XERDB 1 32 33 #define CONFIG_PCI 1 34 35 #define CONFIG_BOARD_EARLY_INIT_F 36 #define CONFIG_MISC_INIT_R 37 38 /* 39 * On-board devices 40 */ 41 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 42 #define CONFIG_VSC7385_ENET 43 44 /* 45 * System Clock Setup 46 */ 47 #ifdef CONFIG_PCISLAVE 48 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ 49 #else 50 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ 51 #define CONFIG_83XX_GENERIC_PCI 1 52 #endif 53 54 #ifndef CONFIG_SYS_CLK_FREQ 55 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 56 #endif 57 58 /* 59 * Hardware Reset Configuration Word 60 */ 61 #define CONFIG_SYS_HRCW_LOW (\ 62 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 63 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 64 HRCWL_SVCOD_DIV_2 |\ 65 HRCWL_CSB_TO_CLKIN_5X1 |\ 66 HRCWL_CORE_TO_CSB_2X1) 67 68 #ifdef CONFIG_PCISLAVE 69 #define CONFIG_SYS_HRCW_HIGH (\ 70 HRCWH_PCI_AGENT |\ 71 HRCWH_PCI1_ARBITER_DISABLE |\ 72 HRCWH_CORE_ENABLE |\ 73 HRCWH_FROM_0XFFF00100 |\ 74 HRCWH_BOOTSEQ_DISABLE |\ 75 HRCWH_SW_WATCHDOG_DISABLE |\ 76 HRCWH_ROM_LOC_LOCAL_16BIT |\ 77 HRCWH_RL_EXT_LEGACY |\ 78 HRCWH_TSEC1M_IN_RGMII |\ 79 HRCWH_TSEC2M_IN_RGMII |\ 80 HRCWH_BIG_ENDIAN |\ 81 HRCWH_LDP_CLEAR) 82 #else 83 #define CONFIG_SYS_HRCW_HIGH (\ 84 HRCWH_PCI_HOST |\ 85 HRCWH_PCI1_ARBITER_ENABLE |\ 86 HRCWH_CORE_ENABLE |\ 87 HRCWH_FROM_0X00000100 |\ 88 HRCWH_BOOTSEQ_DISABLE |\ 89 HRCWH_SW_WATCHDOG_DISABLE |\ 90 HRCWH_ROM_LOC_LOCAL_16BIT |\ 91 HRCWH_RL_EXT_LEGACY |\ 92 HRCWH_TSEC1M_IN_RGMII |\ 93 HRCWH_TSEC2M_IN_RGMII |\ 94 HRCWH_BIG_ENDIAN |\ 95 HRCWH_LDP_CLEAR) 96 #endif 97 98 /* System performance - define the value i.e. CONFIG_SYS_XXX 99 */ 100 101 /* Arbiter Configuration Register */ 102 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 103 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 104 105 /* System Priority Control Regsiter */ 106 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ 107 108 /* System Clock Configuration Register */ 109 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ 110 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ 111 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ 112 113 /* 114 * System IO Config 115 */ 116 #define CONFIG_SYS_SICRH 0x08200000 117 #define CONFIG_SYS_SICRL 0x00000000 118 119 /* 120 * Output Buffer Impedance 121 */ 122 #define CONFIG_SYS_OBIR 0x30100000 123 124 /* 125 * IMMR new address 126 */ 127 #define CONFIG_SYS_IMMR 0xE0000000 128 129 /* 130 * Device configurations 131 */ 132 133 /* Vitesse 7385 */ 134 135 #ifdef CONFIG_VSC7385_ENET 136 137 #define CONFIG_TSEC2 138 139 /* The flash address and size of the VSC7385 firmware image */ 140 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 141 #define CONFIG_VSC7385_IMAGE_SIZE 8192 142 143 #endif 144 145 /* 146 * DDR Setup 147 */ 148 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 149 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 150 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 151 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 152 #define CONFIG_SYS_83XX_DDR_USES_CS0 153 154 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) 155 156 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 157 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 158 159 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 160 161 /* 162 * Manually set up DDR parameters 163 */ 164 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ 165 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 166 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ 167 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 168 169 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 170 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 171 | (0 << TIMING_CFG0_WRT_SHIFT) \ 172 | (0 << TIMING_CFG0_RRT_SHIFT) \ 173 | (0 << TIMING_CFG0_WWT_SHIFT) \ 174 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 175 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 176 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 177 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 178 /* 0x00220802 */ 179 /* 0x00260802 */ /* DDR400 */ 180 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 181 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 182 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 183 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 184 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 185 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 186 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 187 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 188 /* 0x3935d322 */ 189 /* 0x3937d322 */ 190 #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 191 192 #define CONFIG_SYS_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ 193 | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 194 /* 0x06090100 */ 195 196 #if defined(CONFIG_DDR_2T_TIMING) 197 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 198 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ 199 | SDRAM_CFG_2T_EN \ 200 | SDRAM_CFG_DBW_32) 201 #else 202 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 203 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) 204 /* 0x43000000 */ 205 #endif 206 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 207 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 208 | (0x0442 << SDRAM_MODE_SD_SHIFT)) 209 /* 0x04400442 */ /* DDR400 */ 210 #define CONFIG_SYS_DDR_MODE2 0x00000000 211 212 /* 213 * Memory test 214 */ 215 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 216 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 217 #define CONFIG_SYS_MEMTEST_END 0x0ef70010 218 219 /* 220 * The reserved memory 221 */ 222 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 223 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 225 #define CONFIG_SYS_RAMBOOT 226 #else 227 #undef CONFIG_SYS_RAMBOOT 228 #endif 229 230 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 231 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 232 233 /* 234 * Initial RAM Base Address Setup 235 */ 236 #define CONFIG_SYS_INIT_RAM_LOCK 1 237 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 238 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 239 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 240 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 241 242 /* 243 * Local Bus Configuration & Clock Setup 244 */ 245 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 246 #define CONFIG_SYS_LBC_LBCR 0x00000000 247 248 /* 249 * FLASH on the Local Bus 250 */ 251 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 252 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 253 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 254 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ 255 256 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 257 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 258 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 259 260 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 261 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ 262 263 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ 264 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ 265 BR_V) /* valid */ 266 #define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ 267 | OR_GPCM_XACS \ 268 | OR_GPCM_SCY_9 \ 269 | OR_GPCM_EHTR \ 270 | OR_GPCM_EAD) 271 /* 0xFF806FF7 TODO SLOW 8 MB flash size */ 272 273 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 274 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 275 276 #undef CONFIG_SYS_FLASH_CHECKSUM 277 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 278 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 279 280 /* 281 * NAND Flash on the Local Bus 282 */ 283 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 284 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \ 285 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ 286 BR_PS_8 | /* Port Size = 8 bit */ \ 287 BR_MS_FCM | /* MSEL = FCM */ \ 288 BR_V) /* valid */ 289 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ 290 OR_FCM_CSCT | \ 291 OR_FCM_CST | \ 292 OR_FCM_CHT | \ 293 OR_FCM_SCY_1 | \ 294 OR_FCM_TRLX | \ 295 OR_FCM_EHTR) 296 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 297 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 298 299 /* Vitesse 7385 */ 300 301 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 302 303 #ifdef CONFIG_VSC7385_ENET 304 305 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */ 306 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ 307 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */ 308 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ 309 310 #endif 311 312 /* 313 * Serial Port 314 */ 315 #define CONFIG_CONS_INDEX 1 316 #undef CONFIG_SERIAL_SOFTWARE_FIFO 317 #define CONFIG_SYS_NS16550 318 #define CONFIG_SYS_NS16550_SERIAL 319 #define CONFIG_SYS_NS16550_REG_SIZE 1 320 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 321 322 #define CONFIG_SYS_BAUDRATE_TABLE \ 323 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 324 325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 327 328 /* SERDES */ 329 #define CONFIG_FSL_SERDES 330 #define CONFIG_FSL_SERDES1 0xe3000 331 #define CONFIG_FSL_SERDES2 0xe3100 332 333 /* Use the HUSH parser */ 334 #define CONFIG_SYS_HUSH_PARSER 335 #ifdef CONFIG_SYS_HUSH_PARSER 336 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 337 #endif 338 339 /* Pass open firmware flat tree */ 340 #define CONFIG_OF_LIBFDT 1 341 #define CONFIG_OF_BOARD_SETUP 1 342 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 343 344 /* I2C */ 345 #define CONFIG_HARD_I2C /* I2C with hardware support */ 346 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 347 #define CONFIG_FSL_I2C 348 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 349 #define CONFIG_SYS_I2C_SLAVE 0x7F 350 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 351 #define CONFIG_SYS_I2C_OFFSET 0x3000 352 #define CONFIG_SYS_I2C2_OFFSET 0x3100 353 354 /* 355 * Config on-board RTC 356 */ 357 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 358 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 359 360 /* 361 * General PCI 362 * Addresses are mapped 1-1. 363 */ 364 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 365 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 366 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 368 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 369 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 370 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 371 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 372 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 373 374 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 375 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 376 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 377 378 #ifdef CONFIG_PCI 379 #define CONFIG_NET_MULTI 380 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 381 382 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 383 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 384 #endif /* CONFIG_PCI */ 385 386 /* 387 * TSEC 388 */ 389 #ifdef CONFIG_TSEC_ENET 390 391 #define CONFIG_NET_MULTI 392 #define CONFIG_GMII /* MII PHY management */ 393 394 #define CONFIG_TSEC1 395 396 #ifdef CONFIG_TSEC1 397 #define CONFIG_HAS_ETH0 398 #define CONFIG_TSEC1_NAME "TSEC0" 399 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 400 #define TSEC1_PHY_ADDR 2 401 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 402 #define TSEC1_PHYIDX 0 403 #endif 404 405 #ifdef CONFIG_TSEC2 406 #define CONFIG_HAS_ETH1 407 #define CONFIG_TSEC2_NAME "TSEC1" 408 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 409 #define TSEC2_PHY_ADDR 0x1c 410 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 411 #define TSEC2_PHYIDX 0 412 #endif 413 414 /* Options are: TSEC[0-1] */ 415 #define CONFIG_ETHPRIME "TSEC0" 416 417 #endif 418 419 /* 420 * SATA 421 */ 422 #define CONFIG_LIBATA 423 #define CONFIG_FSL_SATA 424 425 #define CONFIG_SYS_SATA_MAX_DEVICE 2 426 #define CONFIG_SATA1 427 #define CONFIG_SYS_SATA1_OFFSET 0x18000 428 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 429 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 430 #define CONFIG_SATA2 431 #define CONFIG_SYS_SATA2_OFFSET 0x19000 432 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 433 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 434 435 #ifdef CONFIG_FSL_SATA 436 #define CONFIG_LBA48 437 #define CONFIG_CMD_SATA 438 #define CONFIG_DOS_PARTITION 439 #define CONFIG_CMD_EXT2 440 #endif 441 442 /* 443 * Environment 444 */ 445 #ifndef CONFIG_SYS_RAMBOOT 446 #define CONFIG_ENV_IS_IN_FLASH 1 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) 448 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ 449 #define CONFIG_ENV_SIZE 0x4000 450 #else 451 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 452 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) 454 #define CONFIG_ENV_SIZE 0x2000 455 #endif 456 457 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 458 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 459 460 /* 461 * BOOTP options 462 */ 463 #define CONFIG_BOOTP_BOOTFILESIZE 464 #define CONFIG_BOOTP_BOOTPATH 465 #define CONFIG_BOOTP_GATEWAY 466 #define CONFIG_BOOTP_HOSTNAME 467 468 469 /* 470 * Command line configuration. 471 */ 472 #include <config_cmd_default.h> 473 474 #define CONFIG_CMD_PING 475 #define CONFIG_CMD_I2C 476 #define CONFIG_CMD_MII 477 #define CONFIG_CMD_DATE 478 479 #if defined(CONFIG_PCI) 480 #define CONFIG_CMD_PCI 481 #endif 482 483 #if defined(CONFIG_SYS_RAMBOOT) 484 #undef CONFIG_CMD_ENV 485 #undef CONFIG_CMD_LOADS 486 #endif 487 488 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 489 490 #undef CONFIG_WATCHDOG /* watchdog disabled */ 491 492 /* 493 * Miscellaneous configurable options 494 */ 495 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 496 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 497 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 498 499 #if defined(CONFIG_CMD_KGDB) 500 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 501 #else 502 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 503 #endif 504 505 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 506 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 507 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 508 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 509 510 /* 511 * For booting Linux, the board info and command line data 512 * have to be in the first 8 MB of memory, since this is 513 * the maximum mapped by the Linux kernel during initialization. 514 */ 515 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 516 517 /* 518 * Core HID Setup 519 */ 520 #define CONFIG_SYS_HID0_INIT 0x000000000 521 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 522 #define CONFIG_SYS_HID2 HID2_HBE 523 524 /* 525 * MMU Setup 526 */ 527 528 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 529 530 /* DDR: cache cacheable */ 531 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 532 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 533 534 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 535 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 536 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 537 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 538 539 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 540 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 541 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 542 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 543 544 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 545 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 546 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 547 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 548 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 549 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 550 551 /* L2 Switch: cache-inhibit and guarded */ 552 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \ 553 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 554 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) 555 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 556 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 557 558 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 559 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 560 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 561 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 562 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 563 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 564 565 /* Stack in dcache: cacheable, no memory coherence */ 566 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 567 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 568 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 569 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 570 571 #ifdef CONFIG_PCI 572 /* PCI MEM space: cacheable */ 573 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 574 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 575 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 576 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 577 /* PCI MMIO space: cache-inhibit and guarded */ 578 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ 579 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 580 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 581 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 582 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 583 #else 584 #define CONFIG_SYS_IBAT6L (0) 585 #define CONFIG_SYS_IBAT6U (0) 586 #define CONFIG_SYS_IBAT7L (0) 587 #define CONFIG_SYS_IBAT7U (0) 588 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 589 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 590 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 591 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 592 #endif 593 594 /* 595 * Internal Definitions 596 * 597 * Boot Flags 598 */ 599 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 600 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 601 602 #if defined(CONFIG_CMD_KGDB) 603 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 604 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 605 #endif 606 607 /* 608 * Environment Configuration 609 */ 610 #define CONFIG_ENV_OVERWRITE 611 612 #ifdef CONFIG_HAS_ETH0 613 #define CONFIG_ETHADDR 00:04:9f:ef:04:01 614 #endif 615 616 #ifdef CONFIG_HAS_ETH1 617 #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02 618 #endif 619 620 #define CONFIG_HAS_FSL_DR_USB 621 622 #define CONFIG_IPADDR 10.0.0.2 623 #define CONFIG_SERVERIP 10.0.0.1 624 #define CONFIG_GATEWAYIP 10.0.0.1 625 #define CONFIG_NETMASK 255.0.0.0 626 #define CONFIG_NETDEV eth1 627 628 #define CONFIG_HOSTNAME mpc837x_rdb 629 #define CONFIG_ROOTPATH /nfsroot 630 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot 631 #define CONFIG_BOOTFILE uImage 632 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 633 #define CONFIG_FDTFILE mpc8379_rdb.dtb 634 635 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 636 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 637 #define CONFIG_BAUDRATE 115200 638 639 #define XMK_STR(x) #x 640 #define MK_STR(x) XMK_STR(x) 641 642 #define CONFIG_EXTRA_ENV_SETTINGS \ 643 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 644 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 645 "tftpflash=tftp $loadaddr $uboot;" \ 646 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 647 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 648 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 649 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 650 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 651 "fdtaddr=400000\0" \ 652 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ 653 "ramdiskaddr=1000000\0" \ 654 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ 655 "console=ttyS0\0" \ 656 "setbootargs=setenv bootargs " \ 657 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ 658 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ 659 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 660 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" 661 662 #define CONFIG_NFSBOOTCOMMAND \ 663 "setenv rootdev /dev/nfs;" \ 664 "run setbootargs;" \ 665 "run setipargs;" \ 666 "tftp $loadaddr $bootfile;" \ 667 "tftp $fdtaddr $fdtfile;" \ 668 "bootm $loadaddr - $fdtaddr" 669 670 #define CONFIG_RAMBOOTCOMMAND \ 671 "setenv rootdev /dev/ram;" \ 672 "run setbootargs;" \ 673 "tftp $ramdiskaddr $ramdiskfile;" \ 674 "tftp $loadaddr $bootfile;" \ 675 "tftp $fdtaddr $fdtfile;" \ 676 "bootm $loadaddr $ramdiskaddr $fdtaddr" 677 678 #undef MK_STR 679 #undef XMK_STR 680 681 #endif /* __CONFIG_H */ 682