1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300		1 /* E300 family */
16 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
17 #define CONFIG_MPC837XERDB	1
18 #define CONFIG_DISPLAY_BOARDINFO
19 
20 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
21 
22 #define CONFIG_PCI	1
23 
24 #define CONFIG_BOARD_EARLY_INIT_F
25 #define CONFIG_MISC_INIT_R
26 #define CONFIG_HWCONFIG
27 
28 /*
29  * On-board devices
30  */
31 #define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
32 #define CONFIG_VSC7385_ENET
33 
34 /*
35  * System Clock Setup
36  */
37 #ifdef CONFIG_PCISLAVE
38 #define CONFIG_83XX_PCICLK	66666667 /* in HZ */
39 #else
40 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
41 #define CONFIG_PCIE
42 #endif
43 
44 #ifndef CONFIG_SYS_CLK_FREQ
45 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
46 #endif
47 
48 /*
49  * Hardware Reset Configuration Word
50  */
51 #define CONFIG_SYS_HRCW_LOW (\
52 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
53 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
54 	HRCWL_SVCOD_DIV_2 |\
55 	HRCWL_CSB_TO_CLKIN_5X1 |\
56 	HRCWL_CORE_TO_CSB_2X1)
57 
58 #ifdef CONFIG_PCISLAVE
59 #define CONFIG_SYS_HRCW_HIGH (\
60 	HRCWH_PCI_AGENT |\
61 	HRCWH_PCI1_ARBITER_DISABLE |\
62 	HRCWH_CORE_ENABLE |\
63 	HRCWH_FROM_0XFFF00100 |\
64 	HRCWH_BOOTSEQ_DISABLE |\
65 	HRCWH_SW_WATCHDOG_DISABLE |\
66 	HRCWH_ROM_LOC_LOCAL_16BIT |\
67 	HRCWH_RL_EXT_LEGACY |\
68 	HRCWH_TSEC1M_IN_RGMII |\
69 	HRCWH_TSEC2M_IN_RGMII |\
70 	HRCWH_BIG_ENDIAN |\
71 	HRCWH_LDP_CLEAR)
72 #else
73 #define CONFIG_SYS_HRCW_HIGH (\
74 	HRCWH_PCI_HOST |\
75 	HRCWH_PCI1_ARBITER_ENABLE |\
76 	HRCWH_CORE_ENABLE |\
77 	HRCWH_FROM_0X00000100 |\
78 	HRCWH_BOOTSEQ_DISABLE |\
79 	HRCWH_SW_WATCHDOG_DISABLE |\
80 	HRCWH_ROM_LOC_LOCAL_16BIT |\
81 	HRCWH_RL_EXT_LEGACY |\
82 	HRCWH_TSEC1M_IN_RGMII |\
83 	HRCWH_TSEC2M_IN_RGMII |\
84 	HRCWH_BIG_ENDIAN |\
85 	HRCWH_LDP_CLEAR)
86 #endif
87 
88 /* System performance - define the value i.e. CONFIG_SYS_XXX
89 */
90 
91 /* Arbiter Configuration Register */
92 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
93 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
94 
95 /* System Priority Control Regsiter */
96 #define CONFIG_SYS_SPCR_TSECEP	3	/* eTSEC1&2 emergency priority (0-3) */
97 
98 /* System Clock Configuration Register */
99 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
100 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
101 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
102 
103 /*
104  * System IO Config
105  */
106 #define CONFIG_SYS_SICRH		0x08200000
107 #define CONFIG_SYS_SICRL		0x00000000
108 
109 /*
110  * Output Buffer Impedance
111  */
112 #define CONFIG_SYS_OBIR		0x30100000
113 
114 /*
115  * IMMR new address
116  */
117 #define CONFIG_SYS_IMMR		0xE0000000
118 
119 /*
120  * Device configurations
121  */
122 
123 /* Vitesse 7385 */
124 
125 #ifdef CONFIG_VSC7385_ENET
126 
127 #define CONFIG_TSEC2
128 
129 /* The flash address and size of the VSC7385 firmware image */
130 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
131 #define CONFIG_VSC7385_IMAGE_SIZE	8192
132 
133 #endif
134 
135 /*
136  * DDR Setup
137  */
138 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
139 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
140 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
141 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
142 #define CONFIG_SYS_83XX_DDR_USES_CS0
143 
144 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
145 
146 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
147 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
148 
149 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
150 
151 /*
152  * Manually set up DDR parameters
153  */
154 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
155 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
156 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
157 					| CSCONFIG_ODT_WR_ONLY_CURRENT \
158 					| CSCONFIG_ROW_BIT_13 \
159 					| CSCONFIG_COL_BIT_10)
160 
161 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
162 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
163 				| (0 << TIMING_CFG0_WRT_SHIFT) \
164 				| (0 << TIMING_CFG0_RRT_SHIFT) \
165 				| (0 << TIMING_CFG0_WWT_SHIFT) \
166 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
167 				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
168 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
169 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
170 				/* 0x00260802 */ /* DDR400 */
171 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
172 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
173 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
174 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
175 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
176 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
177 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
178 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
179 				/* 0x3937d322 */
180 #define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
181 				| (5 << TIMING_CFG2_CPO_SHIFT) \
182 				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
183 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
184 				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
185 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
186 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
187 				/* 0x02984cc8 */
188 
189 #define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
190 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
191 				/* 0x06090100 */
192 
193 #if defined(CONFIG_DDR_2T_TIMING)
194 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
195 					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
196 					| SDRAM_CFG_32_BE \
197 					| SDRAM_CFG_2T_EN)
198 					/* 0x43088000 */
199 #else
200 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
201 					| SDRAM_CFG_SDRAM_TYPE_DDR2)
202 					/* 0x43000000 */
203 #endif
204 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
205 #define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
206 					| (0x0442 << SDRAM_MODE_SD_SHIFT))
207 					/* 0x04400442 */ /* DDR400 */
208 #define CONFIG_SYS_DDR_MODE2		0x00000000
209 
210 /*
211  * Memory test
212  */
213 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
214 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
215 #define CONFIG_SYS_MEMTEST_END		0x0ef70010
216 
217 /*
218  * The reserved memory
219  */
220 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
221 
222 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223 #define CONFIG_SYS_RAMBOOT
224 #else
225 #undef	CONFIG_SYS_RAMBOOT
226 #endif
227 
228 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
229 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
230 
231 /*
232  * Initial RAM Base Address Setup
233  */
234 #define CONFIG_SYS_INIT_RAM_LOCK	1
235 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
236 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
237 #define CONFIG_SYS_GBL_DATA_OFFSET	\
238 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
239 
240 /*
241  * Local Bus Configuration & Clock Setup
242  */
243 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
244 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
245 #define CONFIG_SYS_LBC_LBCR		0x00000000
246 #define CONFIG_FSL_ELBC		1
247 
248 /*
249  * FLASH on the Local Bus
250  */
251 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
252 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
253 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
254 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
255 
256 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
257 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
258 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
259 
260 					/* Window base at flash base */
261 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
262 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
263 
264 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
265 				| BR_PS_16	/* 16 bit port */ \
266 				| BR_MS_GPCM	/* MSEL = GPCM */ \
267 				| BR_V)		/* valid */
268 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
269 				| OR_GPCM_XACS \
270 				| OR_GPCM_SCY_9 \
271 				| OR_GPCM_EHTR_SET \
272 				| OR_GPCM_EAD)
273 				/* 0xFF800191 */
274 
275 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
276 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
277 
278 #undef	CONFIG_SYS_FLASH_CHECKSUM
279 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
280 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
281 
282 /*
283  * NAND Flash on the Local Bus
284  */
285 #define CONFIG_SYS_NAND_BASE	0xE0600000
286 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
287 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
288 				| BR_PS_8		/* 8 bit port */ \
289 				| BR_MS_FCM		/* MSEL = FCM */ \
290 				| BR_V)			/* valid */
291 #define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
292 				| OR_FCM_CSCT \
293 				| OR_FCM_CST \
294 				| OR_FCM_CHT \
295 				| OR_FCM_SCY_1 \
296 				| OR_FCM_TRLX \
297 				| OR_FCM_EHTR)
298 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
299 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
300 
301 /* Vitesse 7385 */
302 
303 #define CONFIG_SYS_VSC7385_BASE	0xF0000000
304 
305 #ifdef CONFIG_VSC7385_ENET
306 
307 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
308 					| BR_PS_8 \
309 					| BR_MS_GPCM \
310 					| BR_V)
311 					/* 0xF0000801 */
312 #define CONFIG_SYS_OR2_PRELIM		(OR_AM_128KB \
313 					| OR_GPCM_CSNT \
314 					| OR_GPCM_XACS \
315 					| OR_GPCM_SCY_15 \
316 					| OR_GPCM_SETA \
317 					| OR_GPCM_TRLX_SET \
318 					| OR_GPCM_EHTR_SET \
319 					| OR_GPCM_EAD)
320 					/* 0xfffe09ff */
321 
322 					/* Access Base */
323 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
324 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
325 
326 #endif
327 
328 /*
329  * Serial Port
330  */
331 #define CONFIG_CONS_INDEX	1
332 #define CONFIG_SYS_NS16550_SERIAL
333 #define CONFIG_SYS_NS16550_REG_SIZE	1
334 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
335 
336 #define CONFIG_SYS_BAUDRATE_TABLE \
337 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
338 
339 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
340 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
341 
342 /* SERDES */
343 #define CONFIG_FSL_SERDES
344 #define CONFIG_FSL_SERDES1	0xe3000
345 #define CONFIG_FSL_SERDES2	0xe3100
346 
347 /* Use the HUSH parser */
348 #define CONFIG_SYS_HUSH_PARSER
349 
350 /* I2C */
351 #define CONFIG_SYS_I2C
352 #define CONFIG_SYS_I2C_FSL
353 #define CONFIG_SYS_FSL_I2C_SPEED	400000
354 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
355 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
356 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
357 
358 /*
359  * Config on-board RTC
360  */
361 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
362 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
363 
364 /*
365  * General PCI
366  * Addresses are mapped 1-1.
367  */
368 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
369 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
370 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
371 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
372 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
373 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
374 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
375 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
376 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
377 
378 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
379 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
380 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
381 
382 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
383 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
384 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
385 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
386 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
387 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
388 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
389 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
390 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
391 
392 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
393 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
394 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
395 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
396 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
397 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
398 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
399 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
400 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
401 
402 #ifdef CONFIG_PCI
403 #define CONFIG_PCI_INDIRECT_BRIDGE
404 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
405 
406 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
407 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
408 #endif	/* CONFIG_PCI */
409 
410 /*
411  * TSEC
412  */
413 #ifdef CONFIG_TSEC_ENET
414 
415 #define CONFIG_GMII			/* MII PHY management */
416 
417 #define CONFIG_TSEC1
418 
419 #ifdef CONFIG_TSEC1
420 #define CONFIG_HAS_ETH0
421 #define CONFIG_TSEC1_NAME		"TSEC0"
422 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
423 #define TSEC1_PHY_ADDR			2
424 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
425 #define TSEC1_PHYIDX			0
426 #endif
427 
428 #ifdef CONFIG_TSEC2
429 #define CONFIG_HAS_ETH1
430 #define CONFIG_TSEC2_NAME		"TSEC1"
431 #define CONFIG_SYS_TSEC2_OFFSET		0x25000
432 #define TSEC2_PHY_ADDR			0x1c
433 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
434 #define TSEC2_PHYIDX			0
435 #endif
436 
437 /* Options are: TSEC[0-1] */
438 #define CONFIG_ETHPRIME			"TSEC0"
439 
440 #endif
441 
442 /*
443  * SATA
444  */
445 #define CONFIG_LIBATA
446 #define CONFIG_FSL_SATA
447 
448 #define CONFIG_SYS_SATA_MAX_DEVICE	2
449 #define CONFIG_SATA1
450 #define CONFIG_SYS_SATA1_OFFSET	0x18000
451 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
452 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
453 #define CONFIG_SATA2
454 #define CONFIG_SYS_SATA2_OFFSET	0x19000
455 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
456 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
457 
458 #ifdef CONFIG_FSL_SATA
459 #define CONFIG_LBA48
460 #define CONFIG_CMD_SATA
461 #define CONFIG_DOS_PARTITION
462 #define CONFIG_CMD_EXT2
463 #endif
464 
465 /*
466  * Environment
467  */
468 #ifndef CONFIG_SYS_RAMBOOT
469 	#define CONFIG_ENV_IS_IN_FLASH	1
470 	#define CONFIG_ENV_ADDR		\
471 			(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
472 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
473 	#define CONFIG_ENV_SIZE		0x4000
474 #else
475 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
476 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
477 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
478 	#define CONFIG_ENV_SIZE		0x2000
479 #endif
480 
481 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
482 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
483 
484 /*
485  * BOOTP options
486  */
487 #define CONFIG_BOOTP_BOOTFILESIZE
488 #define CONFIG_BOOTP_BOOTPATH
489 #define CONFIG_BOOTP_GATEWAY
490 #define CONFIG_BOOTP_HOSTNAME
491 
492 
493 /*
494  * Command line configuration.
495  */
496 #define CONFIG_CMD_PING
497 #define CONFIG_CMD_I2C
498 #define CONFIG_CMD_MII
499 #define CONFIG_CMD_DATE
500 
501 #if defined(CONFIG_PCI)
502 #define CONFIG_CMD_PCI
503 #endif
504 
505 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
506 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
507 
508 #undef CONFIG_WATCHDOG		/* watchdog disabled */
509 
510 #define CONFIG_MMC     1
511 
512 #ifdef CONFIG_MMC
513 #define CONFIG_FSL_ESDHC
514 #define CONFIG_FSL_ESDHC_PIN_MUX
515 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
516 #define CONFIG_CMD_MMC
517 #define CONFIG_GENERIC_MMC
518 #define CONFIG_CMD_EXT2
519 #define CONFIG_CMD_FAT
520 #define CONFIG_DOS_PARTITION
521 #endif
522 
523 /*
524  * Miscellaneous configurable options
525  */
526 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
527 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
528 
529 #if defined(CONFIG_CMD_KGDB)
530 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
531 #else
532 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
533 #endif
534 
535 				/* Print Buffer Size */
536 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
537 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
538 				/* Boot Argument Buffer Size */
539 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
540 
541 /*
542  * For booting Linux, the board info and command line data
543  * have to be in the first 256 MB of memory, since this is
544  * the maximum mapped by the Linux kernel during initialization.
545  */
546 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
547 
548 /*
549  * Core HID Setup
550  */
551 #define CONFIG_SYS_HID0_INIT	0x000000000
552 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
553 				| HID0_ENABLE_INSTRUCTION_CACHE)
554 #define CONFIG_SYS_HID2		HID2_HBE
555 
556 /*
557  * MMU Setup
558  */
559 
560 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
561 
562 /* DDR: cache cacheable */
563 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
564 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
565 
566 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
567 				| BATL_PP_RW \
568 				| BATL_MEMCOHERENCE)
569 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
570 				| BATU_BL_256M \
571 				| BATU_VS \
572 				| BATU_VP)
573 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
574 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
575 
576 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
577 				| BATL_PP_RW \
578 				| BATL_MEMCOHERENCE)
579 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
580 				| BATU_BL_256M \
581 				| BATU_VS \
582 				| BATU_VP)
583 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
584 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
585 
586 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
587 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
588 				| BATL_PP_RW \
589 				| BATL_CACHEINHIBIT \
590 				| BATL_GUARDEDSTORAGE)
591 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
592 				| BATU_BL_8M \
593 				| BATU_VS \
594 				| BATU_VP)
595 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
596 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
597 
598 /* L2 Switch: cache-inhibit and guarded */
599 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_VSC7385_BASE \
600 				| BATL_PP_RW \
601 				| BATL_CACHEINHIBIT \
602 				| BATL_GUARDEDSTORAGE)
603 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_VSC7385_BASE \
604 				| BATU_BL_128K \
605 				| BATU_VS \
606 				| BATU_VP)
607 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
608 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
609 
610 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
611 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
612 				| BATL_PP_RW \
613 				| BATL_MEMCOHERENCE)
614 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
615 				| BATU_BL_32M \
616 				| BATU_VS \
617 				| BATU_VP)
618 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
619 				| BATL_PP_RW \
620 				| BATL_CACHEINHIBIT \
621 				| BATL_GUARDEDSTORAGE)
622 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
623 
624 /* Stack in dcache: cacheable, no memory coherence */
625 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
626 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
627 				| BATU_BL_128K \
628 				| BATU_VS \
629 				| BATU_VP)
630 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
631 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
632 
633 #ifdef CONFIG_PCI
634 /* PCI MEM space: cacheable */
635 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
636 				| BATL_PP_RW \
637 				| BATL_MEMCOHERENCE)
638 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
639 				| BATU_BL_256M \
640 				| BATU_VS \
641 				| BATU_VP)
642 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
643 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
644 /* PCI MMIO space: cache-inhibit and guarded */
645 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
646 				| BATL_PP_RW \
647 				| BATL_CACHEINHIBIT \
648 				| BATL_GUARDEDSTORAGE)
649 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
650 				| BATU_BL_256M \
651 				| BATU_VS \
652 				| BATU_VP)
653 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
654 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
655 #else
656 #define CONFIG_SYS_IBAT6L	(0)
657 #define CONFIG_SYS_IBAT6U	(0)
658 #define CONFIG_SYS_IBAT7L	(0)
659 #define CONFIG_SYS_IBAT7U	(0)
660 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
661 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
662 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
663 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
664 #endif
665 
666 #if defined(CONFIG_CMD_KGDB)
667 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
668 #endif
669 
670 /*
671  * Environment Configuration
672  */
673 #define CONFIG_ENV_OVERWRITE
674 
675 #define CONFIG_HAS_FSL_DR_USB
676 #define CONFIG_CMD_USB
677 #define CONFIG_USB_STORAGE
678 #define CONFIG_USB_EHCI
679 #define CONFIG_USB_EHCI_FSL
680 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
681 
682 #define CONFIG_NETDEV		"eth1"
683 
684 #define CONFIG_HOSTNAME		mpc837x_rdb
685 #define CONFIG_ROOTPATH		"/nfsroot"
686 #define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
687 #define CONFIG_BOOTFILE		"uImage"
688 				/* U-Boot image on TFTP server */
689 #define CONFIG_UBOOTPATH	"u-boot.bin"
690 #define CONFIG_FDTFILE		"mpc8379_rdb.dtb"
691 
692 				/* default location for tftp and bootm */
693 #define CONFIG_LOADADDR		800000
694 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
695 #define CONFIG_BAUDRATE		115200
696 
697 #define CONFIG_EXTRA_ENV_SETTINGS \
698 	"netdev=" CONFIG_NETDEV "\0"				\
699 	"uboot=" CONFIG_UBOOTPATH "\0"					\
700 	"tftpflash=tftp $loadaddr $uboot;"				\
701 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
702 			" +$filesize; "	\
703 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
704 			" +$filesize; "	\
705 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
706 			" $filesize; "	\
707 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
708 			" +$filesize; "	\
709 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
710 			" $filesize\0"	\
711 	"fdtaddr=780000\0"						\
712 	"fdtfile=" CONFIG_FDTFILE "\0"					\
713 	"ramdiskaddr=1000000\0"						\
714 	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
715 	"console=ttyS0\0"						\
716 	"setbootargs=setenv bootargs "					\
717 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
718 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
719 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
720 							"$netdev:off "	\
721 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
722 
723 #define CONFIG_NFSBOOTCOMMAND						\
724 	"setenv rootdev /dev/nfs;"					\
725 	"run setbootargs;"						\
726 	"run setipargs;"						\
727 	"tftp $loadaddr $bootfile;"					\
728 	"tftp $fdtaddr $fdtfile;"					\
729 	"bootm $loadaddr - $fdtaddr"
730 
731 #define CONFIG_RAMBOOTCOMMAND						\
732 	"setenv rootdev /dev/ram;"					\
733 	"run setbootargs;"						\
734 	"tftp $ramdiskaddr $ramdiskfile;"				\
735 	"tftp $loadaddr $bootfile;"					\
736 	"tftp $fdtaddr $fdtfile;"					\
737 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
738 
739 #endif	/* __CONFIG_H */
740