1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11 
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300		1 /* E300 family */
16 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
17 #define CONFIG_MPC837XERDB	1
18 
19 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
20 
21 #define CONFIG_PCI	1
22 
23 #define CONFIG_BOARD_EARLY_INIT_F
24 #define CONFIG_MISC_INIT_R
25 #define CONFIG_HWCONFIG
26 
27 /*
28  * On-board devices
29  */
30 #define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
31 #define CONFIG_VSC7385_ENET
32 
33 /*
34  * System Clock Setup
35  */
36 #ifdef CONFIG_PCISLAVE
37 #define CONFIG_83XX_PCICLK	66666667 /* in HZ */
38 #else
39 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
40 #define CONFIG_PCIE
41 #endif
42 
43 #ifndef CONFIG_SYS_CLK_FREQ
44 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
45 #endif
46 
47 /*
48  * Hardware Reset Configuration Word
49  */
50 #define CONFIG_SYS_HRCW_LOW (\
51 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
53 	HRCWL_SVCOD_DIV_2 |\
54 	HRCWL_CSB_TO_CLKIN_5X1 |\
55 	HRCWL_CORE_TO_CSB_2X1)
56 
57 #ifdef CONFIG_PCISLAVE
58 #define CONFIG_SYS_HRCW_HIGH (\
59 	HRCWH_PCI_AGENT |\
60 	HRCWH_PCI1_ARBITER_DISABLE |\
61 	HRCWH_CORE_ENABLE |\
62 	HRCWH_FROM_0XFFF00100 |\
63 	HRCWH_BOOTSEQ_DISABLE |\
64 	HRCWH_SW_WATCHDOG_DISABLE |\
65 	HRCWH_ROM_LOC_LOCAL_16BIT |\
66 	HRCWH_RL_EXT_LEGACY |\
67 	HRCWH_TSEC1M_IN_RGMII |\
68 	HRCWH_TSEC2M_IN_RGMII |\
69 	HRCWH_BIG_ENDIAN |\
70 	HRCWH_LDP_CLEAR)
71 #else
72 #define CONFIG_SYS_HRCW_HIGH (\
73 	HRCWH_PCI_HOST |\
74 	HRCWH_PCI1_ARBITER_ENABLE |\
75 	HRCWH_CORE_ENABLE |\
76 	HRCWH_FROM_0X00000100 |\
77 	HRCWH_BOOTSEQ_DISABLE |\
78 	HRCWH_SW_WATCHDOG_DISABLE |\
79 	HRCWH_ROM_LOC_LOCAL_16BIT |\
80 	HRCWH_RL_EXT_LEGACY |\
81 	HRCWH_TSEC1M_IN_RGMII |\
82 	HRCWH_TSEC2M_IN_RGMII |\
83 	HRCWH_BIG_ENDIAN |\
84 	HRCWH_LDP_CLEAR)
85 #endif
86 
87 /* System performance - define the value i.e. CONFIG_SYS_XXX
88 */
89 
90 /* Arbiter Configuration Register */
91 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
92 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
93 
94 /* System Priority Control Regsiter */
95 #define CONFIG_SYS_SPCR_TSECEP	3	/* eTSEC1&2 emergency priority (0-3) */
96 
97 /* System Clock Configuration Register */
98 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
99 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
100 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
101 
102 /*
103  * System IO Config
104  */
105 #define CONFIG_SYS_SICRH		0x08200000
106 #define CONFIG_SYS_SICRL		0x00000000
107 
108 /*
109  * Output Buffer Impedance
110  */
111 #define CONFIG_SYS_OBIR		0x30100000
112 
113 /*
114  * IMMR new address
115  */
116 #define CONFIG_SYS_IMMR		0xE0000000
117 
118 /*
119  * Device configurations
120  */
121 
122 /* Vitesse 7385 */
123 
124 #ifdef CONFIG_VSC7385_ENET
125 
126 #define CONFIG_TSEC2
127 
128 /* The flash address and size of the VSC7385 firmware image */
129 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
130 #define CONFIG_VSC7385_IMAGE_SIZE	8192
131 
132 #endif
133 
134 /*
135  * DDR Setup
136  */
137 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
138 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
139 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
140 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
141 #define CONFIG_SYS_83XX_DDR_USES_CS0
142 
143 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
144 
145 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
146 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
147 
148 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
149 
150 /*
151  * Manually set up DDR parameters
152  */
153 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
154 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
155 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
156 					| CSCONFIG_ODT_WR_ONLY_CURRENT \
157 					| CSCONFIG_ROW_BIT_13 \
158 					| CSCONFIG_COL_BIT_10)
159 
160 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
161 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
162 				| (0 << TIMING_CFG0_WRT_SHIFT) \
163 				| (0 << TIMING_CFG0_RRT_SHIFT) \
164 				| (0 << TIMING_CFG0_WWT_SHIFT) \
165 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
166 				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
167 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
168 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
169 				/* 0x00260802 */ /* DDR400 */
170 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
171 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
172 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
173 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
174 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
175 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
176 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
177 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
178 				/* 0x3937d322 */
179 #define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
180 				| (5 << TIMING_CFG2_CPO_SHIFT) \
181 				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
182 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
183 				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
184 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
185 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
186 				/* 0x02984cc8 */
187 
188 #define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
189 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
190 				/* 0x06090100 */
191 
192 #if defined(CONFIG_DDR_2T_TIMING)
193 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
194 					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
195 					| SDRAM_CFG_32_BE \
196 					| SDRAM_CFG_2T_EN)
197 					/* 0x43088000 */
198 #else
199 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
200 					| SDRAM_CFG_SDRAM_TYPE_DDR2)
201 					/* 0x43000000 */
202 #endif
203 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
204 #define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
205 					| (0x0442 << SDRAM_MODE_SD_SHIFT))
206 					/* 0x04400442 */ /* DDR400 */
207 #define CONFIG_SYS_DDR_MODE2		0x00000000
208 
209 /*
210  * Memory test
211  */
212 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
213 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
214 #define CONFIG_SYS_MEMTEST_END		0x0ef70010
215 
216 /*
217  * The reserved memory
218  */
219 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
220 
221 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
222 #define CONFIG_SYS_RAMBOOT
223 #else
224 #undef	CONFIG_SYS_RAMBOOT
225 #endif
226 
227 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
228 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
229 
230 /*
231  * Initial RAM Base Address Setup
232  */
233 #define CONFIG_SYS_INIT_RAM_LOCK	1
234 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
235 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
236 #define CONFIG_SYS_GBL_DATA_OFFSET	\
237 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
238 
239 /*
240  * Local Bus Configuration & Clock Setup
241  */
242 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
243 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
244 #define CONFIG_SYS_LBC_LBCR		0x00000000
245 #define CONFIG_FSL_ELBC		1
246 
247 /*
248  * FLASH on the Local Bus
249  */
250 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
251 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
252 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
253 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
254 
255 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
256 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
257 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
258 
259 					/* Window base at flash base */
260 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
261 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
262 
263 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
264 				| BR_PS_16	/* 16 bit port */ \
265 				| BR_MS_GPCM	/* MSEL = GPCM */ \
266 				| BR_V)		/* valid */
267 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
268 				| OR_GPCM_XACS \
269 				| OR_GPCM_SCY_9 \
270 				| OR_GPCM_EHTR_SET \
271 				| OR_GPCM_EAD)
272 				/* 0xFF800191 */
273 
274 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
275 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
276 
277 #undef	CONFIG_SYS_FLASH_CHECKSUM
278 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
279 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
280 
281 /*
282  * NAND Flash on the Local Bus
283  */
284 #define CONFIG_SYS_NAND_BASE	0xE0600000
285 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
286 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
287 				| BR_PS_8		/* 8 bit port */ \
288 				| BR_MS_FCM		/* MSEL = FCM */ \
289 				| BR_V)			/* valid */
290 #define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
291 				| OR_FCM_CSCT \
292 				| OR_FCM_CST \
293 				| OR_FCM_CHT \
294 				| OR_FCM_SCY_1 \
295 				| OR_FCM_TRLX \
296 				| OR_FCM_EHTR)
297 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
298 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
299 
300 /* Vitesse 7385 */
301 
302 #define CONFIG_SYS_VSC7385_BASE	0xF0000000
303 
304 #ifdef CONFIG_VSC7385_ENET
305 
306 #define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
307 					| BR_PS_8 \
308 					| BR_MS_GPCM \
309 					| BR_V)
310 					/* 0xF0000801 */
311 #define CONFIG_SYS_OR2_PRELIM		(OR_AM_128KB \
312 					| OR_GPCM_CSNT \
313 					| OR_GPCM_XACS \
314 					| OR_GPCM_SCY_15 \
315 					| OR_GPCM_SETA \
316 					| OR_GPCM_TRLX_SET \
317 					| OR_GPCM_EHTR_SET \
318 					| OR_GPCM_EAD)
319 					/* 0xfffe09ff */
320 
321 					/* Access Base */
322 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
323 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
324 
325 #endif
326 
327 /*
328  * Serial Port
329  */
330 #define CONFIG_CONS_INDEX	1
331 #define CONFIG_SYS_NS16550
332 #define CONFIG_SYS_NS16550_SERIAL
333 #define CONFIG_SYS_NS16550_REG_SIZE	1
334 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
335 
336 #define CONFIG_SYS_BAUDRATE_TABLE \
337 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
338 
339 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
340 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
341 
342 /* SERDES */
343 #define CONFIG_FSL_SERDES
344 #define CONFIG_FSL_SERDES1	0xe3000
345 #define CONFIG_FSL_SERDES2	0xe3100
346 
347 /* Use the HUSH parser */
348 #define CONFIG_SYS_HUSH_PARSER
349 
350 /* Pass open firmware flat tree */
351 #define CONFIG_OF_LIBFDT	1
352 #define CONFIG_OF_BOARD_SETUP	1
353 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
354 
355 /* I2C */
356 #define CONFIG_SYS_I2C
357 #define CONFIG_SYS_I2C_FSL
358 #define CONFIG_SYS_FSL_I2C_SPEED	400000
359 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
360 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
361 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
362 
363 /*
364  * Config on-board RTC
365  */
366 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
367 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
368 
369 /*
370  * General PCI
371  * Addresses are mapped 1-1.
372  */
373 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
374 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
375 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
376 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
377 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
378 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
379 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
380 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
381 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
382 
383 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
384 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
385 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
386 
387 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
388 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
389 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
390 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
391 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
392 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
393 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
394 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
395 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
396 
397 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
398 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
399 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
400 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
401 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
402 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
403 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
404 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
405 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
406 
407 #ifdef CONFIG_PCI
408 #define CONFIG_PCI_INDIRECT_BRIDGE
409 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
410 
411 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
412 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
413 #endif	/* CONFIG_PCI */
414 
415 /*
416  * TSEC
417  */
418 #ifdef CONFIG_TSEC_ENET
419 
420 #define CONFIG_GMII			/* MII PHY management */
421 
422 #define CONFIG_TSEC1
423 
424 #ifdef CONFIG_TSEC1
425 #define CONFIG_HAS_ETH0
426 #define CONFIG_TSEC1_NAME		"TSEC0"
427 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
428 #define TSEC1_PHY_ADDR			2
429 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
430 #define TSEC1_PHYIDX			0
431 #endif
432 
433 #ifdef CONFIG_TSEC2
434 #define CONFIG_HAS_ETH1
435 #define CONFIG_TSEC2_NAME		"TSEC1"
436 #define CONFIG_SYS_TSEC2_OFFSET		0x25000
437 #define TSEC2_PHY_ADDR			0x1c
438 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
439 #define TSEC2_PHYIDX			0
440 #endif
441 
442 /* Options are: TSEC[0-1] */
443 #define CONFIG_ETHPRIME			"TSEC0"
444 
445 #endif
446 
447 /*
448  * SATA
449  */
450 #define CONFIG_LIBATA
451 #define CONFIG_FSL_SATA
452 
453 #define CONFIG_SYS_SATA_MAX_DEVICE	2
454 #define CONFIG_SATA1
455 #define CONFIG_SYS_SATA1_OFFSET	0x18000
456 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
457 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
458 #define CONFIG_SATA2
459 #define CONFIG_SYS_SATA2_OFFSET	0x19000
460 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
461 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
462 
463 #ifdef CONFIG_FSL_SATA
464 #define CONFIG_LBA48
465 #define CONFIG_CMD_SATA
466 #define CONFIG_DOS_PARTITION
467 #define CONFIG_CMD_EXT2
468 #endif
469 
470 /*
471  * Environment
472  */
473 #ifndef CONFIG_SYS_RAMBOOT
474 	#define CONFIG_ENV_IS_IN_FLASH	1
475 	#define CONFIG_ENV_ADDR		\
476 			(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
477 	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
478 	#define CONFIG_ENV_SIZE		0x4000
479 #else
480 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
481 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
482 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
483 	#define CONFIG_ENV_SIZE		0x2000
484 #endif
485 
486 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
487 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
488 
489 /*
490  * BOOTP options
491  */
492 #define CONFIG_BOOTP_BOOTFILESIZE
493 #define CONFIG_BOOTP_BOOTPATH
494 #define CONFIG_BOOTP_GATEWAY
495 #define CONFIG_BOOTP_HOSTNAME
496 
497 
498 /*
499  * Command line configuration.
500  */
501 #include <config_cmd_default.h>
502 
503 #define CONFIG_CMD_PING
504 #define CONFIG_CMD_I2C
505 #define CONFIG_CMD_MII
506 #define CONFIG_CMD_DATE
507 
508 #if defined(CONFIG_PCI)
509 #define CONFIG_CMD_PCI
510 #endif
511 
512 #if defined(CONFIG_SYS_RAMBOOT)
513 #undef CONFIG_CMD_SAVEENV
514 #undef CONFIG_CMD_LOADS
515 #endif
516 
517 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
518 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
519 
520 #undef CONFIG_WATCHDOG		/* watchdog disabled */
521 
522 #define CONFIG_MMC     1
523 
524 #ifdef CONFIG_MMC
525 #define CONFIG_FSL_ESDHC
526 #define CONFIG_FSL_ESDHC_PIN_MUX
527 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
528 #define CONFIG_CMD_MMC
529 #define CONFIG_GENERIC_MMC
530 #define CONFIG_CMD_EXT2
531 #define CONFIG_CMD_FAT
532 #define CONFIG_DOS_PARTITION
533 #endif
534 
535 /*
536  * Miscellaneous configurable options
537  */
538 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
539 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
540 
541 #if defined(CONFIG_CMD_KGDB)
542 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
543 #else
544 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
545 #endif
546 
547 				/* Print Buffer Size */
548 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
549 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
550 				/* Boot Argument Buffer Size */
551 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
552 
553 /*
554  * For booting Linux, the board info and command line data
555  * have to be in the first 256 MB of memory, since this is
556  * the maximum mapped by the Linux kernel during initialization.
557  */
558 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
559 
560 /*
561  * Core HID Setup
562  */
563 #define CONFIG_SYS_HID0_INIT	0x000000000
564 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
565 				| HID0_ENABLE_INSTRUCTION_CACHE)
566 #define CONFIG_SYS_HID2		HID2_HBE
567 
568 /*
569  * MMU Setup
570  */
571 
572 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
573 
574 /* DDR: cache cacheable */
575 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
576 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
577 
578 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
579 				| BATL_PP_RW \
580 				| BATL_MEMCOHERENCE)
581 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
582 				| BATU_BL_256M \
583 				| BATU_VS \
584 				| BATU_VP)
585 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
586 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
587 
588 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
589 				| BATL_PP_RW \
590 				| BATL_MEMCOHERENCE)
591 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
592 				| BATU_BL_256M \
593 				| BATU_VS \
594 				| BATU_VP)
595 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
596 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
597 
598 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
599 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
600 				| BATL_PP_RW \
601 				| BATL_CACHEINHIBIT \
602 				| BATL_GUARDEDSTORAGE)
603 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
604 				| BATU_BL_8M \
605 				| BATU_VS \
606 				| BATU_VP)
607 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
608 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
609 
610 /* L2 Switch: cache-inhibit and guarded */
611 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_VSC7385_BASE \
612 				| BATL_PP_RW \
613 				| BATL_CACHEINHIBIT \
614 				| BATL_GUARDEDSTORAGE)
615 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_VSC7385_BASE \
616 				| BATU_BL_128K \
617 				| BATU_VS \
618 				| BATU_VP)
619 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
620 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
621 
622 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
623 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
624 				| BATL_PP_RW \
625 				| BATL_MEMCOHERENCE)
626 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
627 				| BATU_BL_32M \
628 				| BATU_VS \
629 				| BATU_VP)
630 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
631 				| BATL_PP_RW \
632 				| BATL_CACHEINHIBIT \
633 				| BATL_GUARDEDSTORAGE)
634 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
635 
636 /* Stack in dcache: cacheable, no memory coherence */
637 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
638 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
639 				| BATU_BL_128K \
640 				| BATU_VS \
641 				| BATU_VP)
642 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
643 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
644 
645 #ifdef CONFIG_PCI
646 /* PCI MEM space: cacheable */
647 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
648 				| BATL_PP_RW \
649 				| BATL_MEMCOHERENCE)
650 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
651 				| BATU_BL_256M \
652 				| BATU_VS \
653 				| BATU_VP)
654 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
655 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
656 /* PCI MMIO space: cache-inhibit and guarded */
657 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
658 				| BATL_PP_RW \
659 				| BATL_CACHEINHIBIT \
660 				| BATL_GUARDEDSTORAGE)
661 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
662 				| BATU_BL_256M \
663 				| BATU_VS \
664 				| BATU_VP)
665 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
666 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
667 #else
668 #define CONFIG_SYS_IBAT6L	(0)
669 #define CONFIG_SYS_IBAT6U	(0)
670 #define CONFIG_SYS_IBAT7L	(0)
671 #define CONFIG_SYS_IBAT7U	(0)
672 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
673 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
674 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
675 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
676 #endif
677 
678 #if defined(CONFIG_CMD_KGDB)
679 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
680 #endif
681 
682 /*
683  * Environment Configuration
684  */
685 #define CONFIG_ENV_OVERWRITE
686 
687 #define CONFIG_HAS_FSL_DR_USB
688 #define CONFIG_CMD_USB
689 #define CONFIG_USB_STORAGE
690 #define CONFIG_USB_EHCI
691 #define CONFIG_USB_EHCI_FSL
692 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
693 
694 #define CONFIG_NETDEV		"eth1"
695 
696 #define CONFIG_HOSTNAME		mpc837x_rdb
697 #define CONFIG_ROOTPATH		"/nfsroot"
698 #define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
699 #define CONFIG_BOOTFILE		"uImage"
700 				/* U-Boot image on TFTP server */
701 #define CONFIG_UBOOTPATH	"u-boot.bin"
702 #define CONFIG_FDTFILE		"mpc8379_rdb.dtb"
703 
704 				/* default location for tftp and bootm */
705 #define CONFIG_LOADADDR		800000
706 #define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
707 #define CONFIG_BAUDRATE		115200
708 
709 #define CONFIG_EXTRA_ENV_SETTINGS \
710 	"netdev=" CONFIG_NETDEV "\0"				\
711 	"uboot=" CONFIG_UBOOTPATH "\0"					\
712 	"tftpflash=tftp $loadaddr $uboot;"				\
713 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
714 			" +$filesize; "	\
715 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
716 			" +$filesize; "	\
717 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
718 			" $filesize; "	\
719 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
720 			" +$filesize; "	\
721 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
722 			" $filesize\0"	\
723 	"fdtaddr=780000\0"						\
724 	"fdtfile=" CONFIG_FDTFILE "\0"					\
725 	"ramdiskaddr=1000000\0"						\
726 	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
727 	"console=ttyS0\0"						\
728 	"setbootargs=setenv bootargs "					\
729 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
730 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
731 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
732 							"$netdev:off "	\
733 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
734 
735 #define CONFIG_NFSBOOTCOMMAND						\
736 	"setenv rootdev /dev/nfs;"					\
737 	"run setbootargs;"						\
738 	"run setipargs;"						\
739 	"tftp $loadaddr $bootfile;"					\
740 	"tftp $fdtaddr $fdtfile;"					\
741 	"bootm $loadaddr - $fdtaddr"
742 
743 #define CONFIG_RAMBOOTCOMMAND						\
744 	"setenv rootdev /dev/ram;"					\
745 	"run setbootargs;"						\
746 	"tftp $ramdiskaddr $ramdiskfile;"				\
747 	"tftp $loadaddr $bootfile;"					\
748 	"tftp $fdtaddr $fdtfile;"					\
749 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
750 
751 #endif	/* __CONFIG_H */
752