1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #ifndef __CONFIG_H 22 #define __CONFIG_H 23 24 /* 25 * High Level Configuration Options 26 */ 27 #define CONFIG_E300 1 /* E300 family */ 28 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 29 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ 30 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 31 32 /* 33 * System Clock Setup 34 */ 35 #ifdef CONFIG_PCISLAVE 36 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 37 #else 38 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 39 #endif 40 41 #ifndef CONFIG_SYS_CLK_FREQ 42 #define CONFIG_SYS_CLK_FREQ 66000000 43 #endif 44 45 /* 46 * Hardware Reset Configuration Word 47 * if CLKIN is 66MHz, then 48 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 49 */ 50 #define CFG_HRCW_LOW (\ 51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 53 HRCWL_SVCOD_DIV_2 |\ 54 HRCWL_CSB_TO_CLKIN_6X1 |\ 55 HRCWL_CORE_TO_CSB_1_5X1) 56 57 #ifdef CONFIG_PCISLAVE 58 #define CFG_HRCW_HIGH (\ 59 HRCWH_PCI_AGENT |\ 60 HRCWH_PCI1_ARBITER_DISABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0XFFF00100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_RL_EXT_LEGACY |\ 67 HRCWH_TSEC1M_IN_RGMII |\ 68 HRCWH_TSEC2M_IN_RGMII |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LDP_CLEAR) 71 #else 72 #define CFG_HRCW_HIGH (\ 73 HRCWH_PCI_HOST |\ 74 HRCWH_PCI1_ARBITER_ENABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0X00000100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_RL_EXT_LEGACY |\ 81 HRCWH_TSEC1M_IN_RGMII |\ 82 HRCWH_TSEC2M_IN_RGMII |\ 83 HRCWH_BIG_ENDIAN |\ 84 HRCWH_LDP_CLEAR) 85 #endif 86 87 /* 88 * eTSEC Clock Config 89 */ 90 #define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 91 #define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 92 93 /* 94 * System IO Config 95 */ 96 #define CFG_SICRH 0x00000000 97 #define CFG_SICRL 0x00000000 98 99 /* 100 * Output Buffer Impedance 101 */ 102 #define CFG_OBIR 0x31100000 103 104 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 105 #define CONFIG_BOARD_EARLY_INIT_R 106 107 /* 108 * IMMR new address 109 */ 110 #define CFG_IMMR 0xE0000000 111 112 /* 113 * DDR Setup 114 */ 115 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 116 #define CFG_SDRAM_BASE CFG_DDR_BASE 117 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 118 #define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 119 #define CFG_83XX_DDR_USES_CS0 120 #define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ 121 122 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 123 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 124 125 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 126 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 127 128 #if defined(CONFIG_SPD_EEPROM) 129 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 130 #else 131 /* 132 * Manually set up DDR parameters 133 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 134 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 135 */ 136 #define CFG_DDR_SIZE 512 /* MB */ 137 #define CFG_DDR_CS0_BNDS 0x0000001f 138 #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ 139 | 0x00010000 /* ODT_WR to CSn */ \ 140 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) 141 /* 0x80010202 */ 142 #define CFG_DDR_TIMING_3 0x00000000 143 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 144 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 145 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 146 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 147 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 148 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 149 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 150 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 151 /* 0x00620802 */ 152 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 153 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 154 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 155 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 156 | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 157 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 158 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 159 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 160 /* 0x3935d322 */ 161 #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 162 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ 163 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 164 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 165 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 166 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 167 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 168 /* 0x131088c8 */ 169 #define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 170 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 171 /* 0x03E00100 */ 172 #define CFG_DDR_SDRAM_CFG 0x43000000 173 #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 174 #define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ 175 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) 176 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 177 #define CFG_DDR_MODE2 0x00000000 178 #endif 179 180 /* 181 * Memory test 182 */ 183 #undef CFG_DRAM_TEST /* memory test, takes time */ 184 #define CFG_MEMTEST_START 0x00040000 /* memtest region */ 185 #define CFG_MEMTEST_END 0x00140000 186 187 /* 188 * The reserved memory 189 */ 190 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 191 192 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 193 #define CFG_RAMBOOT 194 #else 195 #undef CFG_RAMBOOT 196 #endif 197 198 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 199 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 200 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 201 202 /* 203 * Initial RAM Base Address Setup 204 */ 205 #define CFG_INIT_RAM_LOCK 1 206 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 207 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 208 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 209 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 210 211 /* 212 * Local Bus Configuration & Clock Setup 213 */ 214 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 215 #define CFG_LBC_LBCR 0x00000000 216 217 /* 218 * FLASH on the Local Bus 219 */ 220 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 221 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 222 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 223 #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ 224 225 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 226 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 227 228 #define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ 229 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ 230 | BR_V ) /* valid */ 231 #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ 232 | OR_UPM_XAM \ 233 | OR_GPCM_CSNT \ 234 | OR_GPCM_ACS_0b11 \ 235 | OR_GPCM_XACS \ 236 | OR_GPCM_SCY_15 \ 237 | OR_GPCM_TRLX \ 238 | OR_GPCM_EHTR \ 239 | OR_GPCM_EAD ) 240 /* 0xFE000FF7 */ 241 242 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 243 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ 244 245 #undef CFG_FLASH_CHECKSUM 246 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 249 /* 250 * BCSR on the Local Bus 251 */ 252 #define CFG_BCSR 0xF8000000 253 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 254 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 255 256 #define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ 257 #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ 258 259 /* 260 * NAND Flash on the Local Bus 261 */ 262 #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ 263 #define CFG_BR3_PRELIM ( CFG_NAND_BASE \ 264 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 265 | BR_PS_8 /* Port Size = 8 bit */ \ 266 | BR_MS_FCM /* MSEL = FCM */ \ 267 | BR_V ) /* valid */ 268 #define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ 269 | OR_FCM_CSCT \ 270 | OR_FCM_CST \ 271 | OR_FCM_CHT \ 272 | OR_FCM_SCY_1 \ 273 | OR_FCM_TRLX \ 274 | OR_FCM_EHTR ) 275 /* 0xFFFF8396 */ 276 277 #define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE 278 #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 279 280 /* 281 * Serial Port 282 */ 283 #define CONFIG_CONS_INDEX 1 284 #undef CONFIG_SERIAL_SOFTWARE_FIFO 285 #define CFG_NS16550 286 #define CFG_NS16550_SERIAL 287 #define CFG_NS16550_REG_SIZE 1 288 #define CFG_NS16550_CLK get_bus_freq(0) 289 290 #define CFG_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 292 293 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 294 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 295 296 /* Use the HUSH parser */ 297 #define CFG_HUSH_PARSER 298 #ifdef CFG_HUSH_PARSER 299 #define CFG_PROMPT_HUSH_PS2 "> " 300 #endif 301 302 /* Pass open firmware flat tree */ 303 #define CONFIG_OF_LIBFDT 1 304 #define CONFIG_OF_BOARD_SETUP 1 305 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 306 307 /* I2C */ 308 #define CONFIG_HARD_I2C /* I2C with hardware support */ 309 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 310 #define CONFIG_FSL_I2C 311 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 312 #define CFG_I2C_SLAVE 0x7F 313 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 314 #define CFG_I2C_OFFSET 0x3000 315 #define CFG_I2C2_OFFSET 0x3100 316 317 /* 318 * Config on-board RTC 319 */ 320 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 321 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 322 323 /* 324 * General PCI 325 * Addresses are mapped 1-1. 326 */ 327 #define CFG_PCI_MEM_BASE 0x80000000 328 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE 329 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ 330 #define CFG_PCI_MMIO_BASE 0x90000000 331 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE 332 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ 333 #define CFG_PCI_IO_BASE 0xE0300000 334 #define CFG_PCI_IO_PHYS 0xE0300000 335 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ 336 337 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE 338 #define CFG_PCI_SLV_MEM_BUS 0x00000000 339 #define CFG_PCI_SLV_MEM_SIZE 0x80000000 340 341 #ifdef CONFIG_PCI 342 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ 343 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 344 345 #define CONFIG_NET_MULTI 346 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 347 348 #undef CONFIG_EEPRO100 349 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 350 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 351 #endif /* CONFIG_PCI */ 352 353 #ifndef CONFIG_NET_MULTI 354 #define CONFIG_NET_MULTI 1 355 #endif 356 357 /* 358 * TSEC 359 */ 360 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 361 #define CFG_TSEC1_OFFSET 0x24000 362 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 363 #define CFG_TSEC2_OFFSET 0x25000 364 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 365 366 /* 367 * TSEC ethernet configuration 368 */ 369 #define CONFIG_MII 1 /* MII PHY management */ 370 #define CONFIG_TSEC1 1 371 #define CONFIG_TSEC1_NAME "eTSEC0" 372 #define CONFIG_TSEC2 1 373 #define CONFIG_TSEC2_NAME "eTSEC1" 374 #define TSEC1_PHY_ADDR 2 375 #define TSEC2_PHY_ADDR 3 376 #define TSEC1_PHYIDX 0 377 #define TSEC2_PHYIDX 0 378 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 379 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 380 381 /* Options are: TSEC[0-1] */ 382 #define CONFIG_ETHPRIME "eTSEC1" 383 384 /* 385 * Environment 386 */ 387 #ifndef CFG_RAMBOOT 388 #define CFG_ENV_IS_IN_FLASH 1 389 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 390 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 391 #define CFG_ENV_SIZE 0x2000 392 #else 393 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 394 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 395 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 396 #define CFG_ENV_SIZE 0x2000 397 #endif 398 399 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 400 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 401 402 /* 403 * BOOTP options 404 */ 405 #define CONFIG_BOOTP_BOOTFILESIZE 406 #define CONFIG_BOOTP_BOOTPATH 407 #define CONFIG_BOOTP_GATEWAY 408 #define CONFIG_BOOTP_HOSTNAME 409 410 411 /* 412 * Command line configuration. 413 */ 414 #include <config_cmd_default.h> 415 416 #define CONFIG_CMD_PING 417 #define CONFIG_CMD_I2C 418 #define CONFIG_CMD_MII 419 #define CONFIG_CMD_DATE 420 421 #if defined(CONFIG_PCI) 422 #define CONFIG_CMD_PCI 423 #endif 424 425 #if defined(CFG_RAMBOOT) 426 #undef CONFIG_CMD_ENV 427 #undef CONFIG_CMD_LOADS 428 #endif 429 430 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 431 432 #undef CONFIG_WATCHDOG /* watchdog disabled */ 433 434 /* 435 * Miscellaneous configurable options 436 */ 437 #define CFG_LONGHELP /* undef to save memory */ 438 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 439 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 440 441 #if defined(CONFIG_CMD_KGDB) 442 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 443 #else 444 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 445 #endif 446 447 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 448 #define CFG_MAXARGS 16 /* max number of command args */ 449 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 450 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 451 452 /* 453 * For booting Linux, the board info and command line data 454 * have to be in the first 8 MB of memory, since this is 455 * the maximum mapped by the Linux kernel during initialization. 456 */ 457 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 458 459 /* 460 * Core HID Setup 461 */ 462 #define CFG_HID0_INIT 0x000000000 463 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 464 #define CFG_HID2 HID2_HBE 465 466 /* 467 * MMU Setup 468 */ 469 470 /* DDR: cache cacheable */ 471 #define CFG_SDRAM_LOWER CFG_SDRAM_BASE 472 #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) 473 474 #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 475 #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 476 #define CFG_DBAT0L CFG_IBAT0L 477 #define CFG_DBAT0U CFG_IBAT0U 478 479 #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 480 #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 481 #define CFG_DBAT1L CFG_IBAT1L 482 #define CFG_DBAT1U CFG_IBAT1U 483 484 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 485 #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ 486 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 487 #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 488 #define CFG_DBAT2L CFG_IBAT2L 489 #define CFG_DBAT2U CFG_IBAT2U 490 491 /* BCSR: cache-inhibit and guarded */ 492 #define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ 493 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 494 #define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) 495 #define CFG_DBAT3L CFG_IBAT3L 496 #define CFG_DBAT3U CFG_IBAT3U 497 498 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 499 #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 500 #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 501 #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ 502 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 503 #define CFG_DBAT4U CFG_IBAT4U 504 505 /* Stack in dcache: cacheable, no memory coherence */ 506 #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) 507 #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 508 #define CFG_DBAT5L CFG_IBAT5L 509 #define CFG_DBAT5U CFG_IBAT5U 510 511 #ifdef CONFIG_PCI 512 /* PCI MEM space: cacheable */ 513 #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 514 #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 515 #define CFG_DBAT6L CFG_IBAT6L 516 #define CFG_DBAT6U CFG_IBAT6U 517 /* PCI MMIO space: cache-inhibit and guarded */ 518 #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ 519 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 520 #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 521 #define CFG_DBAT7L CFG_IBAT7L 522 #define CFG_DBAT7U CFG_IBAT7U 523 #else 524 #define CFG_IBAT6L (0) 525 #define CFG_IBAT6U (0) 526 #define CFG_IBAT7L (0) 527 #define CFG_IBAT7U (0) 528 #define CFG_DBAT6L CFG_IBAT6L 529 #define CFG_DBAT6U CFG_IBAT6U 530 #define CFG_DBAT7L CFG_IBAT7L 531 #define CFG_DBAT7U CFG_IBAT7U 532 #endif 533 534 /* 535 * Internal Definitions 536 * 537 * Boot Flags 538 */ 539 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 540 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 541 542 #if defined(CONFIG_CMD_KGDB) 543 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 544 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 545 #endif 546 547 /* 548 * Environment Configuration 549 */ 550 551 #define CONFIG_ENV_OVERWRITE 552 553 #if defined(CONFIG_TSEC_ENET) 554 #define CONFIG_HAS_ETH0 555 #define CONFIG_ETHADDR 00:E0:0C:00:83:79 556 #define CONFIG_HAS_ETH1 557 #define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 558 #endif 559 560 #define CONFIG_BAUDRATE 115200 561 562 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 563 564 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 565 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 566 567 #define CONFIG_EXTRA_ENV_SETTINGS \ 568 "netdev=eth0\0" \ 569 "consoledev=ttyS0\0" \ 570 "ramdiskaddr=1000000\0" \ 571 "ramdiskfile=ramfs.83xx\0" \ 572 "fdtaddr=400000\0" \ 573 "fdtfile=mpc837xemds.dtb\0" \ 574 "" 575 576 #define CONFIG_NFSBOOTCOMMAND \ 577 "setenv bootargs root=/dev/nfs rw " \ 578 "nfsroot=$serverip:$rootpath " \ 579 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 580 "console=$consoledev,$baudrate $othbootargs;" \ 581 "tftp $loadaddr $bootfile;" \ 582 "tftp $fdtaddr $fdtfile;" \ 583 "bootm $loadaddr - $fdtaddr" 584 585 #define CONFIG_RAMBOOTCOMMAND \ 586 "setenv bootargs root=/dev/ram rw " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "tftp $ramdiskaddr $ramdiskfile;" \ 589 "tftp $loadaddr $bootfile;" \ 590 "tftp $fdtaddr $fdtfile;" \ 591 "bootm $loadaddr $ramdiskaddr $fdtaddr" 592 593 594 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 595 596 #endif /* __CONFIG_H */ 597