1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2007 Freescale Semiconductor, Inc. 4 * Dave Liu <daveliu@freescale.com> 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * High Level Configuration Options 12 */ 13 #define CONFIG_E300 1 /* E300 family */ 14 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 15 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 16 17 /* 18 * System Clock Setup 19 */ 20 #ifdef CONFIG_PCISLAVE 21 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 22 #else 23 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 24 #endif 25 26 #ifndef CONFIG_SYS_CLK_FREQ 27 #define CONFIG_SYS_CLK_FREQ 66000000 28 #endif 29 30 /* 31 * Hardware Reset Configuration Word 32 * if CLKIN is 66MHz, then 33 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 34 */ 35 #define CONFIG_SYS_HRCW_LOW (\ 36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 37 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 38 HRCWL_SVCOD_DIV_2 |\ 39 HRCWL_CSB_TO_CLKIN_6X1 |\ 40 HRCWL_CORE_TO_CSB_1_5X1) 41 42 #ifdef CONFIG_PCISLAVE 43 #define CONFIG_SYS_HRCW_HIGH (\ 44 HRCWH_PCI_AGENT |\ 45 HRCWH_PCI1_ARBITER_DISABLE |\ 46 HRCWH_CORE_ENABLE |\ 47 HRCWH_FROM_0XFFF00100 |\ 48 HRCWH_BOOTSEQ_DISABLE |\ 49 HRCWH_SW_WATCHDOG_DISABLE |\ 50 HRCWH_ROM_LOC_LOCAL_16BIT |\ 51 HRCWH_RL_EXT_LEGACY |\ 52 HRCWH_TSEC1M_IN_RGMII |\ 53 HRCWH_TSEC2M_IN_RGMII |\ 54 HRCWH_BIG_ENDIAN |\ 55 HRCWH_LDP_CLEAR) 56 #else 57 #define CONFIG_SYS_HRCW_HIGH (\ 58 HRCWH_PCI_HOST |\ 59 HRCWH_PCI1_ARBITER_ENABLE |\ 60 HRCWH_CORE_ENABLE |\ 61 HRCWH_FROM_0X00000100 |\ 62 HRCWH_BOOTSEQ_DISABLE |\ 63 HRCWH_SW_WATCHDOG_DISABLE |\ 64 HRCWH_ROM_LOC_LOCAL_16BIT |\ 65 HRCWH_RL_EXT_LEGACY |\ 66 HRCWH_TSEC1M_IN_RGMII |\ 67 HRCWH_TSEC2M_IN_RGMII |\ 68 HRCWH_BIG_ENDIAN |\ 69 HRCWH_LDP_CLEAR) 70 #endif 71 72 /* Arbiter Configuration Register */ 73 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 74 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 75 76 /* System Priority Control Register */ 77 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 78 79 /* 80 * IP blocks clock configuration 81 */ 82 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 83 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 84 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 85 86 /* 87 * System IO Config 88 */ 89 #define CONFIG_SYS_SICRH 0x00000000 90 #define CONFIG_SYS_SICRL 0x00000000 91 92 /* 93 * Output Buffer Impedance 94 */ 95 #define CONFIG_SYS_OBIR 0x31100000 96 97 #define CONFIG_HWCONFIG 98 99 /* 100 * IMMR new address 101 */ 102 #define CONFIG_SYS_IMMR 0xE0000000 103 104 /* 105 * DDR Setup 106 */ 107 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 109 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 111 #define CONFIG_SYS_83XX_DDR_USES_CS0 112 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 113 | DDRCDR_ODT \ 114 | DDRCDR_Q_DRN) 115 /* 0x80080001 */ /* ODT 150ohm on SoC */ 116 117 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 118 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 119 120 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 121 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 122 123 #if defined(CONFIG_SPD_EEPROM) 124 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 125 #else 126 /* 127 * Manually set up DDR parameters 128 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 129 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 130 */ 131 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 133 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 134 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 135 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 136 | CSCONFIG_ROW_BIT_14 \ 137 | CSCONFIG_COL_BIT_10) 138 /* 0x80010202 */ 139 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 141 | (0 << TIMING_CFG0_WRT_SHIFT) \ 142 | (0 << TIMING_CFG0_RRT_SHIFT) \ 143 | (0 << TIMING_CFG0_WWT_SHIFT) \ 144 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 145 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 146 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 147 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 148 /* 0x00620802 */ 149 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 150 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 151 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 152 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 153 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 154 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 156 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 157 /* 0x3935d322 */ 158 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 159 | (6 << TIMING_CFG2_CPO_SHIFT) \ 160 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 161 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 162 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 163 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 164 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 165 /* 0x131088c8 */ 166 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 167 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 168 /* 0x03E00100 */ 169 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 170 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 171 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 172 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 173 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 174 #define CONFIG_SYS_DDR_MODE2 0x00000000 175 #endif 176 177 /* 178 * Memory test 179 */ 180 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 181 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 182 #define CONFIG_SYS_MEMTEST_END 0x00140000 183 184 /* 185 * The reserved memory 186 */ 187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 188 189 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 190 #define CONFIG_SYS_RAMBOOT 191 #else 192 #undef CONFIG_SYS_RAMBOOT 193 #endif 194 195 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 196 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 197 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 198 199 /* 200 * Initial RAM Base Address Setup 201 */ 202 #define CONFIG_SYS_INIT_RAM_LOCK 1 203 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 204 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 205 #define CONFIG_SYS_GBL_DATA_OFFSET \ 206 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 207 208 /* 209 * Local Bus Configuration & Clock Setup 210 */ 211 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 212 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 213 #define CONFIG_SYS_LBC_LBCR 0x00000000 214 #define CONFIG_FSL_ELBC 1 215 216 /* 217 * FLASH on the Local Bus 218 */ 219 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 220 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 221 222 /* Window base at flash base */ 223 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 224 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 225 226 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 227 | BR_PS_16 /* 16 bit port */ \ 228 | BR_MS_GPCM /* MSEL = GPCM */ \ 229 | BR_V) /* valid */ 230 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 231 | OR_UPM_XAM \ 232 | OR_GPCM_CSNT \ 233 | OR_GPCM_ACS_DIV2 \ 234 | OR_GPCM_XACS \ 235 | OR_GPCM_SCY_15 \ 236 | OR_GPCM_TRLX_SET \ 237 | OR_GPCM_EHTR_SET \ 238 | OR_GPCM_EAD) 239 /* 0xFE000FF7 */ 240 241 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 242 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 243 244 #undef CONFIG_SYS_FLASH_CHECKSUM 245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 247 248 /* 249 * BCSR on the Local Bus 250 */ 251 #define CONFIG_SYS_BCSR 0xF8000000 252 /* Access window base at BCSR base */ 253 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 254 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 255 256 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 257 | BR_PS_8 \ 258 | BR_MS_GPCM \ 259 | BR_V) 260 /* 0xF8000801 */ 261 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 262 | OR_GPCM_XAM \ 263 | OR_GPCM_CSNT \ 264 | OR_GPCM_XACS \ 265 | OR_GPCM_SCY_15 \ 266 | OR_GPCM_TRLX_SET \ 267 | OR_GPCM_EHTR_SET \ 268 | OR_GPCM_EAD) 269 /* 0xFFFFE9F7 */ 270 271 /* 272 * NAND Flash on the Local Bus 273 */ 274 #define CONFIG_SYS_MAX_NAND_DEVICE 1 275 #define CONFIG_NAND_FSL_ELBC 1 276 277 #define CONFIG_SYS_NAND_BASE 0xE0600000 278 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 279 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 280 | BR_PS_8 /* 8 bit port */ \ 281 | BR_MS_FCM /* MSEL = FCM */ \ 282 | BR_V) /* valid */ 283 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 284 | OR_FCM_BCTLD \ 285 | OR_FCM_CST \ 286 | OR_FCM_CHT \ 287 | OR_FCM_SCY_1 \ 288 | OR_FCM_RST \ 289 | OR_FCM_TRLX \ 290 | OR_FCM_EHTR) 291 /* 0xFFFF919E */ 292 293 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 294 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 295 296 /* 297 * Serial Port 298 */ 299 #define CONFIG_SYS_NS16550_SERIAL 300 #define CONFIG_SYS_NS16550_REG_SIZE 1 301 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 302 303 #define CONFIG_SYS_BAUDRATE_TABLE \ 304 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 305 306 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 307 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 308 309 /* I2C */ 310 #define CONFIG_SYS_I2C 311 #define CONFIG_SYS_I2C_FSL 312 #define CONFIG_SYS_FSL_I2C_SPEED 400000 313 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 314 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 315 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 316 317 /* 318 * Config on-board RTC 319 */ 320 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 321 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 322 323 /* 324 * General PCI 325 * Addresses are mapped 1-1. 326 */ 327 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 328 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 329 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 330 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 331 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 332 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 333 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 334 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 335 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 336 337 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 338 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 339 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 340 341 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 342 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 343 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 344 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 345 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 346 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 347 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 348 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 349 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 350 351 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 352 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 353 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 354 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 355 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 356 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 357 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 358 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 359 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 360 361 #ifdef CONFIG_PCI 362 #define CONFIG_PCI_INDIRECT_BRIDGE 363 #ifndef __ASSEMBLY__ 364 extern int board_pci_host_broken(void); 365 #endif 366 #define CONFIG_PCIE 367 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 368 369 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 370 #define CONFIG_USB_EHCI_FSL 371 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 372 373 #undef CONFIG_EEPRO100 374 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 376 #endif /* CONFIG_PCI */ 377 378 /* 379 * TSEC 380 */ 381 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 382 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 383 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 384 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 385 386 /* 387 * TSEC ethernet configuration 388 */ 389 #define CONFIG_TSEC1 1 390 #define CONFIG_TSEC1_NAME "eTSEC0" 391 #define CONFIG_TSEC2 1 392 #define CONFIG_TSEC2_NAME "eTSEC1" 393 #define TSEC1_PHY_ADDR 2 394 #define TSEC2_PHY_ADDR 3 395 #define TSEC1_PHY_ADDR_SGMII 8 396 #define TSEC2_PHY_ADDR_SGMII 4 397 #define TSEC1_PHYIDX 0 398 #define TSEC2_PHYIDX 0 399 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 400 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 401 402 /* Options are: TSEC[0-1] */ 403 #define CONFIG_ETHPRIME "eTSEC1" 404 405 /* SERDES */ 406 #define CONFIG_FSL_SERDES 407 #define CONFIG_FSL_SERDES1 0xe3000 408 #define CONFIG_FSL_SERDES2 0xe3100 409 410 /* 411 * SATA 412 */ 413 #define CONFIG_SYS_SATA_MAX_DEVICE 2 414 #define CONFIG_SATA1 415 #define CONFIG_SYS_SATA1_OFFSET 0x18000 416 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 417 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 418 #define CONFIG_SATA2 419 #define CONFIG_SYS_SATA2_OFFSET 0x19000 420 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 421 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 422 423 #ifdef CONFIG_FSL_SATA 424 #define CONFIG_LBA48 425 #endif 426 427 /* 428 * Environment 429 */ 430 #ifndef CONFIG_SYS_RAMBOOT 431 #define CONFIG_ENV_ADDR \ 432 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 433 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 434 #define CONFIG_ENV_SIZE 0x2000 435 #else 436 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 437 #define CONFIG_ENV_SIZE 0x2000 438 #endif 439 440 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 441 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 442 443 /* 444 * BOOTP options 445 */ 446 #define CONFIG_BOOTP_BOOTFILESIZE 447 448 /* 449 * Command line configuration. 450 */ 451 452 #undef CONFIG_WATCHDOG /* watchdog disabled */ 453 454 #ifdef CONFIG_MMC 455 #define CONFIG_FSL_ESDHC_PIN_MUX 456 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 457 #endif 458 459 /* 460 * Miscellaneous configurable options 461 */ 462 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 463 464 /* 465 * For booting Linux, the board info and command line data 466 * have to be in the first 256 MB of memory, since this is 467 * the maximum mapped by the Linux kernel during initialization. 468 */ 469 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 470 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 471 472 /* 473 * Core HID Setup 474 */ 475 #define CONFIG_SYS_HID0_INIT 0x000000000 476 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 477 HID0_ENABLE_INSTRUCTION_CACHE) 478 #define CONFIG_SYS_HID2 HID2_HBE 479 480 /* 481 * MMU Setup 482 */ 483 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 484 485 /* DDR: cache cacheable */ 486 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 487 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 488 489 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 490 | BATL_PP_RW \ 491 | BATL_MEMCOHERENCE) 492 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 493 | BATU_BL_256M \ 494 | BATU_VS \ 495 | BATU_VP) 496 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 497 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 498 499 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 500 | BATL_PP_RW \ 501 | BATL_MEMCOHERENCE) 502 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 503 | BATU_BL_256M \ 504 | BATU_VS \ 505 | BATU_VP) 506 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 507 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 508 509 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 510 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 511 | BATL_PP_RW \ 512 | BATL_CACHEINHIBIT \ 513 | BATL_GUARDEDSTORAGE) 514 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 515 | BATU_BL_8M \ 516 | BATU_VS \ 517 | BATU_VP) 518 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 519 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 520 521 /* BCSR: cache-inhibit and guarded */ 522 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 523 | BATL_PP_RW \ 524 | BATL_CACHEINHIBIT \ 525 | BATL_GUARDEDSTORAGE) 526 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 527 | BATU_BL_128K \ 528 | BATU_VS \ 529 | BATU_VP) 530 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 531 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 532 533 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 534 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 535 | BATL_PP_RW \ 536 | BATL_MEMCOHERENCE) 537 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 538 | BATU_BL_32M \ 539 | BATU_VS \ 540 | BATU_VP) 541 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 542 | BATL_PP_RW \ 543 | BATL_CACHEINHIBIT \ 544 | BATL_GUARDEDSTORAGE) 545 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 546 547 /* Stack in dcache: cacheable, no memory coherence */ 548 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 549 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 550 | BATU_BL_128K \ 551 | BATU_VS \ 552 | BATU_VP) 553 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 554 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 555 556 #ifdef CONFIG_PCI 557 /* PCI MEM space: cacheable */ 558 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 559 | BATL_PP_RW \ 560 | BATL_MEMCOHERENCE) 561 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 562 | BATU_BL_256M \ 563 | BATU_VS \ 564 | BATU_VP) 565 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 566 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 567 /* PCI MMIO space: cache-inhibit and guarded */ 568 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 569 | BATL_PP_RW \ 570 | BATL_CACHEINHIBIT \ 571 | BATL_GUARDEDSTORAGE) 572 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 573 | BATU_BL_256M \ 574 | BATU_VS \ 575 | BATU_VP) 576 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 577 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 578 #else 579 #define CONFIG_SYS_IBAT6L (0) 580 #define CONFIG_SYS_IBAT6U (0) 581 #define CONFIG_SYS_IBAT7L (0) 582 #define CONFIG_SYS_IBAT7U (0) 583 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 584 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 585 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 586 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 587 #endif 588 589 #if defined(CONFIG_CMD_KGDB) 590 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 591 #endif 592 593 /* 594 * Environment Configuration 595 */ 596 597 #define CONFIG_ENV_OVERWRITE 598 599 #if defined(CONFIG_TSEC_ENET) 600 #define CONFIG_HAS_ETH0 601 #define CONFIG_HAS_ETH1 602 #endif 603 604 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 605 606 #define CONFIG_EXTRA_ENV_SETTINGS \ 607 "netdev=eth0\0" \ 608 "consoledev=ttyS0\0" \ 609 "ramdiskaddr=1000000\0" \ 610 "ramdiskfile=ramfs.83xx\0" \ 611 "fdtaddr=780000\0" \ 612 "fdtfile=mpc8379_mds.dtb\0" \ 613 "" 614 615 #define CONFIG_NFSBOOTCOMMAND \ 616 "setenv bootargs root=/dev/nfs rw " \ 617 "nfsroot=$serverip:$rootpath " \ 618 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 619 "$netdev:off " \ 620 "console=$consoledev,$baudrate $othbootargs;" \ 621 "tftp $loadaddr $bootfile;" \ 622 "tftp $fdtaddr $fdtfile;" \ 623 "bootm $loadaddr - $fdtaddr" 624 625 #define CONFIG_RAMBOOTCOMMAND \ 626 "setenv bootargs root=/dev/ram rw " \ 627 "console=$consoledev,$baudrate $othbootargs;" \ 628 "tftp $ramdiskaddr $ramdiskfile;" \ 629 "tftp $loadaddr $bootfile;" \ 630 "tftp $fdtaddr $fdtfile;" \ 631 "bootm $loadaddr $ramdiskaddr $fdtaddr" 632 633 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 634 635 #endif /* __CONFIG_H */ 636