1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Dave Liu <daveliu@freescale.com>
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License as
7  * published by the Free Software Foundation; either version 2 of
8  * the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18  * MA 02111-1307 USA
19  */
20 
21 #ifndef __CONFIG_H
22 #define __CONFIG_H
23 
24 /*
25  * High Level Configuration Options
26  */
27 #define CONFIG_E300		1 /* E300 family */
28 #define CONFIG_MPC83xx		1 /* MPC83xx family */
29 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
30 #define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
31 
32 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
33 
34 /*
35  * System Clock Setup
36  */
37 #ifdef CONFIG_PCISLAVE
38 #define CONFIG_83XX_PCICLK	66000000 /* in HZ */
39 #else
40 #define CONFIG_83XX_CLKIN	66000000 /* in Hz */
41 #endif
42 
43 #ifndef CONFIG_SYS_CLK_FREQ
44 #define CONFIG_SYS_CLK_FREQ	66000000
45 #endif
46 
47 /*
48  * Hardware Reset Configuration Word
49  * if CLKIN is 66MHz, then
50  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
51  */
52 #define CONFIG_SYS_HRCW_LOW (\
53 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 	HRCWL_SVCOD_DIV_2 |\
56 	HRCWL_CSB_TO_CLKIN_6X1 |\
57 	HRCWL_CORE_TO_CSB_1_5X1)
58 
59 #ifdef CONFIG_PCISLAVE
60 #define CONFIG_SYS_HRCW_HIGH (\
61 	HRCWH_PCI_AGENT |\
62 	HRCWH_PCI1_ARBITER_DISABLE |\
63 	HRCWH_CORE_ENABLE |\
64 	HRCWH_FROM_0XFFF00100 |\
65 	HRCWH_BOOTSEQ_DISABLE |\
66 	HRCWH_SW_WATCHDOG_DISABLE |\
67 	HRCWH_ROM_LOC_LOCAL_16BIT |\
68 	HRCWH_RL_EXT_LEGACY |\
69 	HRCWH_TSEC1M_IN_RGMII |\
70 	HRCWH_TSEC2M_IN_RGMII |\
71 	HRCWH_BIG_ENDIAN |\
72 	HRCWH_LDP_CLEAR)
73 #else
74 #define CONFIG_SYS_HRCW_HIGH (\
75 	HRCWH_PCI_HOST |\
76 	HRCWH_PCI1_ARBITER_ENABLE |\
77 	HRCWH_CORE_ENABLE |\
78 	HRCWH_FROM_0X00000100 |\
79 	HRCWH_BOOTSEQ_DISABLE |\
80 	HRCWH_SW_WATCHDOG_DISABLE |\
81 	HRCWH_ROM_LOC_LOCAL_16BIT |\
82 	HRCWH_RL_EXT_LEGACY |\
83 	HRCWH_TSEC1M_IN_RGMII |\
84 	HRCWH_TSEC2M_IN_RGMII |\
85 	HRCWH_BIG_ENDIAN |\
86 	HRCWH_LDP_CLEAR)
87 #endif
88 
89 /* Arbiter Configuration Register */
90 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
91 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count is 4 */
92 
93 /* System Priority Control Register */
94 #define CONFIG_SYS_SPCR_TSECEP		3	/* eTSEC1/2 emergency has highest priority */
95 
96 /*
97  * IP blocks clock configuration
98  */
99 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
100 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
101 #define CONFIG_SYS_SCCR_SATACM		SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
102 
103 /*
104  * System IO Config
105  */
106 #define CONFIG_SYS_SICRH		0x00000000
107 #define CONFIG_SYS_SICRL		0x00000000
108 
109 /*
110  * Output Buffer Impedance
111  */
112 #define CONFIG_SYS_OBIR		0x31100000
113 
114 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
115 #define CONFIG_BOARD_EARLY_INIT_R
116 #define CONFIG_HWCONFIG
117 
118 /*
119  * IMMR new address
120  */
121 #define CONFIG_SYS_IMMR		0xE0000000
122 
123 /*
124  * DDR Setup
125  */
126 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
127 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
128 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
129 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
130 #define CONFIG_SYS_83XX_DDR_USES_CS0
131 #define CONFIG_SYS_DDRCDR_VALUE	0x80080001 /* ODT 150ohm on SoC */
132 
133 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
134 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
135 
136 #define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
137 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
138 
139 #if defined(CONFIG_SPD_EEPROM)
140 #define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
141 #else
142 /*
143  * Manually set up DDR parameters
144  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
145  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
146  */
147 #define CONFIG_SYS_DDR_SIZE		512 /* MB */
148 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
149 #define CONFIG_SYS_DDR_CS0_CONFIG	( CSCONFIG_EN \
150 				| 0x00010000  /* ODT_WR to CSn */ \
151 				| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
152 				/* 0x80010202 */
153 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
154 #define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
155 				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
156 				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
157 				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
158 				| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
159 				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
160 				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
161 				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
162 				/* 0x00620802 */
163 #define CONFIG_SYS_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
164 				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
165 				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
166 				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
167 				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
168 				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
169 				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
170 				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
171 				/* 0x3935d322 */
172 #define CONFIG_SYS_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
173 				| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
174 				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
175 				| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
176 				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
177 				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
178 				| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
179 				/* 0x131088c8 */
180 #define CONFIG_SYS_DDR_INTERVAL	( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
181 				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
182 				/* 0x03E00100 */
183 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
184 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
185 #define CONFIG_SYS_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
186 				| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
187 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
188 #define CONFIG_SYS_DDR_MODE2		0x00000000
189 #endif
190 
191 /*
192  * Memory test
193  */
194 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
195 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
196 #define CONFIG_SYS_MEMTEST_END		0x00140000
197 
198 /*
199  * The reserved memory
200  */
201 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
202 
203 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
204 #define CONFIG_SYS_RAMBOOT
205 #else
206 #undef CONFIG_SYS_RAMBOOT
207 #endif
208 
209 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
210 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
211 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */
212 
213 /*
214  * Initial RAM Base Address Setup
215  */
216 #define CONFIG_SYS_INIT_RAM_LOCK	1
217 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
218 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
219 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220 
221 /*
222  * Local Bus Configuration & Clock Setup
223  */
224 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
225 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
226 #define CONFIG_SYS_LBC_LBCR		0x00000000
227 #define CONFIG_FSL_ELBC		1
228 
229 /*
230  * FLASH on the Local Bus
231  */
232 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
233 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
234 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
235 #define CONFIG_SYS_FLASH_SIZE		32 /* max FLASH size is 32M */
236 #define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
237 
238 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
239 #define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
240 
241 #define CONFIG_SYS_BR0_PRELIM		( CONFIG_SYS_FLASH_BASE	/* Flash Base address */ \
242 				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
243 				| BR_V )		/* valid */
244 #define CONFIG_SYS_OR0_PRELIM		( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
245 				| OR_UPM_XAM \
246 				| OR_GPCM_CSNT \
247 				| OR_GPCM_ACS_DIV2 \
248 				| OR_GPCM_XACS \
249 				| OR_GPCM_SCY_15 \
250 				| OR_GPCM_TRLX \
251 				| OR_GPCM_EHTR \
252 				| OR_GPCM_EAD )
253 				/* 0xFE000FF7 */
254 
255 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
256 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
257 
258 #undef CONFIG_SYS_FLASH_CHECKSUM
259 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
260 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
261 
262 /*
263  * BCSR on the Local Bus
264  */
265 #define CONFIG_SYS_BCSR		0xF8000000
266 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR /* Access window base at BCSR base */
267 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */
268 
269 #define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
270 #define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
271 
272 /*
273  * NAND Flash on the Local Bus
274  */
275 #define CONFIG_CMD_NAND		1
276 #define CONFIG_MTD_NAND_VERIFY_WRITE	1
277 #define CONFIG_SYS_MAX_NAND_DEVICE	1
278 #define CONFIG_NAND_FSL_ELBC 	1
279 
280 #define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
281 #define CONFIG_SYS_BR3_PRELIM		( CONFIG_SYS_NAND_BASE \
282 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
283 				| BR_PS_8		/* Port Size = 8 bit */ \
284 				| BR_MS_FCM		/* MSEL = FCM */ \
285 				| BR_V )		/* valid */
286 #define CONFIG_SYS_OR3_PRELIM		( 0xFFFF8000		/* length 32K */ \
287 				| OR_FCM_BCTLD \
288 				| OR_FCM_CST \
289 				| OR_FCM_CHT \
290 				| OR_FCM_SCY_1 \
291 				| OR_FCM_RST \
292 				| OR_FCM_TRLX \
293 				| OR_FCM_EHTR )
294 				/* 0xFFFF919E */
295 
296 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_NAND_BASE
297 #define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
298 
299 /*
300  * Serial Port
301  */
302 #define CONFIG_CONS_INDEX	1
303 #define CONFIG_SYS_NS16550
304 #define CONFIG_SYS_NS16550_SERIAL
305 #define CONFIG_SYS_NS16550_REG_SIZE	1
306 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
307 
308 #define CONFIG_SYS_BAUDRATE_TABLE  \
309 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
310 
311 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
312 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
313 
314 /* Use the HUSH parser */
315 #define CONFIG_SYS_HUSH_PARSER
316 #ifdef CONFIG_SYS_HUSH_PARSER
317 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
318 #endif
319 
320 /* Pass open firmware flat tree */
321 #define CONFIG_OF_LIBFDT	1
322 #define CONFIG_OF_BOARD_SETUP	1
323 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
324 
325 /* I2C */
326 #define CONFIG_HARD_I2C		/* I2C with hardware support */
327 #undef CONFIG_SOFT_I2C		/* I2C bit-banged */
328 #define CONFIG_FSL_I2C
329 #define CONFIG_SYS_I2C_SPEED		400000 /* I2C speed and slave address */
330 #define CONFIG_SYS_I2C_SLAVE		0x7F
331 #define CONFIG_SYS_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
332 #define CONFIG_SYS_I2C_OFFSET		0x3000
333 #define CONFIG_SYS_I2C2_OFFSET		0x3100
334 
335 /*
336  * Config on-board RTC
337  */
338 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
339 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
340 
341 /*
342  * General PCI
343  * Addresses are mapped 1-1.
344  */
345 #define CONFIG_SYS_PCI_MEM_BASE	0x80000000
346 #define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
347 #define CONFIG_SYS_PCI_MEM_SIZE	0x10000000 /* 256M */
348 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
349 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
350 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
351 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
352 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
353 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
354 
355 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
356 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
357 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
358 
359 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
360 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
361 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
362 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
363 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
364 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
365 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
366 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
367 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
368 
369 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
370 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
371 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
372 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
373 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
374 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
375 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
376 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
377 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
378 
379 #ifdef CONFIG_PCI
380 #ifndef __ASSEMBLY__
381 extern int board_pci_host_broken(void);
382 #endif
383 #define CONFIG_PCIE
384 #define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
385 
386 #define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
387 
388 #define CONFIG_NET_MULTI
389 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
390 
391 #undef CONFIG_EEPRO100
392 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
393 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
394 #endif /* CONFIG_PCI */
395 
396 #ifndef CONFIG_NET_MULTI
397 #define CONFIG_NET_MULTI	1
398 #endif
399 
400 /*
401  * TSEC
402  */
403 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
404 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
405 #define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
406 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
407 #define CONFIG_SYS_TSEC2		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
408 
409 /*
410  * TSEC ethernet configuration
411  */
412 #define CONFIG_MII		1 /* MII PHY management */
413 #define CONFIG_TSEC1		1
414 #define CONFIG_TSEC1_NAME	"eTSEC0"
415 #define CONFIG_TSEC2		1
416 #define CONFIG_TSEC2_NAME	"eTSEC1"
417 #define TSEC1_PHY_ADDR		2
418 #define TSEC2_PHY_ADDR		3
419 #define TSEC1_PHY_ADDR_SGMII	8
420 #define TSEC2_PHY_ADDR_SGMII	4
421 #define TSEC1_PHYIDX		0
422 #define TSEC2_PHYIDX		0
423 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
424 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
425 
426 /* Options are: TSEC[0-1] */
427 #define CONFIG_ETHPRIME		"eTSEC1"
428 
429 /* SERDES */
430 #define CONFIG_FSL_SERDES
431 #define CONFIG_FSL_SERDES1	0xe3000
432 #define CONFIG_FSL_SERDES2	0xe3100
433 
434 /*
435  * SATA
436  */
437 #define CONFIG_LIBATA
438 #define CONFIG_FSL_SATA
439 
440 #define CONFIG_SYS_SATA_MAX_DEVICE	2
441 #define CONFIG_SATA1
442 #define CONFIG_SYS_SATA1_OFFSET	0x18000
443 #define CONFIG_SYS_SATA1		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
444 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
445 #define CONFIG_SATA2
446 #define CONFIG_SYS_SATA2_OFFSET	0x19000
447 #define CONFIG_SYS_SATA2		(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
448 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
449 
450 #ifdef CONFIG_FSL_SATA
451 #define CONFIG_LBA48
452 #define CONFIG_CMD_SATA
453 #define CONFIG_DOS_PARTITION
454 #define CONFIG_CMD_EXT2
455 #endif
456 
457 /*
458  * Environment
459  */
460 #ifndef CONFIG_SYS_RAMBOOT
461 	#define CONFIG_ENV_IS_IN_FLASH	1
462 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
463 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
464 	#define CONFIG_ENV_SIZE		0x2000
465 #else
466 	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
467 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
468 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
469 	#define CONFIG_ENV_SIZE		0x2000
470 #endif
471 
472 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
473 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
474 
475 /*
476  * BOOTP options
477  */
478 #define CONFIG_BOOTP_BOOTFILESIZE
479 #define CONFIG_BOOTP_BOOTPATH
480 #define CONFIG_BOOTP_GATEWAY
481 #define CONFIG_BOOTP_HOSTNAME
482 
483 
484 /*
485  * Command line configuration.
486  */
487 #include <config_cmd_default.h>
488 
489 #define CONFIG_CMD_PING
490 #define CONFIG_CMD_I2C
491 #define CONFIG_CMD_MII
492 #define CONFIG_CMD_DATE
493 
494 #if defined(CONFIG_PCI)
495     #define CONFIG_CMD_PCI
496 #endif
497 
498 #if defined(CONFIG_SYS_RAMBOOT)
499     #undef CONFIG_CMD_SAVEENV
500     #undef CONFIG_CMD_LOADS
501 #endif
502 
503 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
504 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
505 
506 #undef CONFIG_WATCHDOG		/* watchdog disabled */
507 
508 #define CONFIG_MMC     1
509 
510 #ifdef CONFIG_MMC
511 #define CONFIG_FSL_ESDHC
512 #define CONFIG_FSL_ESDHC_PIN_MUX
513 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
514 #define CONFIG_CMD_MMC
515 #define CONFIG_GENERIC_MMC
516 #define CONFIG_CMD_EXT2
517 #define CONFIG_CMD_FAT
518 #define CONFIG_DOS_PARTITION
519 #endif
520 
521 /*
522  * Miscellaneous configurable options
523  */
524 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
525 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
526 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
527 
528 #if defined(CONFIG_CMD_KGDB)
529 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
530 #else
531 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
532 #endif
533 
534 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
535 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
536 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
537 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
538 
539 /*
540  * For booting Linux, the board info and command line data
541  * have to be in the first 256 MB of memory, since this is
542  * the maximum mapped by the Linux kernel during initialization.
543  */
544 #define CONFIG_SYS_BOOTMAPSZ		(256 << 20) /* Initial Memory map for Linux */
545 
546 /*
547  * Core HID Setup
548  */
549 #define CONFIG_SYS_HID0_INIT	0x000000000
550 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
551 				 HID0_ENABLE_INSTRUCTION_CACHE)
552 #define CONFIG_SYS_HID2		HID2_HBE
553 
554 /*
555  * MMU Setup
556  */
557 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
558 
559 /* DDR: cache cacheable */
560 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
561 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
562 
563 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
564 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
565 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
566 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
567 
568 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
569 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
570 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
571 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
572 
573 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
574 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
575 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
576 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
577 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
578 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
579 
580 /* BCSR: cache-inhibit and guarded */
581 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
582 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
583 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
584 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
585 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
586 
587 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
588 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
589 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
590 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
591 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
592 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
593 
594 /* Stack in dcache: cacheable, no memory coherence */
595 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
596 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
597 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
598 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
599 
600 #ifdef CONFIG_PCI
601 /* PCI MEM space: cacheable */
602 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
603 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
604 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
605 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
606 /* PCI MMIO space: cache-inhibit and guarded */
607 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
608 			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
609 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
610 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
611 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
612 #else
613 #define CONFIG_SYS_IBAT6L	(0)
614 #define CONFIG_SYS_IBAT6U	(0)
615 #define CONFIG_SYS_IBAT7L	(0)
616 #define CONFIG_SYS_IBAT7U	(0)
617 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
618 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
619 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
620 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
621 #endif
622 
623 #if defined(CONFIG_CMD_KGDB)
624 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
625 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
626 #endif
627 
628 /*
629  * Environment Configuration
630  */
631 
632 #define CONFIG_ENV_OVERWRITE
633 
634 #if defined(CONFIG_TSEC_ENET)
635 #define CONFIG_HAS_ETH0
636 #define CONFIG_HAS_ETH1
637 #endif
638 
639 #define CONFIG_BAUDRATE 115200
640 
641 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
642 
643 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
644 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
645 
646 #define CONFIG_EXTRA_ENV_SETTINGS					\
647    "netdev=eth0\0"							\
648    "consoledev=ttyS0\0"							\
649    "ramdiskaddr=1000000\0"						\
650    "ramdiskfile=ramfs.83xx\0"						\
651    "fdtaddr=780000\0"							\
652    "fdtfile=mpc8379_mds.dtb\0"						\
653    ""
654 
655 #define CONFIG_NFSBOOTCOMMAND						\
656    "setenv bootargs root=/dev/nfs rw "					\
657       "nfsroot=$serverip:$rootpath "					\
658       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
659       "console=$consoledev,$baudrate $othbootargs;"			\
660    "tftp $loadaddr $bootfile;"						\
661    "tftp $fdtaddr $fdtfile;"						\
662    "bootm $loadaddr - $fdtaddr"
663 
664 #define CONFIG_RAMBOOTCOMMAND						\
665    "setenv bootargs root=/dev/ram rw "					\
666       "console=$consoledev,$baudrate $othbootargs;"			\
667    "tftp $ramdiskaddr $ramdiskfile;"					\
668    "tftp $loadaddr $bootfile;"						\
669    "tftp $fdtaddr $fdtfile;"						\
670    "bootm $loadaddr $ramdiskaddr $fdtaddr"
671 
672 
673 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
674 
675 #endif	/* __CONFIG_H */
676