1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 /* E300 family */ 17 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 18 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 /* 23 * System Clock Setup 24 */ 25 #ifdef CONFIG_PCISLAVE 26 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 27 #else 28 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 29 #endif 30 31 #ifndef CONFIG_SYS_CLK_FREQ 32 #define CONFIG_SYS_CLK_FREQ 66000000 33 #endif 34 35 /* 36 * Hardware Reset Configuration Word 37 * if CLKIN is 66MHz, then 38 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 39 */ 40 #define CONFIG_SYS_HRCW_LOW (\ 41 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 42 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 43 HRCWL_SVCOD_DIV_2 |\ 44 HRCWL_CSB_TO_CLKIN_6X1 |\ 45 HRCWL_CORE_TO_CSB_1_5X1) 46 47 #ifdef CONFIG_PCISLAVE 48 #define CONFIG_SYS_HRCW_HIGH (\ 49 HRCWH_PCI_AGENT |\ 50 HRCWH_PCI1_ARBITER_DISABLE |\ 51 HRCWH_CORE_ENABLE |\ 52 HRCWH_FROM_0XFFF00100 |\ 53 HRCWH_BOOTSEQ_DISABLE |\ 54 HRCWH_SW_WATCHDOG_DISABLE |\ 55 HRCWH_ROM_LOC_LOCAL_16BIT |\ 56 HRCWH_RL_EXT_LEGACY |\ 57 HRCWH_TSEC1M_IN_RGMII |\ 58 HRCWH_TSEC2M_IN_RGMII |\ 59 HRCWH_BIG_ENDIAN |\ 60 HRCWH_LDP_CLEAR) 61 #else 62 #define CONFIG_SYS_HRCW_HIGH (\ 63 HRCWH_PCI_HOST |\ 64 HRCWH_PCI1_ARBITER_ENABLE |\ 65 HRCWH_CORE_ENABLE |\ 66 HRCWH_FROM_0X00000100 |\ 67 HRCWH_BOOTSEQ_DISABLE |\ 68 HRCWH_SW_WATCHDOG_DISABLE |\ 69 HRCWH_ROM_LOC_LOCAL_16BIT |\ 70 HRCWH_RL_EXT_LEGACY |\ 71 HRCWH_TSEC1M_IN_RGMII |\ 72 HRCWH_TSEC2M_IN_RGMII |\ 73 HRCWH_BIG_ENDIAN |\ 74 HRCWH_LDP_CLEAR) 75 #endif 76 77 /* Arbiter Configuration Register */ 78 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 79 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 80 81 /* System Priority Control Register */ 82 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 83 84 /* 85 * IP blocks clock configuration 86 */ 87 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 88 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 89 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 90 91 /* 92 * System IO Config 93 */ 94 #define CONFIG_SYS_SICRH 0x00000000 95 #define CONFIG_SYS_SICRL 0x00000000 96 97 /* 98 * Output Buffer Impedance 99 */ 100 #define CONFIG_SYS_OBIR 0x31100000 101 102 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 103 #define CONFIG_BOARD_EARLY_INIT_R 104 #define CONFIG_HWCONFIG 105 106 /* 107 * IMMR new address 108 */ 109 #define CONFIG_SYS_IMMR 0xE0000000 110 111 /* 112 * DDR Setup 113 */ 114 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 116 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 118 #define CONFIG_SYS_83XX_DDR_USES_CS0 119 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 120 | DDRCDR_ODT \ 121 | DDRCDR_Q_DRN) 122 /* 0x80080001 */ /* ODT 150ohm on SoC */ 123 124 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 125 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 126 127 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 128 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 129 130 #if defined(CONFIG_SPD_EEPROM) 131 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 132 #else 133 /* 134 * Manually set up DDR parameters 135 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 136 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 137 */ 138 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 139 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 140 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 141 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 142 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 143 | CSCONFIG_ROW_BIT_14 \ 144 | CSCONFIG_COL_BIT_10) 145 /* 0x80010202 */ 146 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 147 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 148 | (0 << TIMING_CFG0_WRT_SHIFT) \ 149 | (0 << TIMING_CFG0_RRT_SHIFT) \ 150 | (0 << TIMING_CFG0_WWT_SHIFT) \ 151 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 152 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 155 /* 0x00620802 */ 156 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 157 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 158 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 159 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 160 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 161 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 163 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 164 /* 0x3935d322 */ 165 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 166 | (6 << TIMING_CFG2_CPO_SHIFT) \ 167 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 168 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 171 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 172 /* 0x131088c8 */ 173 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 175 /* 0x03E00100 */ 176 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 177 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 178 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 179 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 180 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 181 #define CONFIG_SYS_DDR_MODE2 0x00000000 182 #endif 183 184 /* 185 * Memory test 186 */ 187 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 188 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 189 #define CONFIG_SYS_MEMTEST_END 0x00140000 190 191 /* 192 * The reserved memory 193 */ 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 195 196 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 197 #define CONFIG_SYS_RAMBOOT 198 #else 199 #undef CONFIG_SYS_RAMBOOT 200 #endif 201 202 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 203 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 204 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 205 206 /* 207 * Initial RAM Base Address Setup 208 */ 209 #define CONFIG_SYS_INIT_RAM_LOCK 1 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 211 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 212 #define CONFIG_SYS_GBL_DATA_OFFSET \ 213 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 214 215 /* 216 * Local Bus Configuration & Clock Setup 217 */ 218 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 219 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 220 #define CONFIG_SYS_LBC_LBCR 0x00000000 221 #define CONFIG_FSL_ELBC 1 222 223 /* 224 * FLASH on the Local Bus 225 */ 226 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 227 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 228 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 229 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 230 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 231 232 /* Window base at flash base */ 233 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 234 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 235 236 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 237 | BR_PS_16 /* 16 bit port */ \ 238 | BR_MS_GPCM /* MSEL = GPCM */ \ 239 | BR_V) /* valid */ 240 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 241 | OR_UPM_XAM \ 242 | OR_GPCM_CSNT \ 243 | OR_GPCM_ACS_DIV2 \ 244 | OR_GPCM_XACS \ 245 | OR_GPCM_SCY_15 \ 246 | OR_GPCM_TRLX_SET \ 247 | OR_GPCM_EHTR_SET \ 248 | OR_GPCM_EAD) 249 /* 0xFE000FF7 */ 250 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 252 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 253 254 #undef CONFIG_SYS_FLASH_CHECKSUM 255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 257 258 /* 259 * BCSR on the Local Bus 260 */ 261 #define CONFIG_SYS_BCSR 0xF8000000 262 /* Access window base at BCSR base */ 263 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 264 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 265 266 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 267 | BR_PS_8 \ 268 | BR_MS_GPCM \ 269 | BR_V) 270 /* 0xF8000801 */ 271 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 272 | OR_GPCM_XAM \ 273 | OR_GPCM_CSNT \ 274 | OR_GPCM_XACS \ 275 | OR_GPCM_SCY_15 \ 276 | OR_GPCM_TRLX_SET \ 277 | OR_GPCM_EHTR_SET \ 278 | OR_GPCM_EAD) 279 /* 0xFFFFE9F7 */ 280 281 /* 282 * NAND Flash on the Local Bus 283 */ 284 #define CONFIG_CMD_NAND 1 285 #define CONFIG_SYS_MAX_NAND_DEVICE 1 286 #define CONFIG_NAND_FSL_ELBC 1 287 288 #define CONFIG_SYS_NAND_BASE 0xE0600000 289 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 290 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 291 | BR_PS_8 /* 8 bit port */ \ 292 | BR_MS_FCM /* MSEL = FCM */ \ 293 | BR_V) /* valid */ 294 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 295 | OR_FCM_BCTLD \ 296 | OR_FCM_CST \ 297 | OR_FCM_CHT \ 298 | OR_FCM_SCY_1 \ 299 | OR_FCM_RST \ 300 | OR_FCM_TRLX \ 301 | OR_FCM_EHTR) 302 /* 0xFFFF919E */ 303 304 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 305 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 306 307 /* 308 * Serial Port 309 */ 310 #define CONFIG_CONS_INDEX 1 311 #define CONFIG_SYS_NS16550_SERIAL 312 #define CONFIG_SYS_NS16550_REG_SIZE 1 313 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 314 315 #define CONFIG_SYS_BAUDRATE_TABLE \ 316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 317 318 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 319 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 320 321 /* I2C */ 322 #define CONFIG_SYS_I2C 323 #define CONFIG_SYS_I2C_FSL 324 #define CONFIG_SYS_FSL_I2C_SPEED 400000 325 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 326 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 327 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 328 329 /* 330 * Config on-board RTC 331 */ 332 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 333 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 334 335 /* 336 * General PCI 337 * Addresses are mapped 1-1. 338 */ 339 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 340 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 341 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 342 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 343 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 344 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 345 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 346 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 347 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 348 349 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 350 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 351 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 352 353 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 354 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 355 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 356 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 357 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 358 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 359 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 360 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 361 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 362 363 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 364 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 365 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 366 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 367 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 368 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 369 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 370 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 371 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 372 373 #ifdef CONFIG_PCI 374 #define CONFIG_PCI_INDIRECT_BRIDGE 375 #ifndef __ASSEMBLY__ 376 extern int board_pci_host_broken(void); 377 #endif 378 #define CONFIG_PCIE 379 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 380 381 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 382 #define CONFIG_USB_EHCI 383 #define CONFIG_USB_EHCI_FSL 384 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 385 386 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 387 388 #undef CONFIG_EEPRO100 389 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 390 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 391 #endif /* CONFIG_PCI */ 392 393 /* 394 * TSEC 395 */ 396 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 397 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 398 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 399 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 400 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 401 402 /* 403 * TSEC ethernet configuration 404 */ 405 #define CONFIG_MII 1 /* MII PHY management */ 406 #define CONFIG_TSEC1 1 407 #define CONFIG_TSEC1_NAME "eTSEC0" 408 #define CONFIG_TSEC2 1 409 #define CONFIG_TSEC2_NAME "eTSEC1" 410 #define TSEC1_PHY_ADDR 2 411 #define TSEC2_PHY_ADDR 3 412 #define TSEC1_PHY_ADDR_SGMII 8 413 #define TSEC2_PHY_ADDR_SGMII 4 414 #define TSEC1_PHYIDX 0 415 #define TSEC2_PHYIDX 0 416 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 419 /* Options are: TSEC[0-1] */ 420 #define CONFIG_ETHPRIME "eTSEC1" 421 422 /* SERDES */ 423 #define CONFIG_FSL_SERDES 424 #define CONFIG_FSL_SERDES1 0xe3000 425 #define CONFIG_FSL_SERDES2 0xe3100 426 427 /* 428 * SATA 429 */ 430 #define CONFIG_LIBATA 431 #define CONFIG_FSL_SATA 432 433 #define CONFIG_SYS_SATA_MAX_DEVICE 2 434 #define CONFIG_SATA1 435 #define CONFIG_SYS_SATA1_OFFSET 0x18000 436 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 437 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 438 #define CONFIG_SATA2 439 #define CONFIG_SYS_SATA2_OFFSET 0x19000 440 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 441 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 442 443 #ifdef CONFIG_FSL_SATA 444 #define CONFIG_LBA48 445 #define CONFIG_CMD_SATA 446 #define CONFIG_DOS_PARTITION 447 #endif 448 449 /* 450 * Environment 451 */ 452 #ifndef CONFIG_SYS_RAMBOOT 453 #define CONFIG_ENV_IS_IN_FLASH 1 454 #define CONFIG_ENV_ADDR \ 455 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 456 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 457 #define CONFIG_ENV_SIZE 0x2000 458 #else 459 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 460 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 461 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 462 #define CONFIG_ENV_SIZE 0x2000 463 #endif 464 465 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 466 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 467 468 /* 469 * BOOTP options 470 */ 471 #define CONFIG_BOOTP_BOOTFILESIZE 472 #define CONFIG_BOOTP_BOOTPATH 473 #define CONFIG_BOOTP_GATEWAY 474 #define CONFIG_BOOTP_HOSTNAME 475 476 /* 477 * Command line configuration. 478 */ 479 #define CONFIG_CMD_DATE 480 481 #if defined(CONFIG_PCI) 482 #define CONFIG_CMD_PCI 483 #endif 484 485 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 486 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 487 488 #undef CONFIG_WATCHDOG /* watchdog disabled */ 489 490 #define CONFIG_MMC 1 491 492 #ifdef CONFIG_MMC 493 #define CONFIG_FSL_ESDHC 494 #define CONFIG_FSL_ESDHC_PIN_MUX 495 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 496 #define CONFIG_GENERIC_MMC 497 #define CONFIG_DOS_PARTITION 498 #endif 499 500 /* 501 * Miscellaneous configurable options 502 */ 503 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 504 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 505 506 #if defined(CONFIG_CMD_KGDB) 507 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 508 #else 509 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 510 #endif 511 512 /* Print Buffer Size */ 513 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 514 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 515 /* Boot Argument Buffer Size */ 516 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 517 518 /* 519 * For booting Linux, the board info and command line data 520 * have to be in the first 256 MB of memory, since this is 521 * the maximum mapped by the Linux kernel during initialization. 522 */ 523 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 524 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 525 526 /* 527 * Core HID Setup 528 */ 529 #define CONFIG_SYS_HID0_INIT 0x000000000 530 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 531 HID0_ENABLE_INSTRUCTION_CACHE) 532 #define CONFIG_SYS_HID2 HID2_HBE 533 534 /* 535 * MMU Setup 536 */ 537 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 538 539 /* DDR: cache cacheable */ 540 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 541 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 542 543 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 544 | BATL_PP_RW \ 545 | BATL_MEMCOHERENCE) 546 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 547 | BATU_BL_256M \ 548 | BATU_VS \ 549 | BATU_VP) 550 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 551 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 552 553 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 554 | BATL_PP_RW \ 555 | BATL_MEMCOHERENCE) 556 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 557 | BATU_BL_256M \ 558 | BATU_VS \ 559 | BATU_VP) 560 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 561 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 562 563 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 564 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 565 | BATL_PP_RW \ 566 | BATL_CACHEINHIBIT \ 567 | BATL_GUARDEDSTORAGE) 568 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 569 | BATU_BL_8M \ 570 | BATU_VS \ 571 | BATU_VP) 572 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 573 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 574 575 /* BCSR: cache-inhibit and guarded */ 576 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 577 | BATL_PP_RW \ 578 | BATL_CACHEINHIBIT \ 579 | BATL_GUARDEDSTORAGE) 580 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 581 | BATU_BL_128K \ 582 | BATU_VS \ 583 | BATU_VP) 584 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 585 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 586 587 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 588 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 589 | BATL_PP_RW \ 590 | BATL_MEMCOHERENCE) 591 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 592 | BATU_BL_32M \ 593 | BATU_VS \ 594 | BATU_VP) 595 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 596 | BATL_PP_RW \ 597 | BATL_CACHEINHIBIT \ 598 | BATL_GUARDEDSTORAGE) 599 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 600 601 /* Stack in dcache: cacheable, no memory coherence */ 602 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 603 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 604 | BATU_BL_128K \ 605 | BATU_VS \ 606 | BATU_VP) 607 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 608 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 609 610 #ifdef CONFIG_PCI 611 /* PCI MEM space: cacheable */ 612 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 613 | BATL_PP_RW \ 614 | BATL_MEMCOHERENCE) 615 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 616 | BATU_BL_256M \ 617 | BATU_VS \ 618 | BATU_VP) 619 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 620 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 621 /* PCI MMIO space: cache-inhibit and guarded */ 622 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 623 | BATL_PP_RW \ 624 | BATL_CACHEINHIBIT \ 625 | BATL_GUARDEDSTORAGE) 626 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 627 | BATU_BL_256M \ 628 | BATU_VS \ 629 | BATU_VP) 630 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 631 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 632 #else 633 #define CONFIG_SYS_IBAT6L (0) 634 #define CONFIG_SYS_IBAT6U (0) 635 #define CONFIG_SYS_IBAT7L (0) 636 #define CONFIG_SYS_IBAT7U (0) 637 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 638 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 639 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 640 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 641 #endif 642 643 #if defined(CONFIG_CMD_KGDB) 644 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 645 #endif 646 647 /* 648 * Environment Configuration 649 */ 650 651 #define CONFIG_ENV_OVERWRITE 652 653 #if defined(CONFIG_TSEC_ENET) 654 #define CONFIG_HAS_ETH0 655 #define CONFIG_HAS_ETH1 656 #endif 657 658 #define CONFIG_BAUDRATE 115200 659 660 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 661 662 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 663 664 #define CONFIG_EXTRA_ENV_SETTINGS \ 665 "netdev=eth0\0" \ 666 "consoledev=ttyS0\0" \ 667 "ramdiskaddr=1000000\0" \ 668 "ramdiskfile=ramfs.83xx\0" \ 669 "fdtaddr=780000\0" \ 670 "fdtfile=mpc8379_mds.dtb\0" \ 671 "" 672 673 #define CONFIG_NFSBOOTCOMMAND \ 674 "setenv bootargs root=/dev/nfs rw " \ 675 "nfsroot=$serverip:$rootpath " \ 676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 677 "$netdev:off " \ 678 "console=$consoledev,$baudrate $othbootargs;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr - $fdtaddr" 682 683 #define CONFIG_RAMBOOTCOMMAND \ 684 "setenv bootargs root=/dev/ram rw " \ 685 "console=$consoledev,$baudrate $othbootargs;" \ 686 "tftp $ramdiskaddr $ramdiskfile;" \ 687 "tftp $loadaddr $bootfile;" \ 688 "tftp $fdtaddr $fdtfile;" \ 689 "bootm $loadaddr $ramdiskaddr $fdtaddr" 690 691 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 692 693 #endif /* __CONFIG_H */ 694