1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #define CONFIG_DISPLAY_BOARDINFO 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 /* E300 family */ 17 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 18 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 19 20 #define CONFIG_SYS_TEXT_BASE 0xFE000000 21 22 /* 23 * System Clock Setup 24 */ 25 #ifdef CONFIG_PCISLAVE 26 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 27 #else 28 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 29 #endif 30 31 #ifndef CONFIG_SYS_CLK_FREQ 32 #define CONFIG_SYS_CLK_FREQ 66000000 33 #endif 34 35 /* 36 * Hardware Reset Configuration Word 37 * if CLKIN is 66MHz, then 38 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 39 */ 40 #define CONFIG_SYS_HRCW_LOW (\ 41 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 42 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 43 HRCWL_SVCOD_DIV_2 |\ 44 HRCWL_CSB_TO_CLKIN_6X1 |\ 45 HRCWL_CORE_TO_CSB_1_5X1) 46 47 #ifdef CONFIG_PCISLAVE 48 #define CONFIG_SYS_HRCW_HIGH (\ 49 HRCWH_PCI_AGENT |\ 50 HRCWH_PCI1_ARBITER_DISABLE |\ 51 HRCWH_CORE_ENABLE |\ 52 HRCWH_FROM_0XFFF00100 |\ 53 HRCWH_BOOTSEQ_DISABLE |\ 54 HRCWH_SW_WATCHDOG_DISABLE |\ 55 HRCWH_ROM_LOC_LOCAL_16BIT |\ 56 HRCWH_RL_EXT_LEGACY |\ 57 HRCWH_TSEC1M_IN_RGMII |\ 58 HRCWH_TSEC2M_IN_RGMII |\ 59 HRCWH_BIG_ENDIAN |\ 60 HRCWH_LDP_CLEAR) 61 #else 62 #define CONFIG_SYS_HRCW_HIGH (\ 63 HRCWH_PCI_HOST |\ 64 HRCWH_PCI1_ARBITER_ENABLE |\ 65 HRCWH_CORE_ENABLE |\ 66 HRCWH_FROM_0X00000100 |\ 67 HRCWH_BOOTSEQ_DISABLE |\ 68 HRCWH_SW_WATCHDOG_DISABLE |\ 69 HRCWH_ROM_LOC_LOCAL_16BIT |\ 70 HRCWH_RL_EXT_LEGACY |\ 71 HRCWH_TSEC1M_IN_RGMII |\ 72 HRCWH_TSEC2M_IN_RGMII |\ 73 HRCWH_BIG_ENDIAN |\ 74 HRCWH_LDP_CLEAR) 75 #endif 76 77 /* Arbiter Configuration Register */ 78 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 79 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 80 81 /* System Priority Control Register */ 82 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 83 84 /* 85 * IP blocks clock configuration 86 */ 87 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 88 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 89 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 90 91 /* 92 * System IO Config 93 */ 94 #define CONFIG_SYS_SICRH 0x00000000 95 #define CONFIG_SYS_SICRL 0x00000000 96 97 /* 98 * Output Buffer Impedance 99 */ 100 #define CONFIG_SYS_OBIR 0x31100000 101 102 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 103 #define CONFIG_BOARD_EARLY_INIT_R 104 #define CONFIG_HWCONFIG 105 106 /* 107 * IMMR new address 108 */ 109 #define CONFIG_SYS_IMMR 0xE0000000 110 111 /* 112 * DDR Setup 113 */ 114 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 116 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 118 #define CONFIG_SYS_83XX_DDR_USES_CS0 119 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 120 | DDRCDR_ODT \ 121 | DDRCDR_Q_DRN) 122 /* 0x80080001 */ /* ODT 150ohm on SoC */ 123 124 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 125 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 126 127 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 128 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 129 130 #if defined(CONFIG_SPD_EEPROM) 131 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 132 #else 133 /* 134 * Manually set up DDR parameters 135 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 136 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 137 */ 138 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 139 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 140 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 141 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 142 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 143 | CSCONFIG_ROW_BIT_14 \ 144 | CSCONFIG_COL_BIT_10) 145 /* 0x80010202 */ 146 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 147 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 148 | (0 << TIMING_CFG0_WRT_SHIFT) \ 149 | (0 << TIMING_CFG0_RRT_SHIFT) \ 150 | (0 << TIMING_CFG0_WWT_SHIFT) \ 151 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 152 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 155 /* 0x00620802 */ 156 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 157 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 158 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 159 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 160 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 161 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 163 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 164 /* 0x3935d322 */ 165 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 166 | (6 << TIMING_CFG2_CPO_SHIFT) \ 167 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 168 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 171 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 172 /* 0x131088c8 */ 173 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 175 /* 0x03E00100 */ 176 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 177 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 178 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 179 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 180 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 181 #define CONFIG_SYS_DDR_MODE2 0x00000000 182 #endif 183 184 /* 185 * Memory test 186 */ 187 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 188 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 189 #define CONFIG_SYS_MEMTEST_END 0x00140000 190 191 /* 192 * The reserved memory 193 */ 194 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 195 196 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 197 #define CONFIG_SYS_RAMBOOT 198 #else 199 #undef CONFIG_SYS_RAMBOOT 200 #endif 201 202 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 203 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 204 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 205 206 /* 207 * Initial RAM Base Address Setup 208 */ 209 #define CONFIG_SYS_INIT_RAM_LOCK 1 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 211 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 212 #define CONFIG_SYS_GBL_DATA_OFFSET \ 213 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 214 215 /* 216 * Local Bus Configuration & Clock Setup 217 */ 218 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 219 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 220 #define CONFIG_SYS_LBC_LBCR 0x00000000 221 #define CONFIG_FSL_ELBC 1 222 223 /* 224 * FLASH on the Local Bus 225 */ 226 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 227 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 228 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 229 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 230 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 231 232 /* Window base at flash base */ 233 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 234 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 235 236 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 237 | BR_PS_16 /* 16 bit port */ \ 238 | BR_MS_GPCM /* MSEL = GPCM */ \ 239 | BR_V) /* valid */ 240 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 241 | OR_UPM_XAM \ 242 | OR_GPCM_CSNT \ 243 | OR_GPCM_ACS_DIV2 \ 244 | OR_GPCM_XACS \ 245 | OR_GPCM_SCY_15 \ 246 | OR_GPCM_TRLX_SET \ 247 | OR_GPCM_EHTR_SET \ 248 | OR_GPCM_EAD) 249 /* 0xFE000FF7 */ 250 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 252 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 253 254 #undef CONFIG_SYS_FLASH_CHECKSUM 255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 257 258 /* 259 * BCSR on the Local Bus 260 */ 261 #define CONFIG_SYS_BCSR 0xF8000000 262 /* Access window base at BCSR base */ 263 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 264 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 265 266 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 267 | BR_PS_8 \ 268 | BR_MS_GPCM \ 269 | BR_V) 270 /* 0xF8000801 */ 271 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 272 | OR_GPCM_XAM \ 273 | OR_GPCM_CSNT \ 274 | OR_GPCM_XACS \ 275 | OR_GPCM_SCY_15 \ 276 | OR_GPCM_TRLX_SET \ 277 | OR_GPCM_EHTR_SET \ 278 | OR_GPCM_EAD) 279 /* 0xFFFFE9F7 */ 280 281 /* 282 * NAND Flash on the Local Bus 283 */ 284 #define CONFIG_CMD_NAND 1 285 #define CONFIG_SYS_MAX_NAND_DEVICE 1 286 #define CONFIG_NAND_FSL_ELBC 1 287 288 #define CONFIG_SYS_NAND_BASE 0xE0600000 289 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 290 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 291 | BR_PS_8 /* 8 bit port */ \ 292 | BR_MS_FCM /* MSEL = FCM */ \ 293 | BR_V) /* valid */ 294 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 295 | OR_FCM_BCTLD \ 296 | OR_FCM_CST \ 297 | OR_FCM_CHT \ 298 | OR_FCM_SCY_1 \ 299 | OR_FCM_RST \ 300 | OR_FCM_TRLX \ 301 | OR_FCM_EHTR) 302 /* 0xFFFF919E */ 303 304 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 305 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 306 307 /* 308 * Serial Port 309 */ 310 #define CONFIG_CONS_INDEX 1 311 #define CONFIG_SYS_NS16550 312 #define CONFIG_SYS_NS16550_SERIAL 313 #define CONFIG_SYS_NS16550_REG_SIZE 1 314 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 315 316 #define CONFIG_SYS_BAUDRATE_TABLE \ 317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 318 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 321 322 /* Use the HUSH parser */ 323 #define CONFIG_SYS_HUSH_PARSER 324 325 /* Pass open firmware flat tree */ 326 #define CONFIG_OF_LIBFDT 1 327 #define CONFIG_OF_BOARD_SETUP 1 328 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 329 330 /* I2C */ 331 #define CONFIG_SYS_I2C 332 #define CONFIG_SYS_I2C_FSL 333 #define CONFIG_SYS_FSL_I2C_SPEED 400000 334 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 335 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 336 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 337 338 /* 339 * Config on-board RTC 340 */ 341 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 342 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 343 344 /* 345 * General PCI 346 * Addresses are mapped 1-1. 347 */ 348 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 349 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 350 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 351 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 352 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 353 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 354 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 355 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 356 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 357 358 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 359 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 360 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 361 362 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 363 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 364 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 365 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 366 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 367 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 368 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 369 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 370 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 371 372 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 373 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 374 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 375 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 376 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 377 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 378 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 379 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 380 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 381 382 #ifdef CONFIG_PCI 383 #define CONFIG_PCI_INDIRECT_BRIDGE 384 #ifndef __ASSEMBLY__ 385 extern int board_pci_host_broken(void); 386 #endif 387 #define CONFIG_PCIE 388 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 389 390 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 391 #define CONFIG_CMD_USB 392 #define CONFIG_USB_STORAGE 393 #define CONFIG_USB_EHCI 394 #define CONFIG_USB_EHCI_FSL 395 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 396 397 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 398 399 #undef CONFIG_EEPRO100 400 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 401 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 402 #endif /* CONFIG_PCI */ 403 404 /* 405 * TSEC 406 */ 407 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 408 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 409 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 410 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 411 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 412 413 /* 414 * TSEC ethernet configuration 415 */ 416 #define CONFIG_MII 1 /* MII PHY management */ 417 #define CONFIG_TSEC1 1 418 #define CONFIG_TSEC1_NAME "eTSEC0" 419 #define CONFIG_TSEC2 1 420 #define CONFIG_TSEC2_NAME "eTSEC1" 421 #define TSEC1_PHY_ADDR 2 422 #define TSEC2_PHY_ADDR 3 423 #define TSEC1_PHY_ADDR_SGMII 8 424 #define TSEC2_PHY_ADDR_SGMII 4 425 #define TSEC1_PHYIDX 0 426 #define TSEC2_PHYIDX 0 427 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 428 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 429 430 /* Options are: TSEC[0-1] */ 431 #define CONFIG_ETHPRIME "eTSEC1" 432 433 /* SERDES */ 434 #define CONFIG_FSL_SERDES 435 #define CONFIG_FSL_SERDES1 0xe3000 436 #define CONFIG_FSL_SERDES2 0xe3100 437 438 /* 439 * SATA 440 */ 441 #define CONFIG_LIBATA 442 #define CONFIG_FSL_SATA 443 444 #define CONFIG_SYS_SATA_MAX_DEVICE 2 445 #define CONFIG_SATA1 446 #define CONFIG_SYS_SATA1_OFFSET 0x18000 447 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 448 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 449 #define CONFIG_SATA2 450 #define CONFIG_SYS_SATA2_OFFSET 0x19000 451 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 452 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 453 454 #ifdef CONFIG_FSL_SATA 455 #define CONFIG_LBA48 456 #define CONFIG_CMD_SATA 457 #define CONFIG_DOS_PARTITION 458 #define CONFIG_CMD_EXT2 459 #endif 460 461 /* 462 * Environment 463 */ 464 #ifndef CONFIG_SYS_RAMBOOT 465 #define CONFIG_ENV_IS_IN_FLASH 1 466 #define CONFIG_ENV_ADDR \ 467 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 468 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 469 #define CONFIG_ENV_SIZE 0x2000 470 #else 471 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 472 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 473 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 474 #define CONFIG_ENV_SIZE 0x2000 475 #endif 476 477 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 478 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 479 480 /* 481 * BOOTP options 482 */ 483 #define CONFIG_BOOTP_BOOTFILESIZE 484 #define CONFIG_BOOTP_BOOTPATH 485 #define CONFIG_BOOTP_GATEWAY 486 #define CONFIG_BOOTP_HOSTNAME 487 488 489 /* 490 * Command line configuration. 491 */ 492 #define CONFIG_CMD_PING 493 #define CONFIG_CMD_I2C 494 #define CONFIG_CMD_MII 495 #define CONFIG_CMD_DATE 496 497 #if defined(CONFIG_PCI) 498 #define CONFIG_CMD_PCI 499 #endif 500 501 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 502 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 503 504 #undef CONFIG_WATCHDOG /* watchdog disabled */ 505 506 #define CONFIG_MMC 1 507 508 #ifdef CONFIG_MMC 509 #define CONFIG_FSL_ESDHC 510 #define CONFIG_FSL_ESDHC_PIN_MUX 511 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 512 #define CONFIG_CMD_MMC 513 #define CONFIG_GENERIC_MMC 514 #define CONFIG_CMD_EXT2 515 #define CONFIG_CMD_FAT 516 #define CONFIG_DOS_PARTITION 517 #endif 518 519 /* 520 * Miscellaneous configurable options 521 */ 522 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 523 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 524 525 #if defined(CONFIG_CMD_KGDB) 526 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 527 #else 528 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 529 #endif 530 531 /* Print Buffer Size */ 532 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 533 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 534 /* Boot Argument Buffer Size */ 535 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 536 537 /* 538 * For booting Linux, the board info and command line data 539 * have to be in the first 256 MB of memory, since this is 540 * the maximum mapped by the Linux kernel during initialization. 541 */ 542 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 543 544 /* 545 * Core HID Setup 546 */ 547 #define CONFIG_SYS_HID0_INIT 0x000000000 548 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 549 HID0_ENABLE_INSTRUCTION_CACHE) 550 #define CONFIG_SYS_HID2 HID2_HBE 551 552 /* 553 * MMU Setup 554 */ 555 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 556 557 /* DDR: cache cacheable */ 558 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 559 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 560 561 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 562 | BATL_PP_RW \ 563 | BATL_MEMCOHERENCE) 564 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 565 | BATU_BL_256M \ 566 | BATU_VS \ 567 | BATU_VP) 568 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 569 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 570 571 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 572 | BATL_PP_RW \ 573 | BATL_MEMCOHERENCE) 574 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 575 | BATU_BL_256M \ 576 | BATU_VS \ 577 | BATU_VP) 578 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 579 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 580 581 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 582 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 583 | BATL_PP_RW \ 584 | BATL_CACHEINHIBIT \ 585 | BATL_GUARDEDSTORAGE) 586 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 587 | BATU_BL_8M \ 588 | BATU_VS \ 589 | BATU_VP) 590 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 591 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 592 593 /* BCSR: cache-inhibit and guarded */ 594 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 595 | BATL_PP_RW \ 596 | BATL_CACHEINHIBIT \ 597 | BATL_GUARDEDSTORAGE) 598 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 599 | BATU_BL_128K \ 600 | BATU_VS \ 601 | BATU_VP) 602 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 603 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 604 605 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 606 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 607 | BATL_PP_RW \ 608 | BATL_MEMCOHERENCE) 609 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 610 | BATU_BL_32M \ 611 | BATU_VS \ 612 | BATU_VP) 613 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 614 | BATL_PP_RW \ 615 | BATL_CACHEINHIBIT \ 616 | BATL_GUARDEDSTORAGE) 617 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 618 619 /* Stack in dcache: cacheable, no memory coherence */ 620 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 621 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 622 | BATU_BL_128K \ 623 | BATU_VS \ 624 | BATU_VP) 625 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 626 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 627 628 #ifdef CONFIG_PCI 629 /* PCI MEM space: cacheable */ 630 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 631 | BATL_PP_RW \ 632 | BATL_MEMCOHERENCE) 633 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 634 | BATU_BL_256M \ 635 | BATU_VS \ 636 | BATU_VP) 637 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 638 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 639 /* PCI MMIO space: cache-inhibit and guarded */ 640 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 641 | BATL_PP_RW \ 642 | BATL_CACHEINHIBIT \ 643 | BATL_GUARDEDSTORAGE) 644 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 645 | BATU_BL_256M \ 646 | BATU_VS \ 647 | BATU_VP) 648 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 649 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 650 #else 651 #define CONFIG_SYS_IBAT6L (0) 652 #define CONFIG_SYS_IBAT6U (0) 653 #define CONFIG_SYS_IBAT7L (0) 654 #define CONFIG_SYS_IBAT7U (0) 655 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 656 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 657 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 658 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 659 #endif 660 661 #if defined(CONFIG_CMD_KGDB) 662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 663 #endif 664 665 /* 666 * Environment Configuration 667 */ 668 669 #define CONFIG_ENV_OVERWRITE 670 671 #if defined(CONFIG_TSEC_ENET) 672 #define CONFIG_HAS_ETH0 673 #define CONFIG_HAS_ETH1 674 #endif 675 676 #define CONFIG_BAUDRATE 115200 677 678 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 679 680 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 681 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 682 683 #define CONFIG_EXTRA_ENV_SETTINGS \ 684 "netdev=eth0\0" \ 685 "consoledev=ttyS0\0" \ 686 "ramdiskaddr=1000000\0" \ 687 "ramdiskfile=ramfs.83xx\0" \ 688 "fdtaddr=780000\0" \ 689 "fdtfile=mpc8379_mds.dtb\0" \ 690 "" 691 692 #define CONFIG_NFSBOOTCOMMAND \ 693 "setenv bootargs root=/dev/nfs rw " \ 694 "nfsroot=$serverip:$rootpath " \ 695 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 696 "$netdev:off " \ 697 "console=$consoledev,$baudrate $othbootargs;" \ 698 "tftp $loadaddr $bootfile;" \ 699 "tftp $fdtaddr $fdtfile;" \ 700 "bootm $loadaddr - $fdtaddr" 701 702 #define CONFIG_RAMBOOTCOMMAND \ 703 "setenv bootargs root=/dev/ram rw " \ 704 "console=$consoledev,$baudrate $othbootargs;" \ 705 "tftp $ramdiskaddr $ramdiskfile;" \ 706 "tftp $loadaddr $bootfile;" \ 707 "tftp $fdtaddr $fdtfile;" \ 708 "bootm $loadaddr $ramdiskaddr $fdtaddr" 709 710 711 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 712 713 #endif /* __CONFIG_H */ 714