1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Dave Liu <daveliu@freescale.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10 
11 /*
12  * High Level Configuration Options
13  */
14 #define CONFIG_E300		1 /* E300 family */
15 #define CONFIG_MPC837x		1 /* MPC837x CPU specific */
16 #define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
17 
18 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
19 
20 /*
21  * System Clock Setup
22  */
23 #ifdef CONFIG_PCISLAVE
24 #define CONFIG_83XX_PCICLK	66000000 /* in HZ */
25 #else
26 #define CONFIG_83XX_CLKIN	66000000 /* in Hz */
27 #endif
28 
29 #ifndef CONFIG_SYS_CLK_FREQ
30 #define CONFIG_SYS_CLK_FREQ	66000000
31 #endif
32 
33 /*
34  * Hardware Reset Configuration Word
35  * if CLKIN is 66MHz, then
36  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
37  */
38 #define CONFIG_SYS_HRCW_LOW (\
39 	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
40 	HRCWL_DDR_TO_SCB_CLK_1X1 |\
41 	HRCWL_SVCOD_DIV_2 |\
42 	HRCWL_CSB_TO_CLKIN_6X1 |\
43 	HRCWL_CORE_TO_CSB_1_5X1)
44 
45 #ifdef CONFIG_PCISLAVE
46 #define CONFIG_SYS_HRCW_HIGH (\
47 	HRCWH_PCI_AGENT |\
48 	HRCWH_PCI1_ARBITER_DISABLE |\
49 	HRCWH_CORE_ENABLE |\
50 	HRCWH_FROM_0XFFF00100 |\
51 	HRCWH_BOOTSEQ_DISABLE |\
52 	HRCWH_SW_WATCHDOG_DISABLE |\
53 	HRCWH_ROM_LOC_LOCAL_16BIT |\
54 	HRCWH_RL_EXT_LEGACY |\
55 	HRCWH_TSEC1M_IN_RGMII |\
56 	HRCWH_TSEC2M_IN_RGMII |\
57 	HRCWH_BIG_ENDIAN |\
58 	HRCWH_LDP_CLEAR)
59 #else
60 #define CONFIG_SYS_HRCW_HIGH (\
61 	HRCWH_PCI_HOST |\
62 	HRCWH_PCI1_ARBITER_ENABLE |\
63 	HRCWH_CORE_ENABLE |\
64 	HRCWH_FROM_0X00000100 |\
65 	HRCWH_BOOTSEQ_DISABLE |\
66 	HRCWH_SW_WATCHDOG_DISABLE |\
67 	HRCWH_ROM_LOC_LOCAL_16BIT |\
68 	HRCWH_RL_EXT_LEGACY |\
69 	HRCWH_TSEC1M_IN_RGMII |\
70 	HRCWH_TSEC2M_IN_RGMII |\
71 	HRCWH_BIG_ENDIAN |\
72 	HRCWH_LDP_CLEAR)
73 #endif
74 
75 /* Arbiter Configuration Register */
76 #define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
77 #define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count is 4 */
78 
79 /* System Priority Control Register */
80 #define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC1/2 emergency has highest priority */
81 
82 /*
83  * IP blocks clock configuration
84  */
85 #define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
86 #define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
87 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
88 
89 /*
90  * System IO Config
91  */
92 #define CONFIG_SYS_SICRH		0x00000000
93 #define CONFIG_SYS_SICRL		0x00000000
94 
95 /*
96  * Output Buffer Impedance
97  */
98 #define CONFIG_SYS_OBIR		0x31100000
99 
100 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
101 #define CONFIG_BOARD_EARLY_INIT_R
102 #define CONFIG_HWCONFIG
103 
104 /*
105  * IMMR new address
106  */
107 #define CONFIG_SYS_IMMR		0xE0000000
108 
109 /*
110  * DDR Setup
111  */
112 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
113 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
114 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
115 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
116 #define CONFIG_SYS_83XX_DDR_USES_CS0
117 #define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_DHC_EN \
118 					| DDRCDR_ODT \
119 					| DDRCDR_Q_DRN)
120 					/* 0x80080001 */ /* ODT 150ohm on SoC */
121 
122 #undef CONFIG_DDR_ECC		/* support DDR ECC function */
123 #undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
124 
125 #define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
126 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
127 
128 #if defined(CONFIG_SPD_EEPROM)
129 #define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
130 #else
131 /*
132  * Manually set up DDR parameters
133  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
134  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
135  */
136 #define CONFIG_SYS_DDR_SIZE		512 /* MB */
137 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
138 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
139 			| CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
140 			| CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
141 			| CSCONFIG_ROW_BIT_14 \
142 			| CSCONFIG_COL_BIT_10)
143 			/* 0x80010202 */
144 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
145 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
146 				| (0 << TIMING_CFG0_WRT_SHIFT) \
147 				| (0 << TIMING_CFG0_RRT_SHIFT) \
148 				| (0 << TIMING_CFG0_WWT_SHIFT) \
149 				| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
150 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
151 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
152 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
153 				/* 0x00620802 */
154 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
155 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
156 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
157 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
158 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
159 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
160 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
161 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
162 				/* 0x3935d322 */
163 #define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
164 				| (6 << TIMING_CFG2_CPO_SHIFT) \
165 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
166 				| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
167 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
168 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
169 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
170 				/* 0x131088c8 */
171 #define CONFIG_SYS_DDR_INTERVAL	((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
172 				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
173 				/* 0x03E00100 */
174 #define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
175 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
176 #define CONFIG_SYS_DDR_MODE	((0x0448 << SDRAM_MODE_ESD_SHIFT) \
177 				| (0x1432 << SDRAM_MODE_SD_SHIFT))
178 				/* ODT 150ohm CL=3, AL=1 on SDRAM */
179 #define CONFIG_SYS_DDR_MODE2	0x00000000
180 #endif
181 
182 /*
183  * Memory test
184  */
185 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
186 #define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
187 #define CONFIG_SYS_MEMTEST_END		0x00140000
188 
189 /*
190  * The reserved memory
191  */
192 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
193 
194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195 #define CONFIG_SYS_RAMBOOT
196 #else
197 #undef CONFIG_SYS_RAMBOOT
198 #endif
199 
200 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
201 #define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
202 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
203 
204 /*
205  * Initial RAM Base Address Setup
206  */
207 #define CONFIG_SYS_INIT_RAM_LOCK	1
208 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
209 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
210 #define CONFIG_SYS_GBL_DATA_OFFSET	\
211 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
212 
213 /*
214  * Local Bus Configuration & Clock Setup
215  */
216 #define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
217 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
218 #define CONFIG_SYS_LBC_LBCR		0x00000000
219 #define CONFIG_FSL_ELBC		1
220 
221 /*
222  * FLASH on the Local Bus
223  */
224 #define CONFIG_SYS_FLASH_CFI	/* use the Common Flash Interface */
225 #define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
226 #define CONFIG_SYS_FLASH_BASE	0xFE000000 /* FLASH base address */
227 #define CONFIG_SYS_FLASH_SIZE	32 /* max FLASH size is 32M */
228 #define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
229 
230 					/* Window base at flash base */
231 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
232 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
233 
234 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
235 				| BR_PS_16	/* 16 bit port */ \
236 				| BR_MS_GPCM	/* MSEL = GPCM */ \
237 				| BR_V)		/* valid */
238 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
239 				| OR_UPM_XAM \
240 				| OR_GPCM_CSNT \
241 				| OR_GPCM_ACS_DIV2 \
242 				| OR_GPCM_XACS \
243 				| OR_GPCM_SCY_15 \
244 				| OR_GPCM_TRLX_SET \
245 				| OR_GPCM_EHTR_SET \
246 				| OR_GPCM_EAD)
247 				/* 0xFE000FF7 */
248 
249 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
250 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
251 
252 #undef CONFIG_SYS_FLASH_CHECKSUM
253 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
254 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
255 
256 /*
257  * BCSR on the Local Bus
258  */
259 #define CONFIG_SYS_BCSR		0xF8000000
260 					/* Access window base at BCSR base */
261 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
262 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
263 
264 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR \
265 				| BR_PS_8 \
266 				| BR_MS_GPCM \
267 				| BR_V)
268 				/* 0xF8000801 */
269 #define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
270 				| OR_GPCM_XAM \
271 				| OR_GPCM_CSNT \
272 				| OR_GPCM_XACS \
273 				| OR_GPCM_SCY_15 \
274 				| OR_GPCM_TRLX_SET \
275 				| OR_GPCM_EHTR_SET \
276 				| OR_GPCM_EAD)
277 				/* 0xFFFFE9F7 */
278 
279 /*
280  * NAND Flash on the Local Bus
281  */
282 #define CONFIG_CMD_NAND		1
283 #define CONFIG_MTD_NAND_VERIFY_WRITE	1
284 #define CONFIG_SYS_MAX_NAND_DEVICE	1
285 #define CONFIG_NAND_FSL_ELBC	1
286 
287 #define CONFIG_SYS_NAND_BASE	0xE0600000
288 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE \
289 				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
290 				| BR_PS_8		/* 8 bit port */ \
291 				| BR_MS_FCM		/* MSEL = FCM */ \
292 				| BR_V)			/* valid */
293 #define CONFIG_SYS_OR3_PRELIM	(OR_AM_32KB \
294 				| OR_FCM_BCTLD \
295 				| OR_FCM_CST \
296 				| OR_FCM_CHT \
297 				| OR_FCM_SCY_1 \
298 				| OR_FCM_RST \
299 				| OR_FCM_TRLX \
300 				| OR_FCM_EHTR)
301 				/* 0xFFFF919E */
302 
303 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_NAND_BASE
304 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
305 
306 /*
307  * Serial Port
308  */
309 #define CONFIG_CONS_INDEX	1
310 #define CONFIG_SYS_NS16550
311 #define CONFIG_SYS_NS16550_SERIAL
312 #define CONFIG_SYS_NS16550_REG_SIZE	1
313 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
314 
315 #define CONFIG_SYS_BAUDRATE_TABLE  \
316 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
317 
318 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
319 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
320 
321 /* Use the HUSH parser */
322 #define CONFIG_SYS_HUSH_PARSER
323 
324 /* Pass open firmware flat tree */
325 #define CONFIG_OF_LIBFDT	1
326 #define CONFIG_OF_BOARD_SETUP	1
327 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
328 
329 /* I2C */
330 #define CONFIG_SYS_I2C
331 #define CONFIG_SYS_I2C_FSL
332 #define CONFIG_SYS_FSL_I2C_SPEED	400000
333 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
334 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
335 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
336 
337 /*
338  * Config on-board RTC
339  */
340 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
341 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
342 
343 /*
344  * General PCI
345  * Addresses are mapped 1-1.
346  */
347 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
348 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
349 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
350 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
351 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
352 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
353 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
354 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
355 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
356 
357 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
358 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
359 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
360 
361 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
362 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
363 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
364 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
365 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
366 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
367 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
368 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
369 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
370 
371 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
372 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
373 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
374 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
375 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
376 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
377 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
378 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
379 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
380 
381 #ifdef CONFIG_PCI
382 #define CONFIG_PCI_INDIRECT_BRIDGE
383 #ifndef __ASSEMBLY__
384 extern int board_pci_host_broken(void);
385 #endif
386 #define CONFIG_PCIE
387 #define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
388 
389 #define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
390 
391 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
392 
393 #undef CONFIG_EEPRO100
394 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
395 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
396 #endif /* CONFIG_PCI */
397 
398 /*
399  * TSEC
400  */
401 #define CONFIG_TSEC_ENET	/* TSEC ethernet support */
402 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
403 #define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
404 #define CONFIG_SYS_TSEC2_OFFSET	0x25000
405 #define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
406 
407 /*
408  * TSEC ethernet configuration
409  */
410 #define CONFIG_MII		1 /* MII PHY management */
411 #define CONFIG_TSEC1		1
412 #define CONFIG_TSEC1_NAME	"eTSEC0"
413 #define CONFIG_TSEC2		1
414 #define CONFIG_TSEC2_NAME	"eTSEC1"
415 #define TSEC1_PHY_ADDR		2
416 #define TSEC2_PHY_ADDR		3
417 #define TSEC1_PHY_ADDR_SGMII	8
418 #define TSEC2_PHY_ADDR_SGMII	4
419 #define TSEC1_PHYIDX		0
420 #define TSEC2_PHYIDX		0
421 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
422 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
423 
424 /* Options are: TSEC[0-1] */
425 #define CONFIG_ETHPRIME		"eTSEC1"
426 
427 /* SERDES */
428 #define CONFIG_FSL_SERDES
429 #define CONFIG_FSL_SERDES1	0xe3000
430 #define CONFIG_FSL_SERDES2	0xe3100
431 
432 /*
433  * SATA
434  */
435 #define CONFIG_LIBATA
436 #define CONFIG_FSL_SATA
437 
438 #define CONFIG_SYS_SATA_MAX_DEVICE	2
439 #define CONFIG_SATA1
440 #define CONFIG_SYS_SATA1_OFFSET	0x18000
441 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
442 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
443 #define CONFIG_SATA2
444 #define CONFIG_SYS_SATA2_OFFSET	0x19000
445 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
446 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
447 
448 #ifdef CONFIG_FSL_SATA
449 #define CONFIG_LBA48
450 #define CONFIG_CMD_SATA
451 #define CONFIG_DOS_PARTITION
452 #define CONFIG_CMD_EXT2
453 #endif
454 
455 /*
456  * Environment
457  */
458 #ifndef CONFIG_SYS_RAMBOOT
459 	#define CONFIG_ENV_IS_IN_FLASH	1
460 	#define CONFIG_ENV_ADDR		\
461 			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
462 	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
463 	#define CONFIG_ENV_SIZE		0x2000
464 #else
465 	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
466 	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
467 	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
468 	#define CONFIG_ENV_SIZE		0x2000
469 #endif
470 
471 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
472 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
473 
474 /*
475  * BOOTP options
476  */
477 #define CONFIG_BOOTP_BOOTFILESIZE
478 #define CONFIG_BOOTP_BOOTPATH
479 #define CONFIG_BOOTP_GATEWAY
480 #define CONFIG_BOOTP_HOSTNAME
481 
482 
483 /*
484  * Command line configuration.
485  */
486 #include <config_cmd_default.h>
487 
488 #define CONFIG_CMD_PING
489 #define CONFIG_CMD_I2C
490 #define CONFIG_CMD_MII
491 #define CONFIG_CMD_DATE
492 
493 #if defined(CONFIG_PCI)
494     #define CONFIG_CMD_PCI
495 #endif
496 
497 #if defined(CONFIG_SYS_RAMBOOT)
498     #undef CONFIG_CMD_SAVEENV
499     #undef CONFIG_CMD_LOADS
500 #endif
501 
502 #define CONFIG_CMDLINE_EDITING	1	/* add command line history */
503 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
504 
505 #undef CONFIG_WATCHDOG		/* watchdog disabled */
506 
507 #define CONFIG_MMC     1
508 
509 #ifdef CONFIG_MMC
510 #define CONFIG_FSL_ESDHC
511 #define CONFIG_FSL_ESDHC_PIN_MUX
512 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
513 #define CONFIG_CMD_MMC
514 #define CONFIG_GENERIC_MMC
515 #define CONFIG_CMD_EXT2
516 #define CONFIG_CMD_FAT
517 #define CONFIG_DOS_PARTITION
518 #endif
519 
520 /*
521  * Miscellaneous configurable options
522  */
523 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
524 #define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
525 
526 #if defined(CONFIG_CMD_KGDB)
527 	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
528 #else
529 	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
530 #endif
531 
532 				/* Print Buffer Size */
533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
534 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
535 				/* Boot Argument Buffer Size */
536 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
537 
538 /*
539  * For booting Linux, the board info and command line data
540  * have to be in the first 256 MB of memory, since this is
541  * the maximum mapped by the Linux kernel during initialization.
542  */
543 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
544 
545 /*
546  * Core HID Setup
547  */
548 #define CONFIG_SYS_HID0_INIT	0x000000000
549 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
550 				 HID0_ENABLE_INSTRUCTION_CACHE)
551 #define CONFIG_SYS_HID2		HID2_HBE
552 
553 /*
554  * MMU Setup
555  */
556 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
557 
558 /* DDR: cache cacheable */
559 #define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
560 #define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
561 
562 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
563 				| BATL_PP_RW \
564 				| BATL_MEMCOHERENCE)
565 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
566 				| BATU_BL_256M \
567 				| BATU_VS \
568 				| BATU_VP)
569 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
570 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
571 
572 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
573 				| BATL_PP_RW \
574 				| BATL_MEMCOHERENCE)
575 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
576 				| BATU_BL_256M \
577 				| BATU_VS \
578 				| BATU_VP)
579 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
580 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
581 
582 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
583 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
584 				| BATL_PP_RW \
585 				| BATL_CACHEINHIBIT \
586 				| BATL_GUARDEDSTORAGE)
587 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
588 				| BATU_BL_8M \
589 				| BATU_VS \
590 				| BATU_VP)
591 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
592 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
593 
594 /* BCSR: cache-inhibit and guarded */
595 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_BCSR \
596 				| BATL_PP_RW \
597 				| BATL_CACHEINHIBIT \
598 				| BATL_GUARDEDSTORAGE)
599 #define CONFIG_SYS_IBAT3U	(CONFIG_SYS_BCSR \
600 				| BATU_BL_128K \
601 				| BATU_VS \
602 				| BATU_VP)
603 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
604 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
605 
606 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
607 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
608 				| BATL_PP_RW \
609 				| BATL_MEMCOHERENCE)
610 #define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
611 				| BATU_BL_32M \
612 				| BATU_VS \
613 				| BATU_VP)
614 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
615 				| BATL_PP_RW \
616 				| BATL_CACHEINHIBIT \
617 				| BATL_GUARDEDSTORAGE)
618 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
619 
620 /* Stack in dcache: cacheable, no memory coherence */
621 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
622 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
623 				| BATU_BL_128K \
624 				| BATU_VS \
625 				| BATU_VP)
626 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
627 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
628 
629 #ifdef CONFIG_PCI
630 /* PCI MEM space: cacheable */
631 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
632 				| BATL_PP_RW \
633 				| BATL_MEMCOHERENCE)
634 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
635 				| BATU_BL_256M \
636 				| BATU_VS \
637 				| BATU_VP)
638 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
639 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
640 /* PCI MMIO space: cache-inhibit and guarded */
641 #define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
642 				| BATL_PP_RW \
643 				| BATL_CACHEINHIBIT \
644 				| BATL_GUARDEDSTORAGE)
645 #define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
646 				| BATU_BL_256M \
647 				| BATU_VS \
648 				| BATU_VP)
649 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
650 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
651 #else
652 #define CONFIG_SYS_IBAT6L	(0)
653 #define CONFIG_SYS_IBAT6U	(0)
654 #define CONFIG_SYS_IBAT7L	(0)
655 #define CONFIG_SYS_IBAT7U	(0)
656 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
657 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
658 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
659 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
660 #endif
661 
662 #if defined(CONFIG_CMD_KGDB)
663 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
664 #endif
665 
666 /*
667  * Environment Configuration
668  */
669 
670 #define CONFIG_ENV_OVERWRITE
671 
672 #if defined(CONFIG_TSEC_ENET)
673 #define CONFIG_HAS_ETH0
674 #define CONFIG_HAS_ETH1
675 #endif
676 
677 #define CONFIG_BAUDRATE 115200
678 
679 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
680 
681 #define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
682 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
683 
684 #define CONFIG_EXTRA_ENV_SETTINGS					\
685 	"netdev=eth0\0"							\
686 	"consoledev=ttyS0\0"						\
687 	"ramdiskaddr=1000000\0"						\
688 	"ramdiskfile=ramfs.83xx\0"					\
689 	"fdtaddr=780000\0"						\
690 	"fdtfile=mpc8379_mds.dtb\0"					\
691 	""
692 
693 #define CONFIG_NFSBOOTCOMMAND						\
694 	"setenv bootargs root=/dev/nfs rw "				\
695 		"nfsroot=$serverip:$rootpath "				\
696 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
697 							"$netdev:off "	\
698 		"console=$consoledev,$baudrate $othbootargs;"		\
699 	"tftp $loadaddr $bootfile;"					\
700 	"tftp $fdtaddr $fdtfile;"					\
701 	"bootm $loadaddr - $fdtaddr"
702 
703 #define CONFIG_RAMBOOTCOMMAND						\
704 	"setenv bootargs root=/dev/ram rw "				\
705 		"console=$consoledev,$baudrate $othbootargs;"		\
706 	"tftp $ramdiskaddr $ramdiskfile;"				\
707 	"tftp $loadaddr $bootfile;"					\
708 	"tftp $fdtaddr $fdtfile;"					\
709 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
710 
711 
712 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
713 
714 #endif	/* __CONFIG_H */
715