1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #define CONFIG_SYS_GENERIC_BOARD 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 family */ 18 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 19 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 /* 24 * System Clock Setup 25 */ 26 #ifdef CONFIG_PCISLAVE 27 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 28 #else 29 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 30 #endif 31 32 #ifndef CONFIG_SYS_CLK_FREQ 33 #define CONFIG_SYS_CLK_FREQ 66000000 34 #endif 35 36 /* 37 * Hardware Reset Configuration Word 38 * if CLKIN is 66MHz, then 39 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 40 */ 41 #define CONFIG_SYS_HRCW_LOW (\ 42 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 43 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 44 HRCWL_SVCOD_DIV_2 |\ 45 HRCWL_CSB_TO_CLKIN_6X1 |\ 46 HRCWL_CORE_TO_CSB_1_5X1) 47 48 #ifdef CONFIG_PCISLAVE 49 #define CONFIG_SYS_HRCW_HIGH (\ 50 HRCWH_PCI_AGENT |\ 51 HRCWH_PCI1_ARBITER_DISABLE |\ 52 HRCWH_CORE_ENABLE |\ 53 HRCWH_FROM_0XFFF00100 |\ 54 HRCWH_BOOTSEQ_DISABLE |\ 55 HRCWH_SW_WATCHDOG_DISABLE |\ 56 HRCWH_ROM_LOC_LOCAL_16BIT |\ 57 HRCWH_RL_EXT_LEGACY |\ 58 HRCWH_TSEC1M_IN_RGMII |\ 59 HRCWH_TSEC2M_IN_RGMII |\ 60 HRCWH_BIG_ENDIAN |\ 61 HRCWH_LDP_CLEAR) 62 #else 63 #define CONFIG_SYS_HRCW_HIGH (\ 64 HRCWH_PCI_HOST |\ 65 HRCWH_PCI1_ARBITER_ENABLE |\ 66 HRCWH_CORE_ENABLE |\ 67 HRCWH_FROM_0X00000100 |\ 68 HRCWH_BOOTSEQ_DISABLE |\ 69 HRCWH_SW_WATCHDOG_DISABLE |\ 70 HRCWH_ROM_LOC_LOCAL_16BIT |\ 71 HRCWH_RL_EXT_LEGACY |\ 72 HRCWH_TSEC1M_IN_RGMII |\ 73 HRCWH_TSEC2M_IN_RGMII |\ 74 HRCWH_BIG_ENDIAN |\ 75 HRCWH_LDP_CLEAR) 76 #endif 77 78 /* Arbiter Configuration Register */ 79 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 80 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 81 82 /* System Priority Control Register */ 83 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 84 85 /* 86 * IP blocks clock configuration 87 */ 88 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 89 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 90 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 91 92 /* 93 * System IO Config 94 */ 95 #define CONFIG_SYS_SICRH 0x00000000 96 #define CONFIG_SYS_SICRL 0x00000000 97 98 /* 99 * Output Buffer Impedance 100 */ 101 #define CONFIG_SYS_OBIR 0x31100000 102 103 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 104 #define CONFIG_BOARD_EARLY_INIT_R 105 #define CONFIG_HWCONFIG 106 107 /* 108 * IMMR new address 109 */ 110 #define CONFIG_SYS_IMMR 0xE0000000 111 112 /* 113 * DDR Setup 114 */ 115 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 119 #define CONFIG_SYS_83XX_DDR_USES_CS0 120 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 121 | DDRCDR_ODT \ 122 | DDRCDR_Q_DRN) 123 /* 0x80080001 */ /* ODT 150ohm on SoC */ 124 125 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 126 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 127 128 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 129 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 130 131 #if defined(CONFIG_SPD_EEPROM) 132 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 133 #else 134 /* 135 * Manually set up DDR parameters 136 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 137 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 138 */ 139 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 141 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 142 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 143 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 144 | CSCONFIG_ROW_BIT_14 \ 145 | CSCONFIG_COL_BIT_10) 146 /* 0x80010202 */ 147 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 148 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 149 | (0 << TIMING_CFG0_WRT_SHIFT) \ 150 | (0 << TIMING_CFG0_RRT_SHIFT) \ 151 | (0 << TIMING_CFG0_WWT_SHIFT) \ 152 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 153 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 154 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 155 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 156 /* 0x00620802 */ 157 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 158 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 159 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 160 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 161 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 162 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 163 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 164 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 165 /* 0x3935d322 */ 166 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 167 | (6 << TIMING_CFG2_CPO_SHIFT) \ 168 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 169 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 170 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 171 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 172 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 173 /* 0x131088c8 */ 174 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 175 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 176 /* 0x03E00100 */ 177 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 178 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 179 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 180 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 181 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 182 #define CONFIG_SYS_DDR_MODE2 0x00000000 183 #endif 184 185 /* 186 * Memory test 187 */ 188 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 189 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 190 #define CONFIG_SYS_MEMTEST_END 0x00140000 191 192 /* 193 * The reserved memory 194 */ 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 196 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 204 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 205 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 206 207 /* 208 * Initial RAM Base Address Setup 209 */ 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 213 #define CONFIG_SYS_GBL_DATA_OFFSET \ 214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 216 /* 217 * Local Bus Configuration & Clock Setup 218 */ 219 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 220 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 221 #define CONFIG_SYS_LBC_LBCR 0x00000000 222 #define CONFIG_FSL_ELBC 1 223 224 /* 225 * FLASH on the Local Bus 226 */ 227 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 228 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 229 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 230 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 231 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 232 233 /* Window base at flash base */ 234 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 235 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 236 237 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 238 | BR_PS_16 /* 16 bit port */ \ 239 | BR_MS_GPCM /* MSEL = GPCM */ \ 240 | BR_V) /* valid */ 241 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 242 | OR_UPM_XAM \ 243 | OR_GPCM_CSNT \ 244 | OR_GPCM_ACS_DIV2 \ 245 | OR_GPCM_XACS \ 246 | OR_GPCM_SCY_15 \ 247 | OR_GPCM_TRLX_SET \ 248 | OR_GPCM_EHTR_SET \ 249 | OR_GPCM_EAD) 250 /* 0xFE000FF7 */ 251 252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 253 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 254 255 #undef CONFIG_SYS_FLASH_CHECKSUM 256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 258 259 /* 260 * BCSR on the Local Bus 261 */ 262 #define CONFIG_SYS_BCSR 0xF8000000 263 /* Access window base at BCSR base */ 264 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 265 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 266 267 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 268 | BR_PS_8 \ 269 | BR_MS_GPCM \ 270 | BR_V) 271 /* 0xF8000801 */ 272 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 273 | OR_GPCM_XAM \ 274 | OR_GPCM_CSNT \ 275 | OR_GPCM_XACS \ 276 | OR_GPCM_SCY_15 \ 277 | OR_GPCM_TRLX_SET \ 278 | OR_GPCM_EHTR_SET \ 279 | OR_GPCM_EAD) 280 /* 0xFFFFE9F7 */ 281 282 /* 283 * NAND Flash on the Local Bus 284 */ 285 #define CONFIG_CMD_NAND 1 286 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 287 #define CONFIG_SYS_MAX_NAND_DEVICE 1 288 #define CONFIG_NAND_FSL_ELBC 1 289 290 #define CONFIG_SYS_NAND_BASE 0xE0600000 291 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 292 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 293 | BR_PS_8 /* 8 bit port */ \ 294 | BR_MS_FCM /* MSEL = FCM */ \ 295 | BR_V) /* valid */ 296 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 297 | OR_FCM_BCTLD \ 298 | OR_FCM_CST \ 299 | OR_FCM_CHT \ 300 | OR_FCM_SCY_1 \ 301 | OR_FCM_RST \ 302 | OR_FCM_TRLX \ 303 | OR_FCM_EHTR) 304 /* 0xFFFF919E */ 305 306 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 307 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 308 309 /* 310 * Serial Port 311 */ 312 #define CONFIG_CONS_INDEX 1 313 #define CONFIG_SYS_NS16550 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 317 318 #define CONFIG_SYS_BAUDRATE_TABLE \ 319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 320 321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 323 324 /* Use the HUSH parser */ 325 #define CONFIG_SYS_HUSH_PARSER 326 327 /* Pass open firmware flat tree */ 328 #define CONFIG_OF_LIBFDT 1 329 #define CONFIG_OF_BOARD_SETUP 1 330 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 331 332 /* I2C */ 333 #define CONFIG_SYS_I2C 334 #define CONFIG_SYS_I2C_FSL 335 #define CONFIG_SYS_FSL_I2C_SPEED 400000 336 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 337 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 338 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 339 340 /* 341 * Config on-board RTC 342 */ 343 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 344 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 345 346 /* 347 * General PCI 348 * Addresses are mapped 1-1. 349 */ 350 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 351 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 352 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 353 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 354 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 355 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 356 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 357 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 358 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 359 360 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 361 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 362 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 363 364 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 365 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 366 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 367 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 368 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 369 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 370 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 371 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 372 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 373 374 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 375 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 376 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 377 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 378 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 379 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 380 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 381 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 382 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 383 384 #ifdef CONFIG_PCI 385 #define CONFIG_PCI_INDIRECT_BRIDGE 386 #ifndef __ASSEMBLY__ 387 extern int board_pci_host_broken(void); 388 #endif 389 #define CONFIG_PCIE 390 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 391 392 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 393 #define CONFIG_CMD_USB 394 #define CONFIG_USB_STORAGE 395 #define CONFIG_USB_EHCI 396 #define CONFIG_USB_EHCI_FSL 397 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 398 399 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 400 401 #undef CONFIG_EEPRO100 402 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 403 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 404 #endif /* CONFIG_PCI */ 405 406 /* 407 * TSEC 408 */ 409 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 410 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 411 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 412 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 413 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 414 415 /* 416 * TSEC ethernet configuration 417 */ 418 #define CONFIG_MII 1 /* MII PHY management */ 419 #define CONFIG_TSEC1 1 420 #define CONFIG_TSEC1_NAME "eTSEC0" 421 #define CONFIG_TSEC2 1 422 #define CONFIG_TSEC2_NAME "eTSEC1" 423 #define TSEC1_PHY_ADDR 2 424 #define TSEC2_PHY_ADDR 3 425 #define TSEC1_PHY_ADDR_SGMII 8 426 #define TSEC2_PHY_ADDR_SGMII 4 427 #define TSEC1_PHYIDX 0 428 #define TSEC2_PHYIDX 0 429 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 430 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 431 432 /* Options are: TSEC[0-1] */ 433 #define CONFIG_ETHPRIME "eTSEC1" 434 435 /* SERDES */ 436 #define CONFIG_FSL_SERDES 437 #define CONFIG_FSL_SERDES1 0xe3000 438 #define CONFIG_FSL_SERDES2 0xe3100 439 440 /* 441 * SATA 442 */ 443 #define CONFIG_LIBATA 444 #define CONFIG_FSL_SATA 445 446 #define CONFIG_SYS_SATA_MAX_DEVICE 2 447 #define CONFIG_SATA1 448 #define CONFIG_SYS_SATA1_OFFSET 0x18000 449 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 450 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 451 #define CONFIG_SATA2 452 #define CONFIG_SYS_SATA2_OFFSET 0x19000 453 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 454 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 455 456 #ifdef CONFIG_FSL_SATA 457 #define CONFIG_LBA48 458 #define CONFIG_CMD_SATA 459 #define CONFIG_DOS_PARTITION 460 #define CONFIG_CMD_EXT2 461 #endif 462 463 /* 464 * Environment 465 */ 466 #ifndef CONFIG_SYS_RAMBOOT 467 #define CONFIG_ENV_IS_IN_FLASH 1 468 #define CONFIG_ENV_ADDR \ 469 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 470 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 471 #define CONFIG_ENV_SIZE 0x2000 472 #else 473 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 474 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 475 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 476 #define CONFIG_ENV_SIZE 0x2000 477 #endif 478 479 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 480 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 481 482 /* 483 * BOOTP options 484 */ 485 #define CONFIG_BOOTP_BOOTFILESIZE 486 #define CONFIG_BOOTP_BOOTPATH 487 #define CONFIG_BOOTP_GATEWAY 488 #define CONFIG_BOOTP_HOSTNAME 489 490 491 /* 492 * Command line configuration. 493 */ 494 #include <config_cmd_default.h> 495 496 #define CONFIG_CMD_PING 497 #define CONFIG_CMD_I2C 498 #define CONFIG_CMD_MII 499 #define CONFIG_CMD_DATE 500 501 #if defined(CONFIG_PCI) 502 #define CONFIG_CMD_PCI 503 #endif 504 505 #if defined(CONFIG_SYS_RAMBOOT) 506 #undef CONFIG_CMD_SAVEENV 507 #undef CONFIG_CMD_LOADS 508 #endif 509 510 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 511 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 512 513 #undef CONFIG_WATCHDOG /* watchdog disabled */ 514 515 #define CONFIG_MMC 1 516 517 #ifdef CONFIG_MMC 518 #define CONFIG_FSL_ESDHC 519 #define CONFIG_FSL_ESDHC_PIN_MUX 520 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 521 #define CONFIG_CMD_MMC 522 #define CONFIG_GENERIC_MMC 523 #define CONFIG_CMD_EXT2 524 #define CONFIG_CMD_FAT 525 #define CONFIG_DOS_PARTITION 526 #endif 527 528 /* 529 * Miscellaneous configurable options 530 */ 531 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 532 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 533 534 #if defined(CONFIG_CMD_KGDB) 535 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 536 #else 537 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 538 #endif 539 540 /* Print Buffer Size */ 541 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 542 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 543 /* Boot Argument Buffer Size */ 544 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 545 546 /* 547 * For booting Linux, the board info and command line data 548 * have to be in the first 256 MB of memory, since this is 549 * the maximum mapped by the Linux kernel during initialization. 550 */ 551 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 552 553 /* 554 * Core HID Setup 555 */ 556 #define CONFIG_SYS_HID0_INIT 0x000000000 557 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 558 HID0_ENABLE_INSTRUCTION_CACHE) 559 #define CONFIG_SYS_HID2 HID2_HBE 560 561 /* 562 * MMU Setup 563 */ 564 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 565 566 /* DDR: cache cacheable */ 567 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 568 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 569 570 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 571 | BATL_PP_RW \ 572 | BATL_MEMCOHERENCE) 573 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 574 | BATU_BL_256M \ 575 | BATU_VS \ 576 | BATU_VP) 577 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 578 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 579 580 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 581 | BATL_PP_RW \ 582 | BATL_MEMCOHERENCE) 583 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 584 | BATU_BL_256M \ 585 | BATU_VS \ 586 | BATU_VP) 587 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 588 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 589 590 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 591 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 592 | BATL_PP_RW \ 593 | BATL_CACHEINHIBIT \ 594 | BATL_GUARDEDSTORAGE) 595 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 596 | BATU_BL_8M \ 597 | BATU_VS \ 598 | BATU_VP) 599 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 600 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 601 602 /* BCSR: cache-inhibit and guarded */ 603 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 604 | BATL_PP_RW \ 605 | BATL_CACHEINHIBIT \ 606 | BATL_GUARDEDSTORAGE) 607 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 608 | BATU_BL_128K \ 609 | BATU_VS \ 610 | BATU_VP) 611 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 612 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 613 614 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 615 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 616 | BATL_PP_RW \ 617 | BATL_MEMCOHERENCE) 618 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 619 | BATU_BL_32M \ 620 | BATU_VS \ 621 | BATU_VP) 622 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 623 | BATL_PP_RW \ 624 | BATL_CACHEINHIBIT \ 625 | BATL_GUARDEDSTORAGE) 626 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 627 628 /* Stack in dcache: cacheable, no memory coherence */ 629 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 630 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 631 | BATU_BL_128K \ 632 | BATU_VS \ 633 | BATU_VP) 634 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 635 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 636 637 #ifdef CONFIG_PCI 638 /* PCI MEM space: cacheable */ 639 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 640 | BATL_PP_RW \ 641 | BATL_MEMCOHERENCE) 642 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 643 | BATU_BL_256M \ 644 | BATU_VS \ 645 | BATU_VP) 646 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 647 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 648 /* PCI MMIO space: cache-inhibit and guarded */ 649 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 650 | BATL_PP_RW \ 651 | BATL_CACHEINHIBIT \ 652 | BATL_GUARDEDSTORAGE) 653 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 654 | BATU_BL_256M \ 655 | BATU_VS \ 656 | BATU_VP) 657 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 658 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 659 #else 660 #define CONFIG_SYS_IBAT6L (0) 661 #define CONFIG_SYS_IBAT6U (0) 662 #define CONFIG_SYS_IBAT7L (0) 663 #define CONFIG_SYS_IBAT7U (0) 664 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 665 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 666 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 667 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 668 #endif 669 670 #if defined(CONFIG_CMD_KGDB) 671 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 672 #endif 673 674 /* 675 * Environment Configuration 676 */ 677 678 #define CONFIG_ENV_OVERWRITE 679 680 #if defined(CONFIG_TSEC_ENET) 681 #define CONFIG_HAS_ETH0 682 #define CONFIG_HAS_ETH1 683 #endif 684 685 #define CONFIG_BAUDRATE 115200 686 687 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 688 689 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 690 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 691 692 #define CONFIG_EXTRA_ENV_SETTINGS \ 693 "netdev=eth0\0" \ 694 "consoledev=ttyS0\0" \ 695 "ramdiskaddr=1000000\0" \ 696 "ramdiskfile=ramfs.83xx\0" \ 697 "fdtaddr=780000\0" \ 698 "fdtfile=mpc8379_mds.dtb\0" \ 699 "" 700 701 #define CONFIG_NFSBOOTCOMMAND \ 702 "setenv bootargs root=/dev/nfs rw " \ 703 "nfsroot=$serverip:$rootpath " \ 704 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 705 "$netdev:off " \ 706 "console=$consoledev,$baudrate $othbootargs;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr - $fdtaddr" 710 711 #define CONFIG_RAMBOOTCOMMAND \ 712 "setenv bootargs root=/dev/ram rw " \ 713 "console=$consoledev,$baudrate $othbootargs;" \ 714 "tftp $ramdiskaddr $ramdiskfile;" \ 715 "tftp $loadaddr $bootfile;" \ 716 "tftp $fdtaddr $fdtfile;" \ 717 "bootm $loadaddr $ramdiskaddr $fdtaddr" 718 719 720 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 721 722 #endif /* __CONFIG_H */ 723