1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #ifndef __CONFIG_H 22 #define __CONFIG_H 23 24 /* 25 * High Level Configuration Options 26 */ 27 #define CONFIG_E300 1 /* E300 family */ 28 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 29 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 30 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 31 32 /* 33 * System Clock Setup 34 */ 35 #ifdef CONFIG_PCISLAVE 36 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 37 #else 38 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 39 #endif 40 41 #ifndef CONFIG_SYS_CLK_FREQ 42 #define CONFIG_SYS_CLK_FREQ 66000000 43 #endif 44 45 /* 46 * Hardware Reset Configuration Word 47 * if CLKIN is 66MHz, then 48 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 49 */ 50 #define CONFIG_SYS_HRCW_LOW (\ 51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 52 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 53 HRCWL_SVCOD_DIV_2 |\ 54 HRCWL_CSB_TO_CLKIN_6X1 |\ 55 HRCWL_CORE_TO_CSB_1_5X1) 56 57 #ifdef CONFIG_PCISLAVE 58 #define CONFIG_SYS_HRCW_HIGH (\ 59 HRCWH_PCI_AGENT |\ 60 HRCWH_PCI1_ARBITER_DISABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0XFFF00100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_RL_EXT_LEGACY |\ 67 HRCWH_TSEC1M_IN_RGMII |\ 68 HRCWH_TSEC2M_IN_RGMII |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LDP_CLEAR) 71 #else 72 #define CONFIG_SYS_HRCW_HIGH (\ 73 HRCWH_PCI_HOST |\ 74 HRCWH_PCI1_ARBITER_ENABLE |\ 75 HRCWH_CORE_ENABLE |\ 76 HRCWH_FROM_0X00000100 |\ 77 HRCWH_BOOTSEQ_DISABLE |\ 78 HRCWH_SW_WATCHDOG_DISABLE |\ 79 HRCWH_ROM_LOC_LOCAL_16BIT |\ 80 HRCWH_RL_EXT_LEGACY |\ 81 HRCWH_TSEC1M_IN_RGMII |\ 82 HRCWH_TSEC2M_IN_RGMII |\ 83 HRCWH_BIG_ENDIAN |\ 84 HRCWH_LDP_CLEAR) 85 #endif 86 87 /* Arbiter Configuration Register */ 88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 90 91 /* System Priority Control Register */ 92 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 93 94 /* 95 * IP blocks clock configuration 96 */ 97 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 98 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 99 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 100 101 /* 102 * System IO Config 103 */ 104 #define CONFIG_SYS_SICRH 0x00000000 105 #define CONFIG_SYS_SICRL 0x00000000 106 107 /* 108 * Output Buffer Impedance 109 */ 110 #define CONFIG_SYS_OBIR 0x31100000 111 112 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 113 #define CONFIG_BOARD_EARLY_INIT_R 114 #define CONFIG_HWCONFIG 115 116 /* 117 * IMMR new address 118 */ 119 #define CONFIG_SYS_IMMR 0xE0000000 120 121 /* 122 * DDR Setup 123 */ 124 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 126 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 127 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 128 #define CONFIG_SYS_83XX_DDR_USES_CS0 129 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ 130 131 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 132 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 133 134 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 135 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 136 137 #if defined(CONFIG_SPD_EEPROM) 138 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 139 #else 140 /* 141 * Manually set up DDR parameters 142 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 143 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 144 */ 145 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 147 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ 148 | 0x00010000 /* ODT_WR to CSn */ \ 149 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) 150 /* 0x80010202 */ 151 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 152 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 153 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 154 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 155 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 156 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 157 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 158 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 159 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 160 /* 0x00620802 */ 161 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 162 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 163 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 164 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 165 | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 166 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 167 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 168 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 169 /* 0x3935d322 */ 170 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 171 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ 172 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 173 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 174 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 175 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 176 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 177 /* 0x131088c8 */ 178 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 179 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 180 /* 0x03E00100 */ 181 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 182 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 183 #define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ 184 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) 185 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 186 #define CONFIG_SYS_DDR_MODE2 0x00000000 187 #endif 188 189 /* 190 * Memory test 191 */ 192 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 193 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 194 #define CONFIG_SYS_MEMTEST_END 0x00140000 195 196 /* 197 * The reserved memory 198 */ 199 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 200 201 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 202 #define CONFIG_SYS_RAMBOOT 203 #else 204 #undef CONFIG_SYS_RAMBOOT 205 #endif 206 207 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 208 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 209 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 210 211 /* 212 * Initial RAM Base Address Setup 213 */ 214 #define CONFIG_SYS_INIT_RAM_LOCK 1 215 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 216 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ 217 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 219 220 /* 221 * Local Bus Configuration & Clock Setup 222 */ 223 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 224 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 225 #define CONFIG_SYS_LBC_LBCR 0x00000000 226 227 /* 228 * FLASH on the Local Bus 229 */ 230 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 231 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 232 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 233 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 234 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 235 236 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ 237 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 238 239 #define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ 240 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ 241 | BR_V ) /* valid */ 242 #define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ 243 | OR_UPM_XAM \ 244 | OR_GPCM_CSNT \ 245 | OR_GPCM_ACS_DIV2 \ 246 | OR_GPCM_XACS \ 247 | OR_GPCM_SCY_15 \ 248 | OR_GPCM_TRLX \ 249 | OR_GPCM_EHTR \ 250 | OR_GPCM_EAD ) 251 /* 0xFE000FF7 */ 252 253 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 254 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 255 256 #undef CONFIG_SYS_FLASH_CHECKSUM 257 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 258 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 259 260 /* 261 * BCSR on the Local Bus 262 */ 263 #define CONFIG_SYS_BCSR 0xF8000000 264 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ 265 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 266 267 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ 268 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ 269 270 /* 271 * NAND Flash on the Local Bus 272 */ 273 #define CONFIG_CMD_NAND 1 274 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 275 #define CONFIG_SYS_MAX_NAND_DEVICE 1 276 #define CONFIG_NAND_FSL_ELBC 1 277 278 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 279 #define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ 280 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 281 | BR_PS_8 /* Port Size = 8 bit */ \ 282 | BR_MS_FCM /* MSEL = FCM */ \ 283 | BR_V ) /* valid */ 284 #define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ 285 | OR_FCM_BCTLD \ 286 | OR_FCM_CST \ 287 | OR_FCM_CHT \ 288 | OR_FCM_SCY_1 \ 289 | OR_FCM_RST \ 290 | OR_FCM_TRLX \ 291 | OR_FCM_EHTR ) 292 /* 0xFFFF919E */ 293 294 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 295 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 296 297 /* 298 * Serial Port 299 */ 300 #define CONFIG_CONS_INDEX 1 301 #undef CONFIG_SERIAL_SOFTWARE_FIFO 302 #define CONFIG_SYS_NS16550 303 #define CONFIG_SYS_NS16550_SERIAL 304 #define CONFIG_SYS_NS16550_REG_SIZE 1 305 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 306 307 #define CONFIG_SYS_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 309 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 312 313 /* Use the HUSH parser */ 314 #define CONFIG_SYS_HUSH_PARSER 315 #ifdef CONFIG_SYS_HUSH_PARSER 316 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 317 #endif 318 319 /* Pass open firmware flat tree */ 320 #define CONFIG_OF_LIBFDT 1 321 #define CONFIG_OF_BOARD_SETUP 1 322 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 323 324 #define CONFIG_SYS_64BIT_STRTOUL 1 325 #define CONFIG_SYS_64BIT_VSPRINTF 1 326 327 /* I2C */ 328 #define CONFIG_HARD_I2C /* I2C with hardware support */ 329 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 330 #define CONFIG_FSL_I2C 331 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 332 #define CONFIG_SYS_I2C_SLAVE 0x7F 333 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 334 #define CONFIG_SYS_I2C_OFFSET 0x3000 335 #define CONFIG_SYS_I2C2_OFFSET 0x3100 336 337 /* 338 * Config on-board RTC 339 */ 340 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 342 343 /* 344 * General PCI 345 * Addresses are mapped 1-1. 346 */ 347 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 348 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 349 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 350 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 351 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 352 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 353 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 354 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 355 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 356 357 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 358 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 359 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 360 361 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 362 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 363 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 364 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 365 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 366 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 367 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 368 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 369 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 370 371 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 372 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 373 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 374 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 375 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 376 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 377 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 378 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 379 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 380 381 #ifdef CONFIG_PCI 382 #ifndef __ASSEMBLY__ 383 extern int board_pci_host_broken(void); 384 #endif 385 #define CONFIG_PCIE 386 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 387 388 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 389 390 #define CONFIG_NET_MULTI 391 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 392 393 #undef CONFIG_EEPRO100 394 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 395 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 396 #endif /* CONFIG_PCI */ 397 398 #ifndef CONFIG_NET_MULTI 399 #define CONFIG_NET_MULTI 1 400 #endif 401 402 /* 403 * TSEC 404 */ 405 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 406 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 407 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 408 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 409 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 410 411 /* 412 * TSEC ethernet configuration 413 */ 414 #define CONFIG_MII 1 /* MII PHY management */ 415 #define CONFIG_TSEC1 1 416 #define CONFIG_TSEC1_NAME "eTSEC0" 417 #define CONFIG_TSEC2 1 418 #define CONFIG_TSEC2_NAME "eTSEC1" 419 #define TSEC1_PHY_ADDR 2 420 #define TSEC2_PHY_ADDR 3 421 #define TSEC1_PHY_ADDR_SGMII 8 422 #define TSEC2_PHY_ADDR_SGMII 4 423 #define TSEC1_PHYIDX 0 424 #define TSEC2_PHYIDX 0 425 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 426 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427 428 /* Options are: TSEC[0-1] */ 429 #define CONFIG_ETHPRIME "eTSEC1" 430 431 /* SERDES */ 432 #define CONFIG_FSL_SERDES 433 #define CONFIG_FSL_SERDES1 0xe3000 434 #define CONFIG_FSL_SERDES2 0xe3100 435 436 /* 437 * SATA 438 */ 439 #define CONFIG_LIBATA 440 #define CONFIG_FSL_SATA 441 442 #define CONFIG_SYS_SATA_MAX_DEVICE 2 443 #define CONFIG_SATA1 444 #define CONFIG_SYS_SATA1_OFFSET 0x18000 445 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 446 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 447 #define CONFIG_SATA2 448 #define CONFIG_SYS_SATA2_OFFSET 0x19000 449 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 450 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 451 452 #ifdef CONFIG_FSL_SATA 453 #define CONFIG_LBA48 454 #define CONFIG_CMD_SATA 455 #define CONFIG_DOS_PARTITION 456 #define CONFIG_CMD_EXT2 457 #endif 458 459 /* 460 * Environment 461 */ 462 #ifndef CONFIG_SYS_RAMBOOT 463 #define CONFIG_ENV_IS_IN_FLASH 1 464 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 465 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 466 #define CONFIG_ENV_SIZE 0x2000 467 #else 468 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 469 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 470 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 471 #define CONFIG_ENV_SIZE 0x2000 472 #endif 473 474 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 475 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 476 477 /* 478 * BOOTP options 479 */ 480 #define CONFIG_BOOTP_BOOTFILESIZE 481 #define CONFIG_BOOTP_BOOTPATH 482 #define CONFIG_BOOTP_GATEWAY 483 #define CONFIG_BOOTP_HOSTNAME 484 485 486 /* 487 * Command line configuration. 488 */ 489 #include <config_cmd_default.h> 490 491 #define CONFIG_CMD_PING 492 #define CONFIG_CMD_I2C 493 #define CONFIG_CMD_MII 494 #define CONFIG_CMD_DATE 495 496 #if defined(CONFIG_PCI) 497 #define CONFIG_CMD_PCI 498 #endif 499 500 #if defined(CONFIG_SYS_RAMBOOT) 501 #undef CONFIG_CMD_SAVEENV 502 #undef CONFIG_CMD_LOADS 503 #endif 504 505 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 506 507 #undef CONFIG_WATCHDOG /* watchdog disabled */ 508 509 #define CONFIG_MMC 1 510 511 #ifdef CONFIG_MMC 512 #define CONFIG_FSL_ESDHC 513 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 514 #define CONFIG_CMD_MMC 515 #define CONFIG_GENERIC_MMC 516 #define CONFIG_CMD_EXT2 517 #define CONFIG_CMD_FAT 518 #define CONFIG_DOS_PARTITION 519 #endif 520 521 /* 522 * Miscellaneous configurable options 523 */ 524 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 525 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 526 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 527 528 #if defined(CONFIG_CMD_KGDB) 529 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 530 #else 531 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 532 #endif 533 534 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 535 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 536 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 537 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 538 539 /* 540 * For booting Linux, the board info and command line data 541 * have to be in the first 8 MB of memory, since this is 542 * the maximum mapped by the Linux kernel during initialization. 543 */ 544 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 545 546 /* 547 * Core HID Setup 548 */ 549 #define CONFIG_SYS_HID0_INIT 0x000000000 550 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 551 #define CONFIG_SYS_HID2 HID2_HBE 552 553 /* 554 * MMU Setup 555 */ 556 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 557 558 /* DDR: cache cacheable */ 559 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 560 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 561 562 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 563 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 564 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 565 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 566 567 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 568 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 569 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 570 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 571 572 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 573 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 574 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 575 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 576 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 577 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 578 579 /* BCSR: cache-inhibit and guarded */ 580 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \ 581 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 582 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) 583 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 584 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 585 586 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 587 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 588 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 589 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ 590 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 591 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 592 593 /* Stack in dcache: cacheable, no memory coherence */ 594 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) 595 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 596 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 597 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 598 599 #ifdef CONFIG_PCI 600 /* PCI MEM space: cacheable */ 601 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 602 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 603 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 604 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 605 /* PCI MMIO space: cache-inhibit and guarded */ 606 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ 607 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 608 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 609 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 610 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 611 #else 612 #define CONFIG_SYS_IBAT6L (0) 613 #define CONFIG_SYS_IBAT6U (0) 614 #define CONFIG_SYS_IBAT7L (0) 615 #define CONFIG_SYS_IBAT7U (0) 616 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 617 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 618 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 619 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 620 #endif 621 622 /* 623 * Internal Definitions 624 * 625 * Boot Flags 626 */ 627 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 628 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 629 630 #if defined(CONFIG_CMD_KGDB) 631 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 632 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 633 #endif 634 635 /* 636 * Environment Configuration 637 */ 638 639 #define CONFIG_ENV_OVERWRITE 640 641 #if defined(CONFIG_TSEC_ENET) 642 #define CONFIG_HAS_ETH0 643 #define CONFIG_ETHADDR 00:E0:0C:00:83:79 644 #define CONFIG_HAS_ETH1 645 #define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 646 #endif 647 648 #define CONFIG_BAUDRATE 115200 649 650 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 651 652 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 653 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 654 655 #define CONFIG_EXTRA_ENV_SETTINGS \ 656 "netdev=eth0\0" \ 657 "consoledev=ttyS0\0" \ 658 "ramdiskaddr=1000000\0" \ 659 "ramdiskfile=ramfs.83xx\0" \ 660 "fdtaddr=780000\0" \ 661 "fdtfile=mpc8379_mds.dtb\0" \ 662 "" 663 664 #define CONFIG_NFSBOOTCOMMAND \ 665 "setenv bootargs root=/dev/nfs rw " \ 666 "nfsroot=$serverip:$rootpath " \ 667 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 668 "console=$consoledev,$baudrate $othbootargs;" \ 669 "tftp $loadaddr $bootfile;" \ 670 "tftp $fdtaddr $fdtfile;" \ 671 "bootm $loadaddr - $fdtaddr" 672 673 #define CONFIG_RAMBOOTCOMMAND \ 674 "setenv bootargs root=/dev/ram rw " \ 675 "console=$consoledev,$baudrate $othbootargs;" \ 676 "tftp $ramdiskaddr $ramdiskfile;" \ 677 "tftp $loadaddr $bootfile;" \ 678 "tftp $fdtaddr $fdtfile;" \ 679 "bootm $loadaddr $ramdiskaddr $fdtaddr" 680 681 682 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 683 684 #endif /* __CONFIG_H */ 685