1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 #define CONFIG_E300 1 /* E300 family */ 15 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 16 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 17 18 /* 19 * System Clock Setup 20 */ 21 #ifdef CONFIG_PCISLAVE 22 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 23 #else 24 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 25 #endif 26 27 #ifndef CONFIG_SYS_CLK_FREQ 28 #define CONFIG_SYS_CLK_FREQ 66000000 29 #endif 30 31 /* 32 * Hardware Reset Configuration Word 33 * if CLKIN is 66MHz, then 34 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 39 HRCWL_SVCOD_DIV_2 |\ 40 HRCWL_CSB_TO_CLKIN_6X1 |\ 41 HRCWL_CORE_TO_CSB_1_5X1) 42 43 #ifdef CONFIG_PCISLAVE 44 #define CONFIG_SYS_HRCW_HIGH (\ 45 HRCWH_PCI_AGENT |\ 46 HRCWH_PCI1_ARBITER_DISABLE |\ 47 HRCWH_CORE_ENABLE |\ 48 HRCWH_FROM_0XFFF00100 |\ 49 HRCWH_BOOTSEQ_DISABLE |\ 50 HRCWH_SW_WATCHDOG_DISABLE |\ 51 HRCWH_ROM_LOC_LOCAL_16BIT |\ 52 HRCWH_RL_EXT_LEGACY |\ 53 HRCWH_TSEC1M_IN_RGMII |\ 54 HRCWH_TSEC2M_IN_RGMII |\ 55 HRCWH_BIG_ENDIAN |\ 56 HRCWH_LDP_CLEAR) 57 #else 58 #define CONFIG_SYS_HRCW_HIGH (\ 59 HRCWH_PCI_HOST |\ 60 HRCWH_PCI1_ARBITER_ENABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0X00000100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_RL_EXT_LEGACY |\ 67 HRCWH_TSEC1M_IN_RGMII |\ 68 HRCWH_TSEC2M_IN_RGMII |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LDP_CLEAR) 71 #endif 72 73 /* Arbiter Configuration Register */ 74 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 75 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 76 77 /* System Priority Control Register */ 78 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 79 80 /* 81 * IP blocks clock configuration 82 */ 83 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 84 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 85 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 86 87 /* 88 * System IO Config 89 */ 90 #define CONFIG_SYS_SICRH 0x00000000 91 #define CONFIG_SYS_SICRL 0x00000000 92 93 /* 94 * Output Buffer Impedance 95 */ 96 #define CONFIG_SYS_OBIR 0x31100000 97 98 #define CONFIG_HWCONFIG 99 100 /* 101 * IMMR new address 102 */ 103 #define CONFIG_SYS_IMMR 0xE0000000 104 105 /* 106 * DDR Setup 107 */ 108 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 110 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 112 #define CONFIG_SYS_83XX_DDR_USES_CS0 113 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 114 | DDRCDR_ODT \ 115 | DDRCDR_Q_DRN) 116 /* 0x80080001 */ /* ODT 150ohm on SoC */ 117 118 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 119 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 120 121 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 122 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 123 124 #if defined(CONFIG_SPD_EEPROM) 125 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 126 #else 127 /* 128 * Manually set up DDR parameters 129 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 130 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 131 */ 132 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 134 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 135 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 136 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 137 | CSCONFIG_ROW_BIT_14 \ 138 | CSCONFIG_COL_BIT_10) 139 /* 0x80010202 */ 140 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 141 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 142 | (0 << TIMING_CFG0_WRT_SHIFT) \ 143 | (0 << TIMING_CFG0_RRT_SHIFT) \ 144 | (0 << TIMING_CFG0_WWT_SHIFT) \ 145 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 146 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 147 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 148 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 149 /* 0x00620802 */ 150 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 151 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 152 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 153 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 154 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 155 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 156 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 157 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 158 /* 0x3935d322 */ 159 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 160 | (6 << TIMING_CFG2_CPO_SHIFT) \ 161 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 162 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 163 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 164 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 165 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 166 /* 0x131088c8 */ 167 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 168 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 169 /* 0x03E00100 */ 170 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 171 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 172 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 173 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 174 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 175 #define CONFIG_SYS_DDR_MODE2 0x00000000 176 #endif 177 178 /* 179 * Memory test 180 */ 181 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 182 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 183 #define CONFIG_SYS_MEMTEST_END 0x00140000 184 185 /* 186 * The reserved memory 187 */ 188 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 189 190 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 191 #define CONFIG_SYS_RAMBOOT 192 #else 193 #undef CONFIG_SYS_RAMBOOT 194 #endif 195 196 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 197 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 198 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 199 200 /* 201 * Initial RAM Base Address Setup 202 */ 203 #define CONFIG_SYS_INIT_RAM_LOCK 1 204 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 205 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 206 #define CONFIG_SYS_GBL_DATA_OFFSET \ 207 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 208 209 /* 210 * Local Bus Configuration & Clock Setup 211 */ 212 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 213 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 214 #define CONFIG_SYS_LBC_LBCR 0x00000000 215 #define CONFIG_FSL_ELBC 1 216 217 /* 218 * FLASH on the Local Bus 219 */ 220 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 221 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 222 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 223 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 224 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 225 226 /* Window base at flash base */ 227 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 228 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 229 230 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 231 | BR_PS_16 /* 16 bit port */ \ 232 | BR_MS_GPCM /* MSEL = GPCM */ \ 233 | BR_V) /* valid */ 234 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 235 | OR_UPM_XAM \ 236 | OR_GPCM_CSNT \ 237 | OR_GPCM_ACS_DIV2 \ 238 | OR_GPCM_XACS \ 239 | OR_GPCM_SCY_15 \ 240 | OR_GPCM_TRLX_SET \ 241 | OR_GPCM_EHTR_SET \ 242 | OR_GPCM_EAD) 243 /* 0xFE000FF7 */ 244 245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 246 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 247 248 #undef CONFIG_SYS_FLASH_CHECKSUM 249 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 250 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 251 252 /* 253 * BCSR on the Local Bus 254 */ 255 #define CONFIG_SYS_BCSR 0xF8000000 256 /* Access window base at BCSR base */ 257 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 258 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 259 260 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 261 | BR_PS_8 \ 262 | BR_MS_GPCM \ 263 | BR_V) 264 /* 0xF8000801 */ 265 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 266 | OR_GPCM_XAM \ 267 | OR_GPCM_CSNT \ 268 | OR_GPCM_XACS \ 269 | OR_GPCM_SCY_15 \ 270 | OR_GPCM_TRLX_SET \ 271 | OR_GPCM_EHTR_SET \ 272 | OR_GPCM_EAD) 273 /* 0xFFFFE9F7 */ 274 275 /* 276 * NAND Flash on the Local Bus 277 */ 278 #define CONFIG_SYS_MAX_NAND_DEVICE 1 279 #define CONFIG_NAND_FSL_ELBC 1 280 281 #define CONFIG_SYS_NAND_BASE 0xE0600000 282 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 283 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 284 | BR_PS_8 /* 8 bit port */ \ 285 | BR_MS_FCM /* MSEL = FCM */ \ 286 | BR_V) /* valid */ 287 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 288 | OR_FCM_BCTLD \ 289 | OR_FCM_CST \ 290 | OR_FCM_CHT \ 291 | OR_FCM_SCY_1 \ 292 | OR_FCM_RST \ 293 | OR_FCM_TRLX \ 294 | OR_FCM_EHTR) 295 /* 0xFFFF919E */ 296 297 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 298 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 299 300 /* 301 * Serial Port 302 */ 303 #define CONFIG_SYS_NS16550_SERIAL 304 #define CONFIG_SYS_NS16550_REG_SIZE 1 305 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 306 307 #define CONFIG_SYS_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 309 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 312 313 /* I2C */ 314 #define CONFIG_SYS_I2C 315 #define CONFIG_SYS_I2C_FSL 316 #define CONFIG_SYS_FSL_I2C_SPEED 400000 317 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 318 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 319 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 320 321 /* 322 * Config on-board RTC 323 */ 324 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 325 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 326 327 /* 328 * General PCI 329 * Addresses are mapped 1-1. 330 */ 331 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 332 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 333 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 334 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 335 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 336 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 337 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 338 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 339 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 340 341 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 342 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 343 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 344 345 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 346 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 347 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 348 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 349 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 350 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 351 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 352 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 353 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 354 355 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 356 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 357 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 358 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 359 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 360 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 361 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 362 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 363 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 364 365 #ifdef CONFIG_PCI 366 #define CONFIG_PCI_INDIRECT_BRIDGE 367 #ifndef __ASSEMBLY__ 368 extern int board_pci_host_broken(void); 369 #endif 370 #define CONFIG_PCIE 371 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 372 373 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 374 #define CONFIG_USB_EHCI_FSL 375 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 376 377 #undef CONFIG_EEPRO100 378 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 379 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 380 #endif /* CONFIG_PCI */ 381 382 /* 383 * TSEC 384 */ 385 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 386 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 387 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 388 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 389 390 /* 391 * TSEC ethernet configuration 392 */ 393 #define CONFIG_MII 1 /* MII PHY management */ 394 #define CONFIG_TSEC1 1 395 #define CONFIG_TSEC1_NAME "eTSEC0" 396 #define CONFIG_TSEC2 1 397 #define CONFIG_TSEC2_NAME "eTSEC1" 398 #define TSEC1_PHY_ADDR 2 399 #define TSEC2_PHY_ADDR 3 400 #define TSEC1_PHY_ADDR_SGMII 8 401 #define TSEC2_PHY_ADDR_SGMII 4 402 #define TSEC1_PHYIDX 0 403 #define TSEC2_PHYIDX 0 404 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 405 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 406 407 /* Options are: TSEC[0-1] */ 408 #define CONFIG_ETHPRIME "eTSEC1" 409 410 /* SERDES */ 411 #define CONFIG_FSL_SERDES 412 #define CONFIG_FSL_SERDES1 0xe3000 413 #define CONFIG_FSL_SERDES2 0xe3100 414 415 /* 416 * SATA 417 */ 418 #define CONFIG_SYS_SATA_MAX_DEVICE 2 419 #define CONFIG_SATA1 420 #define CONFIG_SYS_SATA1_OFFSET 0x18000 421 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 422 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 423 #define CONFIG_SATA2 424 #define CONFIG_SYS_SATA2_OFFSET 0x19000 425 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 426 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 427 428 #ifdef CONFIG_FSL_SATA 429 #define CONFIG_LBA48 430 #endif 431 432 /* 433 * Environment 434 */ 435 #ifndef CONFIG_SYS_RAMBOOT 436 #define CONFIG_ENV_ADDR \ 437 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 438 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 439 #define CONFIG_ENV_SIZE 0x2000 440 #else 441 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 442 #define CONFIG_ENV_SIZE 0x2000 443 #endif 444 445 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 446 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 447 448 /* 449 * BOOTP options 450 */ 451 #define CONFIG_BOOTP_BOOTFILESIZE 452 453 /* 454 * Command line configuration. 455 */ 456 457 #undef CONFIG_WATCHDOG /* watchdog disabled */ 458 459 #ifdef CONFIG_MMC 460 #define CONFIG_FSL_ESDHC_PIN_MUX 461 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 462 #endif 463 464 /* 465 * Miscellaneous configurable options 466 */ 467 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 468 469 /* 470 * For booting Linux, the board info and command line data 471 * have to be in the first 256 MB of memory, since this is 472 * the maximum mapped by the Linux kernel during initialization. 473 */ 474 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 475 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 476 477 /* 478 * Core HID Setup 479 */ 480 #define CONFIG_SYS_HID0_INIT 0x000000000 481 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 482 HID0_ENABLE_INSTRUCTION_CACHE) 483 #define CONFIG_SYS_HID2 HID2_HBE 484 485 /* 486 * MMU Setup 487 */ 488 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 489 490 /* DDR: cache cacheable */ 491 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 492 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 493 494 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 495 | BATL_PP_RW \ 496 | BATL_MEMCOHERENCE) 497 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 498 | BATU_BL_256M \ 499 | BATU_VS \ 500 | BATU_VP) 501 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 502 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 503 504 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 505 | BATL_PP_RW \ 506 | BATL_MEMCOHERENCE) 507 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 508 | BATU_BL_256M \ 509 | BATU_VS \ 510 | BATU_VP) 511 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 512 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 513 514 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 515 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 516 | BATL_PP_RW \ 517 | BATL_CACHEINHIBIT \ 518 | BATL_GUARDEDSTORAGE) 519 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 520 | BATU_BL_8M \ 521 | BATU_VS \ 522 | BATU_VP) 523 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 524 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 525 526 /* BCSR: cache-inhibit and guarded */ 527 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 528 | BATL_PP_RW \ 529 | BATL_CACHEINHIBIT \ 530 | BATL_GUARDEDSTORAGE) 531 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 532 | BATU_BL_128K \ 533 | BATU_VS \ 534 | BATU_VP) 535 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 536 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 537 538 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 539 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 540 | BATL_PP_RW \ 541 | BATL_MEMCOHERENCE) 542 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 543 | BATU_BL_32M \ 544 | BATU_VS \ 545 | BATU_VP) 546 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 547 | BATL_PP_RW \ 548 | BATL_CACHEINHIBIT \ 549 | BATL_GUARDEDSTORAGE) 550 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 551 552 /* Stack in dcache: cacheable, no memory coherence */ 553 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 554 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 555 | BATU_BL_128K \ 556 | BATU_VS \ 557 | BATU_VP) 558 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 559 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 560 561 #ifdef CONFIG_PCI 562 /* PCI MEM space: cacheable */ 563 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 564 | BATL_PP_RW \ 565 | BATL_MEMCOHERENCE) 566 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 567 | BATU_BL_256M \ 568 | BATU_VS \ 569 | BATU_VP) 570 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 571 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 572 /* PCI MMIO space: cache-inhibit and guarded */ 573 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 574 | BATL_PP_RW \ 575 | BATL_CACHEINHIBIT \ 576 | BATL_GUARDEDSTORAGE) 577 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 578 | BATU_BL_256M \ 579 | BATU_VS \ 580 | BATU_VP) 581 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 582 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 583 #else 584 #define CONFIG_SYS_IBAT6L (0) 585 #define CONFIG_SYS_IBAT6U (0) 586 #define CONFIG_SYS_IBAT7L (0) 587 #define CONFIG_SYS_IBAT7U (0) 588 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 589 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 590 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 591 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 592 #endif 593 594 #if defined(CONFIG_CMD_KGDB) 595 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 596 #endif 597 598 /* 599 * Environment Configuration 600 */ 601 602 #define CONFIG_ENV_OVERWRITE 603 604 #if defined(CONFIG_TSEC_ENET) 605 #define CONFIG_HAS_ETH0 606 #define CONFIG_HAS_ETH1 607 #endif 608 609 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 610 611 #define CONFIG_EXTRA_ENV_SETTINGS \ 612 "netdev=eth0\0" \ 613 "consoledev=ttyS0\0" \ 614 "ramdiskaddr=1000000\0" \ 615 "ramdiskfile=ramfs.83xx\0" \ 616 "fdtaddr=780000\0" \ 617 "fdtfile=mpc8379_mds.dtb\0" \ 618 "" 619 620 #define CONFIG_NFSBOOTCOMMAND \ 621 "setenv bootargs root=/dev/nfs rw " \ 622 "nfsroot=$serverip:$rootpath " \ 623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 624 "$netdev:off " \ 625 "console=$consoledev,$baudrate $othbootargs;" \ 626 "tftp $loadaddr $bootfile;" \ 627 "tftp $fdtaddr $fdtfile;" \ 628 "bootm $loadaddr - $fdtaddr" 629 630 #define CONFIG_RAMBOOTCOMMAND \ 631 "setenv bootargs root=/dev/ram rw " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "tftp $ramdiskaddr $ramdiskfile;" \ 634 "tftp $loadaddr $bootfile;" \ 635 "tftp $fdtaddr $fdtfile;" \ 636 "bootm $loadaddr $ramdiskaddr $fdtaddr" 637 638 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 639 640 #endif /* __CONFIG_H */ 641