1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #ifndef __CONFIG_H 22 #define __CONFIG_H 23 24 #undef DEBUG 25 26 /* 27 * High Level Configuration Options 28 */ 29 #define CONFIG_E300 1 /* E300 family */ 30 #define CONFIG_MPC83XX 1 /* MPC83XX family */ 31 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ 32 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 33 34 /* 35 * System Clock Setup 36 */ 37 #ifdef CONFIG_PCISLAVE 38 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 39 #else 40 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 41 #endif 42 43 #ifndef CONFIG_SYS_CLK_FREQ 44 #define CONFIG_SYS_CLK_FREQ 66000000 45 #endif 46 47 /* 48 * Hardware Reset Configuration Word 49 * if CLKIN is 66MHz, then 50 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 51 */ 52 #define CFG_HRCW_LOW (\ 53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 54 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 55 HRCWL_SVCOD_DIV_2 |\ 56 HRCWL_CSB_TO_CLKIN_6X1 |\ 57 HRCWL_CORE_TO_CSB_1_5X1) 58 59 #ifdef CONFIG_PCISLAVE 60 #define CFG_HRCW_HIGH (\ 61 HRCWH_PCI_AGENT |\ 62 HRCWH_PCI1_ARBITER_DISABLE |\ 63 HRCWH_CORE_ENABLE |\ 64 HRCWH_FROM_0XFFF00100 |\ 65 HRCWH_BOOTSEQ_DISABLE |\ 66 HRCWH_SW_WATCHDOG_DISABLE |\ 67 HRCWH_ROM_LOC_LOCAL_16BIT |\ 68 HRCWH_RL_EXT_LEGACY |\ 69 HRCWH_TSEC1M_IN_RGMII |\ 70 HRCWH_TSEC2M_IN_RGMII |\ 71 HRCWH_BIG_ENDIAN |\ 72 HRCWH_LDP_CLEAR) 73 #else 74 #define CFG_HRCW_HIGH (\ 75 HRCWH_PCI_HOST |\ 76 HRCWH_PCI1_ARBITER_ENABLE |\ 77 HRCWH_CORE_ENABLE |\ 78 HRCWH_FROM_0X00000100 |\ 79 HRCWH_BOOTSEQ_DISABLE |\ 80 HRCWH_SW_WATCHDOG_DISABLE |\ 81 HRCWH_ROM_LOC_LOCAL_16BIT |\ 82 HRCWH_RL_EXT_LEGACY |\ 83 HRCWH_TSEC1M_IN_RGMII |\ 84 HRCWH_TSEC2M_IN_RGMII |\ 85 HRCWH_BIG_ENDIAN |\ 86 HRCWH_LDP_CLEAR) 87 #endif 88 89 /* 90 * eTSEC Clock Config 91 */ 92 #define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 93 #define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 94 95 /* 96 * System IO Config 97 */ 98 #define CFG_SICRH 0x00000000 99 #define CFG_SICRL 0x00000000 100 101 /* 102 * Output Buffer Impedance 103 */ 104 #define CFG_OBIR 0x31100000 105 106 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 107 #define CONFIG_BOARD_EARLY_INIT_R 108 109 /* 110 * IMMR new address 111 */ 112 #define CFG_IMMR 0xE0000000 113 114 /* 115 * DDR Setup 116 */ 117 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ 118 #define CFG_SDRAM_BASE CFG_DDR_BASE 119 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 120 #define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 121 #define CFG_83XX_DDR_USES_CS0 122 #define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ 123 124 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 125 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 126 127 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 128 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 129 130 #if defined(CONFIG_SPD_EEPROM) 131 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 132 #else 133 /* 134 * Manually set up DDR parameters 135 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 136 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 137 */ 138 #define CFG_DDR_SIZE 512 /* MB */ 139 #define CFG_DDR_CS0_BNDS 0x0000001f 140 #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ 141 | 0x00010000 /* ODT_WR to CSn */ \ 142 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) 143 /* 0x80010202 */ 144 #define CFG_DDR_TIMING_3 0x00000000 145 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 146 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 147 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ 148 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ 149 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 150 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 151 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 152 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 153 /* 0x00620802 */ 154 #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ 155 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 156 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ 157 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 158 | (13 << TIMING_CFG1_REFREC_SHIFT ) \ 159 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ 160 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 161 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 162 /* 0x3935d322 */ 163 #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 164 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ 165 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 166 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 167 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 168 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 169 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 170 /* 0x131088c8 */ 171 #define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 172 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 173 /* 0x03E00100 */ 174 #define CFG_DDR_SDRAM_CFG 0x43000000 175 #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 176 #define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ 177 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) 178 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 179 #define CFG_DDR_MODE2 0x00000000 180 #endif 181 182 /* 183 * Memory test 184 */ 185 #undef CFG_DRAM_TEST /* memory test, takes time */ 186 #define CFG_MEMTEST_START 0x00040000 /* memtest region */ 187 #define CFG_MEMTEST_END 0x00140000 188 189 /* 190 * The reserved memory 191 */ 192 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 193 194 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 195 #define CFG_RAMBOOT 196 #else 197 #undef CFG_RAMBOOT 198 #endif 199 200 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 201 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 202 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 203 204 /* 205 * Initial RAM Base Address Setup 206 */ 207 #define CFG_INIT_RAM_LOCK 1 208 #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 209 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ 210 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 211 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 212 213 /* 214 * Local Bus Configuration & Clock Setup 215 */ 216 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) 217 #define CFG_LBC_LBCR 0x00000000 218 219 /* 220 * FLASH on the Local Bus 221 */ 222 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 223 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 224 #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ 225 #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ 226 227 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ 228 #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ 229 230 #define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ 231 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ 232 | BR_V ) /* valid */ 233 #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ 234 | OR_UPM_XAM \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_ACS_0b11 \ 237 | OR_GPCM_XACS \ 238 | OR_GPCM_SCY_15 \ 239 | OR_GPCM_TRLX \ 240 | OR_GPCM_EHTR \ 241 | OR_GPCM_EAD ) 242 /* 0xFE000FF7 */ 243 244 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ 245 #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ 246 247 #undef CFG_FLASH_CHECKSUM 248 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 249 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 250 251 /* 252 * BCSR on the Local Bus 253 */ 254 #define CFG_BCSR 0xF8000000 255 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ 256 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ 257 258 #define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ 259 #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ 260 261 /* 262 * NAND Flash on the Local Bus 263 */ 264 #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ 265 #define CFG_BR3_PRELIM ( CFG_NAND_BASE \ 266 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 267 | BR_PS_8 /* Port Size = 8 bit */ \ 268 | BR_MS_FCM /* MSEL = FCM */ \ 269 | BR_V ) /* valid */ 270 #define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ 271 | OR_FCM_CSCT \ 272 | OR_FCM_CST \ 273 | OR_FCM_CHT \ 274 | OR_FCM_SCY_1 \ 275 | OR_FCM_TRLX \ 276 | OR_FCM_EHTR ) 277 /* 0xFFFF8396 */ 278 279 #define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE 280 #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ 281 282 /* 283 * Serial Port 284 */ 285 #define CONFIG_CONS_INDEX 1 286 #undef CONFIG_SERIAL_SOFTWARE_FIFO 287 #define CFG_NS16550 288 #define CFG_NS16550_SERIAL 289 #define CFG_NS16550_REG_SIZE 1 290 #define CFG_NS16550_CLK get_bus_freq(0) 291 292 #define CFG_BAUDRATE_TABLE \ 293 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 294 295 #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) 296 #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) 297 298 /* Use the HUSH parser */ 299 #define CFG_HUSH_PARSER 300 #ifdef CFG_HUSH_PARSER 301 #define CFG_PROMPT_HUSH_PS2 "> " 302 #endif 303 304 /* Pass open firmware flat tree */ 305 #define CONFIG_OF_LIBFDT 1 306 #define CONFIG_OF_BOARD_SETUP 1 307 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 308 309 /* I2C */ 310 #define CONFIG_HARD_I2C /* I2C with hardware support */ 311 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 312 #define CONFIG_FSL_I2C 313 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 314 #define CFG_I2C_SLAVE 0x7F 315 #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ 316 #define CFG_I2C_OFFSET 0x3000 317 #define CFG_I2C2_OFFSET 0x3100 318 319 /* 320 * Config on-board RTC 321 */ 322 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 323 #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 324 325 /* 326 * General PCI 327 * Addresses are mapped 1-1. 328 */ 329 #define CFG_PCI_MEM_BASE 0x80000000 330 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE 331 #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ 332 #define CFG_PCI_MMIO_BASE 0x90000000 333 #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE 334 #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ 335 #define CFG_PCI_IO_BASE 0xE0300000 336 #define CFG_PCI_IO_PHYS 0xE0300000 337 #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ 338 339 #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE 340 #define CFG_PCI_SLV_MEM_BUS 0x00000000 341 #define CFG_PCI_SLV_MEM_SIZE 0x80000000 342 343 #ifdef CONFIG_PCI 344 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ 345 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 346 347 #define CONFIG_NET_MULTI 348 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 349 350 #undef CONFIG_EEPRO100 351 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 352 #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 353 #endif /* CONFIG_PCI */ 354 355 #ifndef CONFIG_NET_MULTI 356 #define CONFIG_NET_MULTI 1 357 #endif 358 359 /* 360 * TSEC 361 */ 362 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 363 #define CFG_TSEC1_OFFSET 0x24000 364 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) 365 #define CFG_TSEC2_OFFSET 0x25000 366 #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) 367 368 /* 369 * TSEC ethernet configuration 370 */ 371 #define CONFIG_MII 1 /* MII PHY management */ 372 #define CONFIG_TSEC1 1 373 #define CONFIG_TSEC1_NAME "eTSEC0" 374 #define CONFIG_TSEC2 1 375 #define CONFIG_TSEC2_NAME "eTSEC1" 376 #define TSEC1_PHY_ADDR 2 377 #define TSEC2_PHY_ADDR 3 378 #define TSEC1_PHYIDX 0 379 #define TSEC2_PHYIDX 0 380 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 381 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 382 383 /* Options are: TSEC[0-1] */ 384 #define CONFIG_ETHPRIME "eTSEC1" 385 386 /* 387 * Environment 388 */ 389 #ifndef CFG_RAMBOOT 390 #define CFG_ENV_IS_IN_FLASH 1 391 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 392 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 393 #define CFG_ENV_SIZE 0x2000 394 #else 395 #define CFG_NO_FLASH 1 /* Flash is not usable now */ 396 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 397 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 398 #define CFG_ENV_SIZE 0x2000 399 #endif 400 401 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 402 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 403 404 /* 405 * BOOTP options 406 */ 407 #define CONFIG_BOOTP_BOOTFILESIZE 408 #define CONFIG_BOOTP_BOOTPATH 409 #define CONFIG_BOOTP_GATEWAY 410 #define CONFIG_BOOTP_HOSTNAME 411 412 413 /* 414 * Command line configuration. 415 */ 416 #include <config_cmd_default.h> 417 418 #define CONFIG_CMD_PING 419 #define CONFIG_CMD_I2C 420 #define CONFIG_CMD_MII 421 #define CONFIG_CMD_DATE 422 423 #if defined(CONFIG_PCI) 424 #define CONFIG_CMD_PCI 425 #endif 426 427 #if defined(CFG_RAMBOOT) 428 #undef CONFIG_CMD_ENV 429 #undef CONFIG_CMD_LOADS 430 #endif 431 432 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 433 434 #undef CONFIG_WATCHDOG /* watchdog disabled */ 435 436 /* 437 * Miscellaneous configurable options 438 */ 439 #define CFG_LONGHELP /* undef to save memory */ 440 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 441 #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 442 443 #if defined(CONFIG_CMD_KGDB) 444 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 445 #else 446 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 447 #endif 448 449 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 450 #define CFG_MAXARGS 16 /* max number of command args */ 451 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 452 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 453 454 /* 455 * For booting Linux, the board info and command line data 456 * have to be in the first 8 MB of memory, since this is 457 * the maximum mapped by the Linux kernel during initialization. 458 */ 459 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 460 461 /* 462 * Core HID Setup 463 */ 464 #define CFG_HID0_INIT 0x000000000 465 #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 466 #define CFG_HID2 HID2_HBE 467 468 /* 469 * MMU Setup 470 */ 471 472 /* DDR: cache cacheable */ 473 #define CFG_SDRAM_LOWER CFG_SDRAM_BASE 474 #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) 475 476 #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) 477 #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) 478 #define CFG_DBAT0L CFG_IBAT0L 479 #define CFG_DBAT0U CFG_IBAT0U 480 481 #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) 482 #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) 483 #define CFG_DBAT1L CFG_IBAT1L 484 #define CFG_DBAT1U CFG_IBAT1U 485 486 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 487 #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ 488 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 489 #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) 490 #define CFG_DBAT2L CFG_IBAT2L 491 #define CFG_DBAT2U CFG_IBAT2U 492 493 /* BCSR: cache-inhibit and guarded */ 494 #define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ 495 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 496 #define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) 497 #define CFG_DBAT3L CFG_IBAT3L 498 #define CFG_DBAT3U CFG_IBAT3U 499 500 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 501 #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 502 #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) 503 #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ 504 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 505 #define CFG_DBAT4U CFG_IBAT4U 506 507 /* Stack in dcache: cacheable, no memory coherence */ 508 #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) 509 #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 510 #define CFG_DBAT5L CFG_IBAT5L 511 #define CFG_DBAT5U CFG_IBAT5U 512 513 #ifdef CONFIG_PCI 514 /* PCI MEM space: cacheable */ 515 #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 516 #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 517 #define CFG_DBAT6L CFG_IBAT6L 518 #define CFG_DBAT6U CFG_IBAT6U 519 /* PCI MMIO space: cache-inhibit and guarded */ 520 #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ 521 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 522 #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 523 #define CFG_DBAT7L CFG_IBAT7L 524 #define CFG_DBAT7U CFG_IBAT7U 525 #else 526 #define CFG_IBAT6L (0) 527 #define CFG_IBAT6U (0) 528 #define CFG_IBAT7L (0) 529 #define CFG_IBAT7U (0) 530 #define CFG_DBAT6L CFG_IBAT6L 531 #define CFG_DBAT6U CFG_IBAT6U 532 #define CFG_DBAT7L CFG_IBAT7L 533 #define CFG_DBAT7U CFG_IBAT7U 534 #endif 535 536 /* 537 * Internal Definitions 538 * 539 * Boot Flags 540 */ 541 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 542 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 543 544 #if defined(CONFIG_CMD_KGDB) 545 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 546 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 547 #endif 548 549 /* 550 * Environment Configuration 551 */ 552 553 #define CONFIG_ENV_OVERWRITE 554 555 #if defined(CONFIG_TSEC_ENET) 556 #define CONFIG_HAS_ETH0 557 #define CONFIG_ETHADDR 00:E0:0C:00:83:79 558 #define CONFIG_HAS_ETH1 559 #define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 560 #endif 561 562 #define CONFIG_BAUDRATE 115200 563 564 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 565 566 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 567 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 568 569 #define CONFIG_EXTRA_ENV_SETTINGS \ 570 "netdev=eth0\0" \ 571 "consoledev=ttyS0\0" \ 572 "ramdiskaddr=1000000\0" \ 573 "ramdiskfile=ramfs.83xx\0" \ 574 "fdtaddr=400000\0" \ 575 "fdtfile=mpc837xemds.dtb\0" \ 576 "" 577 578 #define CONFIG_NFSBOOTCOMMAND \ 579 "setenv bootargs root=/dev/nfs rw " \ 580 "nfsroot=$serverip:$rootpath " \ 581 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 582 "console=$consoledev,$baudrate $othbootargs;" \ 583 "tftp $loadaddr $bootfile;" \ 584 "tftp $fdtaddr $fdtfile;" \ 585 "bootm $loadaddr - $fdtaddr" 586 587 #define CONFIG_RAMBOOTCOMMAND \ 588 "setenv bootargs root=/dev/ram rw " \ 589 "console=$consoledev,$baudrate $othbootargs;" \ 590 "tftp $ramdiskaddr $ramdiskfile;" \ 591 "tftp $loadaddr $bootfile;" \ 592 "tftp $fdtaddr $fdtfile;" \ 593 "bootm $loadaddr $ramdiskaddr $fdtaddr" 594 595 596 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 597 598 #endif /* __CONFIG_H */ 599