1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 #define CONFIG_E300 1 /* E300 family */ 15 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 16 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 17 18 /* 19 * System Clock Setup 20 */ 21 #ifdef CONFIG_PCISLAVE 22 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 23 #else 24 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 25 #endif 26 27 #ifndef CONFIG_SYS_CLK_FREQ 28 #define CONFIG_SYS_CLK_FREQ 66000000 29 #endif 30 31 /* 32 * Hardware Reset Configuration Word 33 * if CLKIN is 66MHz, then 34 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 35 */ 36 #define CONFIG_SYS_HRCW_LOW (\ 37 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 38 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 39 HRCWL_SVCOD_DIV_2 |\ 40 HRCWL_CSB_TO_CLKIN_6X1 |\ 41 HRCWL_CORE_TO_CSB_1_5X1) 42 43 #ifdef CONFIG_PCISLAVE 44 #define CONFIG_SYS_HRCW_HIGH (\ 45 HRCWH_PCI_AGENT |\ 46 HRCWH_PCI1_ARBITER_DISABLE |\ 47 HRCWH_CORE_ENABLE |\ 48 HRCWH_FROM_0XFFF00100 |\ 49 HRCWH_BOOTSEQ_DISABLE |\ 50 HRCWH_SW_WATCHDOG_DISABLE |\ 51 HRCWH_ROM_LOC_LOCAL_16BIT |\ 52 HRCWH_RL_EXT_LEGACY |\ 53 HRCWH_TSEC1M_IN_RGMII |\ 54 HRCWH_TSEC2M_IN_RGMII |\ 55 HRCWH_BIG_ENDIAN |\ 56 HRCWH_LDP_CLEAR) 57 #else 58 #define CONFIG_SYS_HRCW_HIGH (\ 59 HRCWH_PCI_HOST |\ 60 HRCWH_PCI1_ARBITER_ENABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0X00000100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_RL_EXT_LEGACY |\ 67 HRCWH_TSEC1M_IN_RGMII |\ 68 HRCWH_TSEC2M_IN_RGMII |\ 69 HRCWH_BIG_ENDIAN |\ 70 HRCWH_LDP_CLEAR) 71 #endif 72 73 /* Arbiter Configuration Register */ 74 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 75 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 76 77 /* System Priority Control Register */ 78 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 79 80 /* 81 * IP blocks clock configuration 82 */ 83 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 84 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 85 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 86 87 /* 88 * System IO Config 89 */ 90 #define CONFIG_SYS_SICRH 0x00000000 91 #define CONFIG_SYS_SICRL 0x00000000 92 93 /* 94 * Output Buffer Impedance 95 */ 96 #define CONFIG_SYS_OBIR 0x31100000 97 98 #define CONFIG_BOARD_EARLY_INIT_R 99 #define CONFIG_HWCONFIG 100 101 /* 102 * IMMR new address 103 */ 104 #define CONFIG_SYS_IMMR 0xE0000000 105 106 /* 107 * DDR Setup 108 */ 109 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 110 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 111 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 112 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 113 #define CONFIG_SYS_83XX_DDR_USES_CS0 114 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 115 | DDRCDR_ODT \ 116 | DDRCDR_Q_DRN) 117 /* 0x80080001 */ /* ODT 150ohm on SoC */ 118 119 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 120 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 121 122 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 123 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 124 125 #if defined(CONFIG_SPD_EEPROM) 126 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 127 #else 128 /* 129 * Manually set up DDR parameters 130 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 131 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 132 */ 133 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 134 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 135 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 136 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 137 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 138 | CSCONFIG_ROW_BIT_14 \ 139 | CSCONFIG_COL_BIT_10) 140 /* 0x80010202 */ 141 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 142 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 143 | (0 << TIMING_CFG0_WRT_SHIFT) \ 144 | (0 << TIMING_CFG0_RRT_SHIFT) \ 145 | (0 << TIMING_CFG0_WWT_SHIFT) \ 146 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 147 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 148 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 149 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 150 /* 0x00620802 */ 151 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 152 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 153 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 154 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 155 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 156 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 157 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 158 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 159 /* 0x3935d322 */ 160 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 161 | (6 << TIMING_CFG2_CPO_SHIFT) \ 162 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 163 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 164 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 165 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 166 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 167 /* 0x131088c8 */ 168 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 169 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 170 /* 0x03E00100 */ 171 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 172 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 173 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 174 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 175 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 176 #define CONFIG_SYS_DDR_MODE2 0x00000000 177 #endif 178 179 /* 180 * Memory test 181 */ 182 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 183 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 184 #define CONFIG_SYS_MEMTEST_END 0x00140000 185 186 /* 187 * The reserved memory 188 */ 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 190 191 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 192 #define CONFIG_SYS_RAMBOOT 193 #else 194 #undef CONFIG_SYS_RAMBOOT 195 #endif 196 197 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 198 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 199 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 200 201 /* 202 * Initial RAM Base Address Setup 203 */ 204 #define CONFIG_SYS_INIT_RAM_LOCK 1 205 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 206 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 207 #define CONFIG_SYS_GBL_DATA_OFFSET \ 208 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 209 210 /* 211 * Local Bus Configuration & Clock Setup 212 */ 213 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 214 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 215 #define CONFIG_SYS_LBC_LBCR 0x00000000 216 #define CONFIG_FSL_ELBC 1 217 218 /* 219 * FLASH on the Local Bus 220 */ 221 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 222 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 223 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 224 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 225 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 226 227 /* Window base at flash base */ 228 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 229 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 230 231 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 232 | BR_PS_16 /* 16 bit port */ \ 233 | BR_MS_GPCM /* MSEL = GPCM */ \ 234 | BR_V) /* valid */ 235 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 236 | OR_UPM_XAM \ 237 | OR_GPCM_CSNT \ 238 | OR_GPCM_ACS_DIV2 \ 239 | OR_GPCM_XACS \ 240 | OR_GPCM_SCY_15 \ 241 | OR_GPCM_TRLX_SET \ 242 | OR_GPCM_EHTR_SET \ 243 | OR_GPCM_EAD) 244 /* 0xFE000FF7 */ 245 246 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 247 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 248 249 #undef CONFIG_SYS_FLASH_CHECKSUM 250 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 251 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 252 253 /* 254 * BCSR on the Local Bus 255 */ 256 #define CONFIG_SYS_BCSR 0xF8000000 257 /* Access window base at BCSR base */ 258 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 259 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 260 261 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 262 | BR_PS_8 \ 263 | BR_MS_GPCM \ 264 | BR_V) 265 /* 0xF8000801 */ 266 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 267 | OR_GPCM_XAM \ 268 | OR_GPCM_CSNT \ 269 | OR_GPCM_XACS \ 270 | OR_GPCM_SCY_15 \ 271 | OR_GPCM_TRLX_SET \ 272 | OR_GPCM_EHTR_SET \ 273 | OR_GPCM_EAD) 274 /* 0xFFFFE9F7 */ 275 276 /* 277 * NAND Flash on the Local Bus 278 */ 279 #define CONFIG_SYS_MAX_NAND_DEVICE 1 280 #define CONFIG_NAND_FSL_ELBC 1 281 282 #define CONFIG_SYS_NAND_BASE 0xE0600000 283 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 284 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 285 | BR_PS_8 /* 8 bit port */ \ 286 | BR_MS_FCM /* MSEL = FCM */ \ 287 | BR_V) /* valid */ 288 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 289 | OR_FCM_BCTLD \ 290 | OR_FCM_CST \ 291 | OR_FCM_CHT \ 292 | OR_FCM_SCY_1 \ 293 | OR_FCM_RST \ 294 | OR_FCM_TRLX \ 295 | OR_FCM_EHTR) 296 /* 0xFFFF919E */ 297 298 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 299 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 300 301 /* 302 * Serial Port 303 */ 304 #define CONFIG_CONS_INDEX 1 305 #define CONFIG_SYS_NS16550_SERIAL 306 #define CONFIG_SYS_NS16550_REG_SIZE 1 307 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 308 309 #define CONFIG_SYS_BAUDRATE_TABLE \ 310 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 311 312 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 313 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 314 315 /* I2C */ 316 #define CONFIG_SYS_I2C 317 #define CONFIG_SYS_I2C_FSL 318 #define CONFIG_SYS_FSL_I2C_SPEED 400000 319 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 320 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 321 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 322 323 /* 324 * Config on-board RTC 325 */ 326 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 327 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 328 329 /* 330 * General PCI 331 * Addresses are mapped 1-1. 332 */ 333 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 334 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 335 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 336 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 337 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 338 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 339 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 340 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 341 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 342 343 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 344 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 345 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 346 347 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 348 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 349 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 350 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 351 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 352 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 353 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 354 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 355 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 356 357 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 358 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 359 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 360 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 361 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 362 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 363 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 364 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 365 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 366 367 #ifdef CONFIG_PCI 368 #define CONFIG_PCI_INDIRECT_BRIDGE 369 #ifndef __ASSEMBLY__ 370 extern int board_pci_host_broken(void); 371 #endif 372 #define CONFIG_PCIE 373 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 374 375 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 376 #define CONFIG_USB_EHCI_FSL 377 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 378 379 #undef CONFIG_EEPRO100 380 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 381 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 382 #endif /* CONFIG_PCI */ 383 384 /* 385 * TSEC 386 */ 387 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 388 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 389 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 390 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 391 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 392 393 /* 394 * TSEC ethernet configuration 395 */ 396 #define CONFIG_MII 1 /* MII PHY management */ 397 #define CONFIG_TSEC1 1 398 #define CONFIG_TSEC1_NAME "eTSEC0" 399 #define CONFIG_TSEC2 1 400 #define CONFIG_TSEC2_NAME "eTSEC1" 401 #define TSEC1_PHY_ADDR 2 402 #define TSEC2_PHY_ADDR 3 403 #define TSEC1_PHY_ADDR_SGMII 8 404 #define TSEC2_PHY_ADDR_SGMII 4 405 #define TSEC1_PHYIDX 0 406 #define TSEC2_PHYIDX 0 407 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 408 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 409 410 /* Options are: TSEC[0-1] */ 411 #define CONFIG_ETHPRIME "eTSEC1" 412 413 /* SERDES */ 414 #define CONFIG_FSL_SERDES 415 #define CONFIG_FSL_SERDES1 0xe3000 416 #define CONFIG_FSL_SERDES2 0xe3100 417 418 /* 419 * SATA 420 */ 421 #define CONFIG_SYS_SATA_MAX_DEVICE 2 422 #define CONFIG_SATA1 423 #define CONFIG_SYS_SATA1_OFFSET 0x18000 424 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 425 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 426 #define CONFIG_SATA2 427 #define CONFIG_SYS_SATA2_OFFSET 0x19000 428 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 429 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 430 431 #ifdef CONFIG_FSL_SATA 432 #define CONFIG_LBA48 433 #endif 434 435 /* 436 * Environment 437 */ 438 #ifndef CONFIG_SYS_RAMBOOT 439 #define CONFIG_ENV_ADDR \ 440 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 441 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 442 #define CONFIG_ENV_SIZE 0x2000 443 #else 444 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 445 #define CONFIG_ENV_SIZE 0x2000 446 #endif 447 448 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 449 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 450 451 /* 452 * BOOTP options 453 */ 454 #define CONFIG_BOOTP_BOOTFILESIZE 455 456 /* 457 * Command line configuration. 458 */ 459 460 #undef CONFIG_WATCHDOG /* watchdog disabled */ 461 462 #ifdef CONFIG_MMC 463 #define CONFIG_FSL_ESDHC 464 #define CONFIG_FSL_ESDHC_PIN_MUX 465 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 466 #endif 467 468 /* 469 * Miscellaneous configurable options 470 */ 471 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 472 473 /* 474 * For booting Linux, the board info and command line data 475 * have to be in the first 256 MB of memory, since this is 476 * the maximum mapped by the Linux kernel during initialization. 477 */ 478 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 479 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 480 481 /* 482 * Core HID Setup 483 */ 484 #define CONFIG_SYS_HID0_INIT 0x000000000 485 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 486 HID0_ENABLE_INSTRUCTION_CACHE) 487 #define CONFIG_SYS_HID2 HID2_HBE 488 489 /* 490 * MMU Setup 491 */ 492 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 493 494 /* DDR: cache cacheable */ 495 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 496 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 497 498 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 499 | BATL_PP_RW \ 500 | BATL_MEMCOHERENCE) 501 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 502 | BATU_BL_256M \ 503 | BATU_VS \ 504 | BATU_VP) 505 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 506 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 507 508 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 509 | BATL_PP_RW \ 510 | BATL_MEMCOHERENCE) 511 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 512 | BATU_BL_256M \ 513 | BATU_VS \ 514 | BATU_VP) 515 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 516 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 517 518 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 519 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 520 | BATL_PP_RW \ 521 | BATL_CACHEINHIBIT \ 522 | BATL_GUARDEDSTORAGE) 523 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 524 | BATU_BL_8M \ 525 | BATU_VS \ 526 | BATU_VP) 527 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 528 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 529 530 /* BCSR: cache-inhibit and guarded */ 531 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 532 | BATL_PP_RW \ 533 | BATL_CACHEINHIBIT \ 534 | BATL_GUARDEDSTORAGE) 535 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 536 | BATU_BL_128K \ 537 | BATU_VS \ 538 | BATU_VP) 539 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 540 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 541 542 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 543 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 544 | BATL_PP_RW \ 545 | BATL_MEMCOHERENCE) 546 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 547 | BATU_BL_32M \ 548 | BATU_VS \ 549 | BATU_VP) 550 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 551 | BATL_PP_RW \ 552 | BATL_CACHEINHIBIT \ 553 | BATL_GUARDEDSTORAGE) 554 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 555 556 /* Stack in dcache: cacheable, no memory coherence */ 557 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 558 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 559 | BATU_BL_128K \ 560 | BATU_VS \ 561 | BATU_VP) 562 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 563 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 564 565 #ifdef CONFIG_PCI 566 /* PCI MEM space: cacheable */ 567 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 568 | BATL_PP_RW \ 569 | BATL_MEMCOHERENCE) 570 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 571 | BATU_BL_256M \ 572 | BATU_VS \ 573 | BATU_VP) 574 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 575 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 576 /* PCI MMIO space: cache-inhibit and guarded */ 577 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 578 | BATL_PP_RW \ 579 | BATL_CACHEINHIBIT \ 580 | BATL_GUARDEDSTORAGE) 581 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 582 | BATU_BL_256M \ 583 | BATU_VS \ 584 | BATU_VP) 585 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 586 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 587 #else 588 #define CONFIG_SYS_IBAT6L (0) 589 #define CONFIG_SYS_IBAT6U (0) 590 #define CONFIG_SYS_IBAT7L (0) 591 #define CONFIG_SYS_IBAT7U (0) 592 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 593 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 594 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 595 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 596 #endif 597 598 #if defined(CONFIG_CMD_KGDB) 599 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 600 #endif 601 602 /* 603 * Environment Configuration 604 */ 605 606 #define CONFIG_ENV_OVERWRITE 607 608 #if defined(CONFIG_TSEC_ENET) 609 #define CONFIG_HAS_ETH0 610 #define CONFIG_HAS_ETH1 611 #endif 612 613 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 614 615 #define CONFIG_EXTRA_ENV_SETTINGS \ 616 "netdev=eth0\0" \ 617 "consoledev=ttyS0\0" \ 618 "ramdiskaddr=1000000\0" \ 619 "ramdiskfile=ramfs.83xx\0" \ 620 "fdtaddr=780000\0" \ 621 "fdtfile=mpc8379_mds.dtb\0" \ 622 "" 623 624 #define CONFIG_NFSBOOTCOMMAND \ 625 "setenv bootargs root=/dev/nfs rw " \ 626 "nfsroot=$serverip:$rootpath " \ 627 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 628 "$netdev:off " \ 629 "console=$consoledev,$baudrate $othbootargs;" \ 630 "tftp $loadaddr $bootfile;" \ 631 "tftp $fdtaddr $fdtfile;" \ 632 "bootm $loadaddr - $fdtaddr" 633 634 #define CONFIG_RAMBOOTCOMMAND \ 635 "setenv bootargs root=/dev/ram rw " \ 636 "console=$consoledev,$baudrate $othbootargs;" \ 637 "tftp $ramdiskaddr $ramdiskfile;" \ 638 "tftp $loadaddr $bootfile;" \ 639 "tftp $fdtaddr $fdtfile;" \ 640 "bootm $loadaddr $ramdiskaddr $fdtaddr" 641 642 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 643 644 #endif /* __CONFIG_H */ 645