1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #define CONFIG_SYS_GENERIC_BOARD 12 #define CONFIG_DISPLAY_BOARDINFO 13 14 /* 15 * High Level Configuration Options 16 */ 17 #define CONFIG_E300 1 /* E300 family */ 18 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 19 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 /* 24 * System Clock Setup 25 */ 26 #ifdef CONFIG_PCISLAVE 27 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 28 #else 29 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 30 #endif 31 32 #ifndef CONFIG_SYS_CLK_FREQ 33 #define CONFIG_SYS_CLK_FREQ 66000000 34 #endif 35 36 /* 37 * Hardware Reset Configuration Word 38 * if CLKIN is 66MHz, then 39 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 40 */ 41 #define CONFIG_SYS_HRCW_LOW (\ 42 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 43 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 44 HRCWL_SVCOD_DIV_2 |\ 45 HRCWL_CSB_TO_CLKIN_6X1 |\ 46 HRCWL_CORE_TO_CSB_1_5X1) 47 48 #ifdef CONFIG_PCISLAVE 49 #define CONFIG_SYS_HRCW_HIGH (\ 50 HRCWH_PCI_AGENT |\ 51 HRCWH_PCI1_ARBITER_DISABLE |\ 52 HRCWH_CORE_ENABLE |\ 53 HRCWH_FROM_0XFFF00100 |\ 54 HRCWH_BOOTSEQ_DISABLE |\ 55 HRCWH_SW_WATCHDOG_DISABLE |\ 56 HRCWH_ROM_LOC_LOCAL_16BIT |\ 57 HRCWH_RL_EXT_LEGACY |\ 58 HRCWH_TSEC1M_IN_RGMII |\ 59 HRCWH_TSEC2M_IN_RGMII |\ 60 HRCWH_BIG_ENDIAN |\ 61 HRCWH_LDP_CLEAR) 62 #else 63 #define CONFIG_SYS_HRCW_HIGH (\ 64 HRCWH_PCI_HOST |\ 65 HRCWH_PCI1_ARBITER_ENABLE |\ 66 HRCWH_CORE_ENABLE |\ 67 HRCWH_FROM_0X00000100 |\ 68 HRCWH_BOOTSEQ_DISABLE |\ 69 HRCWH_SW_WATCHDOG_DISABLE |\ 70 HRCWH_ROM_LOC_LOCAL_16BIT |\ 71 HRCWH_RL_EXT_LEGACY |\ 72 HRCWH_TSEC1M_IN_RGMII |\ 73 HRCWH_TSEC2M_IN_RGMII |\ 74 HRCWH_BIG_ENDIAN |\ 75 HRCWH_LDP_CLEAR) 76 #endif 77 78 /* Arbiter Configuration Register */ 79 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 80 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 81 82 /* System Priority Control Register */ 83 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 84 85 /* 86 * IP blocks clock configuration 87 */ 88 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 89 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 90 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 91 92 /* 93 * System IO Config 94 */ 95 #define CONFIG_SYS_SICRH 0x00000000 96 #define CONFIG_SYS_SICRL 0x00000000 97 98 /* 99 * Output Buffer Impedance 100 */ 101 #define CONFIG_SYS_OBIR 0x31100000 102 103 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 104 #define CONFIG_BOARD_EARLY_INIT_R 105 #define CONFIG_HWCONFIG 106 107 /* 108 * IMMR new address 109 */ 110 #define CONFIG_SYS_IMMR 0xE0000000 111 112 /* 113 * DDR Setup 114 */ 115 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 119 #define CONFIG_SYS_83XX_DDR_USES_CS0 120 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 121 | DDRCDR_ODT \ 122 | DDRCDR_Q_DRN) 123 /* 0x80080001 */ /* ODT 150ohm on SoC */ 124 125 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 126 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 127 128 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 129 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 130 131 #if defined(CONFIG_SPD_EEPROM) 132 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 133 #else 134 /* 135 * Manually set up DDR parameters 136 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 137 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 138 */ 139 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 141 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 142 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 143 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 144 | CSCONFIG_ROW_BIT_14 \ 145 | CSCONFIG_COL_BIT_10) 146 /* 0x80010202 */ 147 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 148 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 149 | (0 << TIMING_CFG0_WRT_SHIFT) \ 150 | (0 << TIMING_CFG0_RRT_SHIFT) \ 151 | (0 << TIMING_CFG0_WWT_SHIFT) \ 152 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 153 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 154 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 155 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 156 /* 0x00620802 */ 157 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 158 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 159 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 160 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 161 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 162 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 163 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 164 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 165 /* 0x3935d322 */ 166 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 167 | (6 << TIMING_CFG2_CPO_SHIFT) \ 168 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 169 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 170 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 171 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 172 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 173 /* 0x131088c8 */ 174 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 175 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 176 /* 0x03E00100 */ 177 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 178 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 179 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 180 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 181 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 182 #define CONFIG_SYS_DDR_MODE2 0x00000000 183 #endif 184 185 /* 186 * Memory test 187 */ 188 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 189 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 190 #define CONFIG_SYS_MEMTEST_END 0x00140000 191 192 /* 193 * The reserved memory 194 */ 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 196 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 204 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 205 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 206 207 /* 208 * Initial RAM Base Address Setup 209 */ 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 213 #define CONFIG_SYS_GBL_DATA_OFFSET \ 214 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 216 /* 217 * Local Bus Configuration & Clock Setup 218 */ 219 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 220 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 221 #define CONFIG_SYS_LBC_LBCR 0x00000000 222 #define CONFIG_FSL_ELBC 1 223 224 /* 225 * FLASH on the Local Bus 226 */ 227 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 228 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 229 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 230 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 231 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 232 233 /* Window base at flash base */ 234 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 235 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 236 237 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 238 | BR_PS_16 /* 16 bit port */ \ 239 | BR_MS_GPCM /* MSEL = GPCM */ \ 240 | BR_V) /* valid */ 241 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 242 | OR_UPM_XAM \ 243 | OR_GPCM_CSNT \ 244 | OR_GPCM_ACS_DIV2 \ 245 | OR_GPCM_XACS \ 246 | OR_GPCM_SCY_15 \ 247 | OR_GPCM_TRLX_SET \ 248 | OR_GPCM_EHTR_SET \ 249 | OR_GPCM_EAD) 250 /* 0xFE000FF7 */ 251 252 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 253 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 254 255 #undef CONFIG_SYS_FLASH_CHECKSUM 256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 258 259 /* 260 * BCSR on the Local Bus 261 */ 262 #define CONFIG_SYS_BCSR 0xF8000000 263 /* Access window base at BCSR base */ 264 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 265 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 266 267 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 268 | BR_PS_8 \ 269 | BR_MS_GPCM \ 270 | BR_V) 271 /* 0xF8000801 */ 272 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 273 | OR_GPCM_XAM \ 274 | OR_GPCM_CSNT \ 275 | OR_GPCM_XACS \ 276 | OR_GPCM_SCY_15 \ 277 | OR_GPCM_TRLX_SET \ 278 | OR_GPCM_EHTR_SET \ 279 | OR_GPCM_EAD) 280 /* 0xFFFFE9F7 */ 281 282 /* 283 * NAND Flash on the Local Bus 284 */ 285 #define CONFIG_CMD_NAND 1 286 #define CONFIG_SYS_MAX_NAND_DEVICE 1 287 #define CONFIG_NAND_FSL_ELBC 1 288 289 #define CONFIG_SYS_NAND_BASE 0xE0600000 290 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 291 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 292 | BR_PS_8 /* 8 bit port */ \ 293 | BR_MS_FCM /* MSEL = FCM */ \ 294 | BR_V) /* valid */ 295 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 296 | OR_FCM_BCTLD \ 297 | OR_FCM_CST \ 298 | OR_FCM_CHT \ 299 | OR_FCM_SCY_1 \ 300 | OR_FCM_RST \ 301 | OR_FCM_TRLX \ 302 | OR_FCM_EHTR) 303 /* 0xFFFF919E */ 304 305 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 306 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 307 308 /* 309 * Serial Port 310 */ 311 #define CONFIG_CONS_INDEX 1 312 #define CONFIG_SYS_NS16550 313 #define CONFIG_SYS_NS16550_SERIAL 314 #define CONFIG_SYS_NS16550_REG_SIZE 1 315 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 316 317 #define CONFIG_SYS_BAUDRATE_TABLE \ 318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 319 320 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 321 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 322 323 /* Use the HUSH parser */ 324 #define CONFIG_SYS_HUSH_PARSER 325 326 /* Pass open firmware flat tree */ 327 #define CONFIG_OF_LIBFDT 1 328 #define CONFIG_OF_BOARD_SETUP 1 329 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 330 331 /* I2C */ 332 #define CONFIG_SYS_I2C 333 #define CONFIG_SYS_I2C_FSL 334 #define CONFIG_SYS_FSL_I2C_SPEED 400000 335 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 336 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 337 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 338 339 /* 340 * Config on-board RTC 341 */ 342 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 343 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 344 345 /* 346 * General PCI 347 * Addresses are mapped 1-1. 348 */ 349 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 350 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 351 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 352 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 353 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 354 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 355 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 356 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 357 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 358 359 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 360 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 361 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 362 363 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 364 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 365 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 366 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 367 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 368 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 369 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 370 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 371 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 372 373 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 374 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 375 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 376 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 377 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 378 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 379 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 380 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 381 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 382 383 #ifdef CONFIG_PCI 384 #define CONFIG_PCI_INDIRECT_BRIDGE 385 #ifndef __ASSEMBLY__ 386 extern int board_pci_host_broken(void); 387 #endif 388 #define CONFIG_PCIE 389 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 390 391 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 392 #define CONFIG_CMD_USB 393 #define CONFIG_USB_STORAGE 394 #define CONFIG_USB_EHCI 395 #define CONFIG_USB_EHCI_FSL 396 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 397 398 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 399 400 #undef CONFIG_EEPRO100 401 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 402 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 403 #endif /* CONFIG_PCI */ 404 405 /* 406 * TSEC 407 */ 408 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 409 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 410 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 411 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 412 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 413 414 /* 415 * TSEC ethernet configuration 416 */ 417 #define CONFIG_MII 1 /* MII PHY management */ 418 #define CONFIG_TSEC1 1 419 #define CONFIG_TSEC1_NAME "eTSEC0" 420 #define CONFIG_TSEC2 1 421 #define CONFIG_TSEC2_NAME "eTSEC1" 422 #define TSEC1_PHY_ADDR 2 423 #define TSEC2_PHY_ADDR 3 424 #define TSEC1_PHY_ADDR_SGMII 8 425 #define TSEC2_PHY_ADDR_SGMII 4 426 #define TSEC1_PHYIDX 0 427 #define TSEC2_PHYIDX 0 428 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 429 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 430 431 /* Options are: TSEC[0-1] */ 432 #define CONFIG_ETHPRIME "eTSEC1" 433 434 /* SERDES */ 435 #define CONFIG_FSL_SERDES 436 #define CONFIG_FSL_SERDES1 0xe3000 437 #define CONFIG_FSL_SERDES2 0xe3100 438 439 /* 440 * SATA 441 */ 442 #define CONFIG_LIBATA 443 #define CONFIG_FSL_SATA 444 445 #define CONFIG_SYS_SATA_MAX_DEVICE 2 446 #define CONFIG_SATA1 447 #define CONFIG_SYS_SATA1_OFFSET 0x18000 448 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 449 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 450 #define CONFIG_SATA2 451 #define CONFIG_SYS_SATA2_OFFSET 0x19000 452 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 453 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 454 455 #ifdef CONFIG_FSL_SATA 456 #define CONFIG_LBA48 457 #define CONFIG_CMD_SATA 458 #define CONFIG_DOS_PARTITION 459 #define CONFIG_CMD_EXT2 460 #endif 461 462 /* 463 * Environment 464 */ 465 #ifndef CONFIG_SYS_RAMBOOT 466 #define CONFIG_ENV_IS_IN_FLASH 1 467 #define CONFIG_ENV_ADDR \ 468 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 469 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 470 #define CONFIG_ENV_SIZE 0x2000 471 #else 472 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 473 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 474 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 475 #define CONFIG_ENV_SIZE 0x2000 476 #endif 477 478 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 479 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 480 481 /* 482 * BOOTP options 483 */ 484 #define CONFIG_BOOTP_BOOTFILESIZE 485 #define CONFIG_BOOTP_BOOTPATH 486 #define CONFIG_BOOTP_GATEWAY 487 #define CONFIG_BOOTP_HOSTNAME 488 489 490 /* 491 * Command line configuration. 492 */ 493 #include <config_cmd_default.h> 494 495 #define CONFIG_CMD_PING 496 #define CONFIG_CMD_I2C 497 #define CONFIG_CMD_MII 498 #define CONFIG_CMD_DATE 499 500 #if defined(CONFIG_PCI) 501 #define CONFIG_CMD_PCI 502 #endif 503 504 #if defined(CONFIG_SYS_RAMBOOT) 505 #undef CONFIG_CMD_SAVEENV 506 #undef CONFIG_CMD_LOADS 507 #endif 508 509 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 510 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 511 512 #undef CONFIG_WATCHDOG /* watchdog disabled */ 513 514 #define CONFIG_MMC 1 515 516 #ifdef CONFIG_MMC 517 #define CONFIG_FSL_ESDHC 518 #define CONFIG_FSL_ESDHC_PIN_MUX 519 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 520 #define CONFIG_CMD_MMC 521 #define CONFIG_GENERIC_MMC 522 #define CONFIG_CMD_EXT2 523 #define CONFIG_CMD_FAT 524 #define CONFIG_DOS_PARTITION 525 #endif 526 527 /* 528 * Miscellaneous configurable options 529 */ 530 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 531 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 532 533 #if defined(CONFIG_CMD_KGDB) 534 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 535 #else 536 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 537 #endif 538 539 /* Print Buffer Size */ 540 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 541 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 542 /* Boot Argument Buffer Size */ 543 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 544 545 /* 546 * For booting Linux, the board info and command line data 547 * have to be in the first 256 MB of memory, since this is 548 * the maximum mapped by the Linux kernel during initialization. 549 */ 550 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 551 552 /* 553 * Core HID Setup 554 */ 555 #define CONFIG_SYS_HID0_INIT 0x000000000 556 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 557 HID0_ENABLE_INSTRUCTION_CACHE) 558 #define CONFIG_SYS_HID2 HID2_HBE 559 560 /* 561 * MMU Setup 562 */ 563 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 564 565 /* DDR: cache cacheable */ 566 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 567 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 568 569 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 570 | BATL_PP_RW \ 571 | BATL_MEMCOHERENCE) 572 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 573 | BATU_BL_256M \ 574 | BATU_VS \ 575 | BATU_VP) 576 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 577 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 578 579 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 580 | BATL_PP_RW \ 581 | BATL_MEMCOHERENCE) 582 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 583 | BATU_BL_256M \ 584 | BATU_VS \ 585 | BATU_VP) 586 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 587 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 588 589 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 590 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 591 | BATL_PP_RW \ 592 | BATL_CACHEINHIBIT \ 593 | BATL_GUARDEDSTORAGE) 594 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 595 | BATU_BL_8M \ 596 | BATU_VS \ 597 | BATU_VP) 598 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 599 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 600 601 /* BCSR: cache-inhibit and guarded */ 602 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 603 | BATL_PP_RW \ 604 | BATL_CACHEINHIBIT \ 605 | BATL_GUARDEDSTORAGE) 606 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 607 | BATU_BL_128K \ 608 | BATU_VS \ 609 | BATU_VP) 610 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 611 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 612 613 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 614 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 615 | BATL_PP_RW \ 616 | BATL_MEMCOHERENCE) 617 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 618 | BATU_BL_32M \ 619 | BATU_VS \ 620 | BATU_VP) 621 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 622 | BATL_PP_RW \ 623 | BATL_CACHEINHIBIT \ 624 | BATL_GUARDEDSTORAGE) 625 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 626 627 /* Stack in dcache: cacheable, no memory coherence */ 628 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 629 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 630 | BATU_BL_128K \ 631 | BATU_VS \ 632 | BATU_VP) 633 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 634 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 635 636 #ifdef CONFIG_PCI 637 /* PCI MEM space: cacheable */ 638 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 639 | BATL_PP_RW \ 640 | BATL_MEMCOHERENCE) 641 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 642 | BATU_BL_256M \ 643 | BATU_VS \ 644 | BATU_VP) 645 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 646 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 647 /* PCI MMIO space: cache-inhibit and guarded */ 648 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 649 | BATL_PP_RW \ 650 | BATL_CACHEINHIBIT \ 651 | BATL_GUARDEDSTORAGE) 652 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 653 | BATU_BL_256M \ 654 | BATU_VS \ 655 | BATU_VP) 656 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 657 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 658 #else 659 #define CONFIG_SYS_IBAT6L (0) 660 #define CONFIG_SYS_IBAT6U (0) 661 #define CONFIG_SYS_IBAT7L (0) 662 #define CONFIG_SYS_IBAT7U (0) 663 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 664 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 665 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 666 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 667 #endif 668 669 #if defined(CONFIG_CMD_KGDB) 670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 671 #endif 672 673 /* 674 * Environment Configuration 675 */ 676 677 #define CONFIG_ENV_OVERWRITE 678 679 #if defined(CONFIG_TSEC_ENET) 680 #define CONFIG_HAS_ETH0 681 #define CONFIG_HAS_ETH1 682 #endif 683 684 #define CONFIG_BAUDRATE 115200 685 686 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 687 688 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 689 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 690 691 #define CONFIG_EXTRA_ENV_SETTINGS \ 692 "netdev=eth0\0" \ 693 "consoledev=ttyS0\0" \ 694 "ramdiskaddr=1000000\0" \ 695 "ramdiskfile=ramfs.83xx\0" \ 696 "fdtaddr=780000\0" \ 697 "fdtfile=mpc8379_mds.dtb\0" \ 698 "" 699 700 #define CONFIG_NFSBOOTCOMMAND \ 701 "setenv bootargs root=/dev/nfs rw " \ 702 "nfsroot=$serverip:$rootpath " \ 703 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 704 "$netdev:off " \ 705 "console=$consoledev,$baudrate $othbootargs;" \ 706 "tftp $loadaddr $bootfile;" \ 707 "tftp $fdtaddr $fdtfile;" \ 708 "bootm $loadaddr - $fdtaddr" 709 710 #define CONFIG_RAMBOOTCOMMAND \ 711 "setenv bootargs root=/dev/ram rw " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $ramdiskaddr $ramdiskfile;" \ 714 "tftp $loadaddr $bootfile;" \ 715 "tftp $fdtaddr $fdtfile;" \ 716 "bootm $loadaddr $ramdiskaddr $fdtaddr" 717 718 719 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 720 721 #endif /* __CONFIG_H */ 722