1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 #define CONFIG_E300 1 /* E300 family */ 15 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 16 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ 17 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ 18 19 #define CONFIG_SYS_TEXT_BASE 0xFE000000 20 21 /* 22 * System Clock Setup 23 */ 24 #ifdef CONFIG_PCISLAVE 25 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ 26 #else 27 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 28 #endif 29 30 #ifndef CONFIG_SYS_CLK_FREQ 31 #define CONFIG_SYS_CLK_FREQ 66000000 32 #endif 33 34 /* 35 * Hardware Reset Configuration Word 36 * if CLKIN is 66MHz, then 37 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz 38 */ 39 #define CONFIG_SYS_HRCW_LOW (\ 40 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 41 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 42 HRCWL_SVCOD_DIV_2 |\ 43 HRCWL_CSB_TO_CLKIN_6X1 |\ 44 HRCWL_CORE_TO_CSB_1_5X1) 45 46 #ifdef CONFIG_PCISLAVE 47 #define CONFIG_SYS_HRCW_HIGH (\ 48 HRCWH_PCI_AGENT |\ 49 HRCWH_PCI1_ARBITER_DISABLE |\ 50 HRCWH_CORE_ENABLE |\ 51 HRCWH_FROM_0XFFF00100 |\ 52 HRCWH_BOOTSEQ_DISABLE |\ 53 HRCWH_SW_WATCHDOG_DISABLE |\ 54 HRCWH_ROM_LOC_LOCAL_16BIT |\ 55 HRCWH_RL_EXT_LEGACY |\ 56 HRCWH_TSEC1M_IN_RGMII |\ 57 HRCWH_TSEC2M_IN_RGMII |\ 58 HRCWH_BIG_ENDIAN |\ 59 HRCWH_LDP_CLEAR) 60 #else 61 #define CONFIG_SYS_HRCW_HIGH (\ 62 HRCWH_PCI_HOST |\ 63 HRCWH_PCI1_ARBITER_ENABLE |\ 64 HRCWH_CORE_ENABLE |\ 65 HRCWH_FROM_0X00000100 |\ 66 HRCWH_BOOTSEQ_DISABLE |\ 67 HRCWH_SW_WATCHDOG_DISABLE |\ 68 HRCWH_ROM_LOC_LOCAL_16BIT |\ 69 HRCWH_RL_EXT_LEGACY |\ 70 HRCWH_TSEC1M_IN_RGMII |\ 71 HRCWH_TSEC2M_IN_RGMII |\ 72 HRCWH_BIG_ENDIAN |\ 73 HRCWH_LDP_CLEAR) 74 #endif 75 76 /* Arbiter Configuration Register */ 77 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 78 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 79 80 /* System Priority Control Register */ 81 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ 82 83 /* 84 * IP blocks clock configuration 85 */ 86 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ 87 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ 88 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ 89 90 /* 91 * System IO Config 92 */ 93 #define CONFIG_SYS_SICRH 0x00000000 94 #define CONFIG_SYS_SICRL 0x00000000 95 96 /* 97 * Output Buffer Impedance 98 */ 99 #define CONFIG_SYS_OBIR 0x31100000 100 101 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ 102 #define CONFIG_BOARD_EARLY_INIT_R 103 #define CONFIG_HWCONFIG 104 105 /* 106 * IMMR new address 107 */ 108 #define CONFIG_SYS_IMMR 0xE0000000 109 110 /* 111 * DDR Setup 112 */ 113 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 115 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 116 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 117 #define CONFIG_SYS_83XX_DDR_USES_CS0 118 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ 119 | DDRCDR_ODT \ 120 | DDRCDR_Q_DRN) 121 /* 0x80080001 */ /* ODT 150ohm on SoC */ 122 123 #undef CONFIG_DDR_ECC /* support DDR ECC function */ 124 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ 125 126 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 127 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ 128 129 #if defined(CONFIG_SPD_EEPROM) 130 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ 131 #else 132 /* 133 * Manually set up DDR parameters 134 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM 135 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 136 */ 137 #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 138 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 139 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 140 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ 141 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ 142 | CSCONFIG_ROW_BIT_14 \ 143 | CSCONFIG_COL_BIT_10) 144 /* 0x80010202 */ 145 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 146 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 147 | (0 << TIMING_CFG0_WRT_SHIFT) \ 148 | (0 << TIMING_CFG0_RRT_SHIFT) \ 149 | (0 << TIMING_CFG0_WWT_SHIFT) \ 150 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 151 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 152 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 153 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 154 /* 0x00620802 */ 155 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ 156 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 157 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ 158 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 159 | (13 << TIMING_CFG1_REFREC_SHIFT) \ 160 | (3 << TIMING_CFG1_WRREC_SHIFT) \ 161 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 162 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 163 /* 0x3935d322 */ 164 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 165 | (6 << TIMING_CFG2_CPO_SHIFT) \ 166 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 167 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 168 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 169 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 170 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) 171 /* 0x131088c8 */ 172 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ 173 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 174 /* 0x03E00100 */ 175 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 176 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ 177 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 178 | (0x1432 << SDRAM_MODE_SD_SHIFT)) 179 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 180 #define CONFIG_SYS_DDR_MODE2 0x00000000 181 #endif 182 183 /* 184 * Memory test 185 */ 186 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 187 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ 188 #define CONFIG_SYS_MEMTEST_END 0x00140000 189 190 /* 191 * The reserved memory 192 */ 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 194 195 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 196 #define CONFIG_SYS_RAMBOOT 197 #else 198 #undef CONFIG_SYS_RAMBOOT 199 #endif 200 201 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 202 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 203 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 204 205 /* 206 * Initial RAM Base Address Setup 207 */ 208 #define CONFIG_SYS_INIT_RAM_LOCK 1 209 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 210 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 211 #define CONFIG_SYS_GBL_DATA_OFFSET \ 212 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 213 214 /* 215 * Local Bus Configuration & Clock Setup 216 */ 217 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 218 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 219 #define CONFIG_SYS_LBC_LBCR 0x00000000 220 #define CONFIG_FSL_ELBC 1 221 222 /* 223 * FLASH on the Local Bus 224 */ 225 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 226 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 227 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 228 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ 229 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 230 231 /* Window base at flash base */ 232 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 233 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 234 235 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 236 | BR_PS_16 /* 16 bit port */ \ 237 | BR_MS_GPCM /* MSEL = GPCM */ \ 238 | BR_V) /* valid */ 239 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 240 | OR_UPM_XAM \ 241 | OR_GPCM_CSNT \ 242 | OR_GPCM_ACS_DIV2 \ 243 | OR_GPCM_XACS \ 244 | OR_GPCM_SCY_15 \ 245 | OR_GPCM_TRLX_SET \ 246 | OR_GPCM_EHTR_SET \ 247 | OR_GPCM_EAD) 248 /* 0xFE000FF7 */ 249 250 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 251 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ 252 253 #undef CONFIG_SYS_FLASH_CHECKSUM 254 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 255 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 256 257 /* 258 * BCSR on the Local Bus 259 */ 260 #define CONFIG_SYS_BCSR 0xF8000000 261 /* Access window base at BCSR base */ 262 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR 263 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 264 265 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ 266 | BR_PS_8 \ 267 | BR_MS_GPCM \ 268 | BR_V) 269 /* 0xF8000801 */ 270 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ 271 | OR_GPCM_XAM \ 272 | OR_GPCM_CSNT \ 273 | OR_GPCM_XACS \ 274 | OR_GPCM_SCY_15 \ 275 | OR_GPCM_TRLX_SET \ 276 | OR_GPCM_EHTR_SET \ 277 | OR_GPCM_EAD) 278 /* 0xFFFFE9F7 */ 279 280 /* 281 * NAND Flash on the Local Bus 282 */ 283 #define CONFIG_CMD_NAND 1 284 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 285 #define CONFIG_SYS_MAX_NAND_DEVICE 1 286 #define CONFIG_NAND_FSL_ELBC 1 287 288 #define CONFIG_SYS_NAND_BASE 0xE0600000 289 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ 290 | BR_DECC_CHK_GEN /* Use HW ECC */ \ 291 | BR_PS_8 /* 8 bit port */ \ 292 | BR_MS_FCM /* MSEL = FCM */ \ 293 | BR_V) /* valid */ 294 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ 295 | OR_FCM_BCTLD \ 296 | OR_FCM_CST \ 297 | OR_FCM_CHT \ 298 | OR_FCM_SCY_1 \ 299 | OR_FCM_RST \ 300 | OR_FCM_TRLX \ 301 | OR_FCM_EHTR) 302 /* 0xFFFF919E */ 303 304 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE 305 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 306 307 /* 308 * Serial Port 309 */ 310 #define CONFIG_CONS_INDEX 1 311 #define CONFIG_SYS_NS16550 312 #define CONFIG_SYS_NS16550_SERIAL 313 #define CONFIG_SYS_NS16550_REG_SIZE 1 314 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 315 316 #define CONFIG_SYS_BAUDRATE_TABLE \ 317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 318 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 321 322 /* Use the HUSH parser */ 323 #define CONFIG_SYS_HUSH_PARSER 324 325 /* Pass open firmware flat tree */ 326 #define CONFIG_OF_LIBFDT 1 327 #define CONFIG_OF_BOARD_SETUP 1 328 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 329 330 /* I2C */ 331 #define CONFIG_SYS_I2C 332 #define CONFIG_SYS_I2C_FSL 333 #define CONFIG_SYS_FSL_I2C_SPEED 400000 334 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 335 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 336 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 337 338 /* 339 * Config on-board RTC 340 */ 341 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ 342 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 343 344 /* 345 * General PCI 346 * Addresses are mapped 1-1. 347 */ 348 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 349 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE 350 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ 351 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 352 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE 353 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ 354 #define CONFIG_SYS_PCI_IO_BASE 0x00000000 355 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 356 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ 357 358 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE 359 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 360 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 361 362 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 363 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 364 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 365 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 366 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 367 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 368 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 369 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 370 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 371 372 #define CONFIG_SYS_PCIE2_BASE 0xC0000000 373 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 374 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 375 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 376 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 377 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 378 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 379 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 380 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 381 382 #ifdef CONFIG_PCI 383 #define CONFIG_PCI_INDIRECT_BRIDGE 384 #ifndef __ASSEMBLY__ 385 extern int board_pci_host_broken(void); 386 #endif 387 #define CONFIG_PCIE 388 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ 389 390 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ 391 392 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 393 394 #undef CONFIG_EEPRO100 395 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 396 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 397 #endif /* CONFIG_PCI */ 398 399 /* 400 * TSEC 401 */ 402 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 403 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 404 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 405 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 406 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 407 408 /* 409 * TSEC ethernet configuration 410 */ 411 #define CONFIG_MII 1 /* MII PHY management */ 412 #define CONFIG_TSEC1 1 413 #define CONFIG_TSEC1_NAME "eTSEC0" 414 #define CONFIG_TSEC2 1 415 #define CONFIG_TSEC2_NAME "eTSEC1" 416 #define TSEC1_PHY_ADDR 2 417 #define TSEC2_PHY_ADDR 3 418 #define TSEC1_PHY_ADDR_SGMII 8 419 #define TSEC2_PHY_ADDR_SGMII 4 420 #define TSEC1_PHYIDX 0 421 #define TSEC2_PHYIDX 0 422 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 425 /* Options are: TSEC[0-1] */ 426 #define CONFIG_ETHPRIME "eTSEC1" 427 428 /* SERDES */ 429 #define CONFIG_FSL_SERDES 430 #define CONFIG_FSL_SERDES1 0xe3000 431 #define CONFIG_FSL_SERDES2 0xe3100 432 433 /* 434 * SATA 435 */ 436 #define CONFIG_LIBATA 437 #define CONFIG_FSL_SATA 438 439 #define CONFIG_SYS_SATA_MAX_DEVICE 2 440 #define CONFIG_SATA1 441 #define CONFIG_SYS_SATA1_OFFSET 0x18000 442 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) 443 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 444 #define CONFIG_SATA2 445 #define CONFIG_SYS_SATA2_OFFSET 0x19000 446 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) 447 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 448 449 #ifdef CONFIG_FSL_SATA 450 #define CONFIG_LBA48 451 #define CONFIG_CMD_SATA 452 #define CONFIG_DOS_PARTITION 453 #define CONFIG_CMD_EXT2 454 #endif 455 456 /* 457 * Environment 458 */ 459 #ifndef CONFIG_SYS_RAMBOOT 460 #define CONFIG_ENV_IS_IN_FLASH 1 461 #define CONFIG_ENV_ADDR \ 462 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 463 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 464 #define CONFIG_ENV_SIZE 0x2000 465 #else 466 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 467 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 468 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 469 #define CONFIG_ENV_SIZE 0x2000 470 #endif 471 472 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 473 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 474 475 /* 476 * BOOTP options 477 */ 478 #define CONFIG_BOOTP_BOOTFILESIZE 479 #define CONFIG_BOOTP_BOOTPATH 480 #define CONFIG_BOOTP_GATEWAY 481 #define CONFIG_BOOTP_HOSTNAME 482 483 484 /* 485 * Command line configuration. 486 */ 487 #include <config_cmd_default.h> 488 489 #define CONFIG_CMD_PING 490 #define CONFIG_CMD_I2C 491 #define CONFIG_CMD_MII 492 #define CONFIG_CMD_DATE 493 494 #if defined(CONFIG_PCI) 495 #define CONFIG_CMD_PCI 496 #endif 497 498 #if defined(CONFIG_SYS_RAMBOOT) 499 #undef CONFIG_CMD_SAVEENV 500 #undef CONFIG_CMD_LOADS 501 #endif 502 503 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 504 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 505 506 #undef CONFIG_WATCHDOG /* watchdog disabled */ 507 508 #define CONFIG_MMC 1 509 510 #ifdef CONFIG_MMC 511 #define CONFIG_FSL_ESDHC 512 #define CONFIG_FSL_ESDHC_PIN_MUX 513 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 514 #define CONFIG_CMD_MMC 515 #define CONFIG_GENERIC_MMC 516 #define CONFIG_CMD_EXT2 517 #define CONFIG_CMD_FAT 518 #define CONFIG_DOS_PARTITION 519 #endif 520 521 /* 522 * Miscellaneous configurable options 523 */ 524 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 525 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 526 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 527 528 #if defined(CONFIG_CMD_KGDB) 529 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 530 #else 531 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 532 #endif 533 534 /* Print Buffer Size */ 535 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 536 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 537 /* Boot Argument Buffer Size */ 538 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 539 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 540 541 /* 542 * For booting Linux, the board info and command line data 543 * have to be in the first 256 MB of memory, since this is 544 * the maximum mapped by the Linux kernel during initialization. 545 */ 546 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 547 548 /* 549 * Core HID Setup 550 */ 551 #define CONFIG_SYS_HID0_INIT 0x000000000 552 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 553 HID0_ENABLE_INSTRUCTION_CACHE) 554 #define CONFIG_SYS_HID2 HID2_HBE 555 556 /* 557 * MMU Setup 558 */ 559 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 560 561 /* DDR: cache cacheable */ 562 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE 563 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) 564 565 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ 566 | BATL_PP_RW \ 567 | BATL_MEMCOHERENCE) 568 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ 569 | BATU_BL_256M \ 570 | BATU_VS \ 571 | BATU_VP) 572 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 573 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 574 575 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ 576 | BATL_PP_RW \ 577 | BATL_MEMCOHERENCE) 578 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ 579 | BATU_BL_256M \ 580 | BATU_VS \ 581 | BATU_VP) 582 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 583 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 584 585 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ 586 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ 587 | BATL_PP_RW \ 588 | BATL_CACHEINHIBIT \ 589 | BATL_GUARDEDSTORAGE) 590 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ 591 | BATU_BL_8M \ 592 | BATU_VS \ 593 | BATU_VP) 594 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 595 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 596 597 /* BCSR: cache-inhibit and guarded */ 598 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ 599 | BATL_PP_RW \ 600 | BATL_CACHEINHIBIT \ 601 | BATL_GUARDEDSTORAGE) 602 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ 603 | BATU_BL_128K \ 604 | BATU_VS \ 605 | BATU_VP) 606 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 607 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 608 609 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 610 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ 611 | BATL_PP_RW \ 612 | BATL_MEMCOHERENCE) 613 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ 614 | BATU_BL_32M \ 615 | BATU_VS \ 616 | BATU_VP) 617 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ 618 | BATL_PP_RW \ 619 | BATL_CACHEINHIBIT \ 620 | BATL_GUARDEDSTORAGE) 621 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 622 623 /* Stack in dcache: cacheable, no memory coherence */ 624 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 625 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ 626 | BATU_BL_128K \ 627 | BATU_VS \ 628 | BATU_VP) 629 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 630 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 631 632 #ifdef CONFIG_PCI 633 /* PCI MEM space: cacheable */ 634 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ 635 | BATL_PP_RW \ 636 | BATL_MEMCOHERENCE) 637 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ 638 | BATU_BL_256M \ 639 | BATU_VS \ 640 | BATU_VP) 641 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 642 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 643 /* PCI MMIO space: cache-inhibit and guarded */ 644 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ 645 | BATL_PP_RW \ 646 | BATL_CACHEINHIBIT \ 647 | BATL_GUARDEDSTORAGE) 648 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ 649 | BATU_BL_256M \ 650 | BATU_VS \ 651 | BATU_VP) 652 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 653 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 654 #else 655 #define CONFIG_SYS_IBAT6L (0) 656 #define CONFIG_SYS_IBAT6U (0) 657 #define CONFIG_SYS_IBAT7L (0) 658 #define CONFIG_SYS_IBAT7U (0) 659 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 660 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 661 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 662 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 663 #endif 664 665 #if defined(CONFIG_CMD_KGDB) 666 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 667 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 668 #endif 669 670 /* 671 * Environment Configuration 672 */ 673 674 #define CONFIG_ENV_OVERWRITE 675 676 #if defined(CONFIG_TSEC_ENET) 677 #define CONFIG_HAS_ETH0 678 #define CONFIG_HAS_ETH1 679 #endif 680 681 #define CONFIG_BAUDRATE 115200 682 683 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 684 685 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 686 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 687 688 #define CONFIG_EXTRA_ENV_SETTINGS \ 689 "netdev=eth0\0" \ 690 "consoledev=ttyS0\0" \ 691 "ramdiskaddr=1000000\0" \ 692 "ramdiskfile=ramfs.83xx\0" \ 693 "fdtaddr=780000\0" \ 694 "fdtfile=mpc8379_mds.dtb\0" \ 695 "" 696 697 #define CONFIG_NFSBOOTCOMMAND \ 698 "setenv bootargs root=/dev/nfs rw " \ 699 "nfsroot=$serverip:$rootpath " \ 700 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 701 "$netdev:off " \ 702 "console=$consoledev,$baudrate $othbootargs;" \ 703 "tftp $loadaddr $bootfile;" \ 704 "tftp $fdtaddr $fdtfile;" \ 705 "bootm $loadaddr - $fdtaddr" 706 707 #define CONFIG_RAMBOOTCOMMAND \ 708 "setenv bootargs root=/dev/ram rw " \ 709 "console=$consoledev,$baudrate $othbootargs;" \ 710 "tftp $ramdiskaddr $ramdiskfile;" \ 711 "tftp $loadaddr $bootfile;" \ 712 "tftp $fdtaddr $fdtfile;" \ 713 "bootm $loadaddr $ramdiskaddr $fdtaddr" 714 715 716 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 717 718 #endif /* __CONFIG_H */ 719