1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #if (TEXT_BASE == 0xFE000000) 60 #define CONFIG_SYS_LOWBOOT 61 #endif 62 63 /* 64 * High Level Configuration Options 65 */ 66 #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 67 #define CONFIG_MPC8349 /* MPC8349 specific */ 68 69 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 70 71 #define CONFIG_MISC_INIT_F 72 #define CONFIG_MISC_INIT_R 73 74 /* 75 * On-board devices 76 */ 77 78 #ifdef CONFIG_MPC8349ITX 79 #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 80 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 81 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 82 #endif 83 84 #define CONFIG_PCI 85 #define CONFIG_RTC_DS1337 86 #define CONFIG_HARD_I2C 87 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 88 89 /* 90 * Device configurations 91 */ 92 93 /* I2C */ 94 #ifdef CONFIG_HARD_I2C 95 96 #define CONFIG_FSL_I2C 97 #define CONFIG_I2C_MULTI_BUS 98 #define CONFIG_I2C_CMD_TREE 99 #define CONFIG_SYS_I2C_OFFSET 0x3000 100 #define CONFIG_SYS_I2C2_OFFSET 0x3100 101 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 102 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 103 104 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 105 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 106 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 107 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 108 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 109 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 110 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 111 112 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 113 #define CONFIG_SYS_I2C_SLAVE 0x7F 114 115 /* Don't probe these addresses: */ 116 #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ 117 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 118 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 119 {1, CONFIG_SYS_I2C_8574A_ADDR2}} 120 /* Bit definitions for the 8574[A] I2C expander */ 121 #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 122 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 123 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 124 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 125 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 126 127 #undef CONFIG_SOFT_I2C 128 129 #endif 130 131 /* Compact Flash */ 132 #ifdef CONFIG_COMPACT_FLASH 133 134 #define CONFIG_SYS_IDE_MAXBUS 1 135 #define CONFIG_SYS_IDE_MAXDEVICE 1 136 137 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 138 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 139 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 140 #define CONFIG_SYS_ATA_REG_OFFSET 0 141 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 142 #define CONFIG_SYS_ATA_STRIDE 2 143 144 #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 145 146 #endif 147 148 /* 149 * SATA 150 */ 151 #ifdef CONFIG_SATA_SIL3114 152 153 #define CONFIG_SYS_SATA_MAX_DEVICE 4 154 #define CONFIG_LIBATA 155 #define CONFIG_LBA48 156 157 #endif 158 159 /* 160 * DDR Setup 161 */ 162 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 163 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 164 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 165 #define CONFIG_SYS_83XX_DDR_USES_CS0 166 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 167 #define CONFIG_SYS_MEMTEST_END 0x2000 168 169 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 170 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 171 172 #define CONFIG_VERY_BIG_RAM 173 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 174 175 #ifdef CONFIG_HARD_I2C 176 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 177 #endif 178 179 #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 180 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 181 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 182 183 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 184 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 185 #endif 186 187 /* 188 *Flash on the Local Bus 189 */ 190 191 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 192 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 193 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 199 200 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 201 boards, we say we have two, but don't display a message if we find only one. */ 202 #define CONFIG_SYS_FLASH_QUIET_TEST 203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 204 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 205 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 206 #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 207 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 208 209 /* Vitesse 7385 */ 210 211 #ifdef CONFIG_VSC7385_ENET 212 213 #define CONFIG_TSEC2 214 215 /* The flash address and size of the VSC7385 firmware image */ 216 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 217 #define CONFIG_VSC7385_IMAGE_SIZE 8192 218 219 #endif 220 221 /* 222 * BRx, ORx, LBLAWBARx, and LBLAWARx 223 */ 224 225 /* Flash */ 226 227 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 228 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 229 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 230 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 231 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 232 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 233 234 /* Vitesse 7385 */ 235 236 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 237 238 #ifdef CONFIG_VSC7385_ENET 239 240 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 241 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 242 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 243 OR_GPCM_EHTR | OR_GPCM_EAD) 244 245 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 246 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 247 248 #endif 249 250 /* LED */ 251 252 #define CONFIG_SYS_LED_BASE 0xF9000000 253 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 254 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 255 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 256 OR_GPCM_EHTR | OR_GPCM_EAD) 257 258 /* Compact Flash */ 259 260 #ifdef CONFIG_COMPACT_FLASH 261 262 #define CONFIG_SYS_CF_BASE 0xF0000000 263 264 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 265 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 266 267 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 268 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 269 270 #endif 271 272 /* 273 * U-Boot memory configuration 274 */ 275 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 276 277 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 278 #define CONFIG_SYS_RAMBOOT 279 #else 280 #undef CONFIG_SYS_RAMBOOT 281 #endif 282 283 #define CONFIG_SYS_INIT_RAM_LOCK 284 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 285 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 286 287 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 288 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 289 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 290 291 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 292 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 293 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 294 295 /* 296 * Local Bus LCRR and LBCR regs 297 * LCRR: DLL bypass, Clock divider is 4 298 * External Local Bus rate is 299 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 300 */ 301 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 302 #define CONFIG_SYS_LBC_LBCR 0x00000000 303 304 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 305 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 306 307 /* 308 * Serial Port 309 */ 310 #define CONFIG_CONS_INDEX 1 311 #undef CONFIG_SERIAL_SOFTWARE_FIFO 312 #define CONFIG_SYS_NS16550 313 #define CONFIG_SYS_NS16550_SERIAL 314 #define CONFIG_SYS_NS16550_REG_SIZE 1 315 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 316 317 #define CONFIG_SYS_BAUDRATE_TABLE \ 318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 319 320 #define CONFIG_CONSOLE ttyS0 321 #define CONFIG_BAUDRATE 115200 322 323 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 324 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 325 326 /* pass open firmware flat tree */ 327 #define CONFIG_OF_LIBFDT 1 328 #define CONFIG_OF_BOARD_SETUP 1 329 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 330 331 /* 332 * PCI 333 */ 334 #ifdef CONFIG_PCI 335 336 #define CONFIG_MPC83XX_PCI2 337 338 /* 339 * General PCI 340 * Addresses are mapped 1-1. 341 */ 342 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 343 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 344 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 345 #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 346 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 347 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 348 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 349 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 350 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 351 352 #ifdef CONFIG_MPC83XX_PCI2 353 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 354 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 355 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 356 #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 357 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 358 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 359 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 360 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 361 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 362 #endif 363 364 #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 365 366 #define CONFIG_NET_MULTI 367 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 368 369 #ifdef CONFIG_RTL8139 370 /* This macro is used by RTL8139 but not defined in PPC architecture */ 371 #define KSEG1ADDR(x) (x) 372 #endif 373 374 #ifndef CONFIG_PCI_PNP 375 #define PCI_ENET0_IOADDR 0x00000000 376 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 377 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 378 #endif 379 380 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 381 382 #endif 383 384 #define PCI_66M 385 #ifdef PCI_66M 386 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 387 #else 388 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 389 #endif 390 391 /* TSEC */ 392 393 #ifdef CONFIG_TSEC_ENET 394 395 #define CONFIG_NET_MULTI 396 #define CONFIG_MII 397 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 398 399 #define CONFIG_TSEC1 400 401 #ifdef CONFIG_TSEC1 402 #define CONFIG_HAS_ETH0 403 #define CONFIG_TSEC1_NAME "TSEC0" 404 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 405 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 406 #define TSEC1_PHYIDX 0 407 #define TSEC1_FLAGS TSEC_GIGABIT 408 #endif 409 410 #ifdef CONFIG_TSEC2 411 #define CONFIG_HAS_ETH1 412 #define CONFIG_TSEC2_NAME "TSEC1" 413 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 414 415 #define TSEC2_PHY_ADDR 4 416 #define TSEC2_PHYIDX 0 417 #define TSEC2_FLAGS TSEC_GIGABIT 418 #endif 419 420 #define CONFIG_ETHPRIME "Freescale TSEC" 421 422 #endif 423 424 /* 425 * Environment 426 */ 427 #define CONFIG_ENV_OVERWRITE 428 429 #ifndef CONFIG_SYS_RAMBOOT 430 #define CONFIG_ENV_IS_IN_FLASH 431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 432 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 433 #define CONFIG_ENV_SIZE 0x2000 434 #else 435 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 436 #undef CONFIG_FLASH_CFI_DRIVER 437 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 439 #define CONFIG_ENV_SIZE 0x2000 440 #endif 441 442 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 444 445 /* 446 * BOOTP options 447 */ 448 #define CONFIG_BOOTP_BOOTFILESIZE 449 #define CONFIG_BOOTP_BOOTPATH 450 #define CONFIG_BOOTP_GATEWAY 451 #define CONFIG_BOOTP_HOSTNAME 452 453 454 /* 455 * Command line configuration. 456 */ 457 #include <config_cmd_default.h> 458 459 #define CONFIG_CMD_CACHE 460 #define CONFIG_CMD_DATE 461 #define CONFIG_CMD_IRQ 462 #define CONFIG_CMD_NET 463 #define CONFIG_CMD_PING 464 #define CONFIG_CMD_DHCP 465 #define CONFIG_CMD_SDRAM 466 467 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) 468 #define CONFIG_DOS_PARTITION 469 #define CONFIG_CMD_FAT 470 #endif 471 472 #ifdef CONFIG_COMPACT_FLASH 473 #define CONFIG_CMD_IDE 474 #endif 475 476 #ifdef CONFIG_SATA_SIL3114 477 #define CONFIG_CMD_SATA 478 #define CONFIG_CMD_EXT2 479 #endif 480 481 #ifdef CONFIG_PCI 482 #define CONFIG_CMD_PCI 483 #endif 484 485 #ifdef CONFIG_HARD_I2C 486 #define CONFIG_CMD_I2C 487 #endif 488 489 /* Watchdog */ 490 #undef CONFIG_WATCHDOG /* watchdog disabled */ 491 492 /* 493 * Miscellaneous configurable options 494 */ 495 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 496 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 497 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 498 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 499 500 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 501 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 502 503 #ifdef CONFIG_MPC8349ITX 504 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 505 #else 506 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 507 #endif 508 509 #if defined(CONFIG_CMD_KGDB) 510 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 511 #else 512 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 513 #endif 514 515 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 516 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 517 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 518 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 519 520 /* 521 * For booting Linux, the board info and command line data 522 * have to be in the first 8 MB of memory, since this is 523 * the maximum mapped by the Linux kernel during initialization. 524 */ 525 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 526 527 #define CONFIG_SYS_HRCW_LOW (\ 528 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 529 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 530 HRCWL_CSB_TO_CLKIN_4X1 |\ 531 HRCWL_VCO_1X2 |\ 532 HRCWL_CORE_TO_CSB_2X1) 533 534 #ifdef CONFIG_SYS_LOWBOOT 535 #define CONFIG_SYS_HRCW_HIGH (\ 536 HRCWH_PCI_HOST |\ 537 HRCWH_32_BIT_PCI |\ 538 HRCWH_PCI1_ARBITER_ENABLE |\ 539 HRCWH_PCI2_ARBITER_ENABLE |\ 540 HRCWH_CORE_ENABLE |\ 541 HRCWH_FROM_0X00000100 |\ 542 HRCWH_BOOTSEQ_DISABLE |\ 543 HRCWH_SW_WATCHDOG_DISABLE |\ 544 HRCWH_ROM_LOC_LOCAL_16BIT |\ 545 HRCWH_TSEC1M_IN_GMII |\ 546 HRCWH_TSEC2M_IN_GMII ) 547 #else 548 #define CONFIG_SYS_HRCW_HIGH (\ 549 HRCWH_PCI_HOST |\ 550 HRCWH_32_BIT_PCI |\ 551 HRCWH_PCI1_ARBITER_ENABLE |\ 552 HRCWH_PCI2_ARBITER_ENABLE |\ 553 HRCWH_CORE_ENABLE |\ 554 HRCWH_FROM_0XFFF00100 |\ 555 HRCWH_BOOTSEQ_DISABLE |\ 556 HRCWH_SW_WATCHDOG_DISABLE |\ 557 HRCWH_ROM_LOC_LOCAL_16BIT |\ 558 HRCWH_TSEC1M_IN_GMII |\ 559 HRCWH_TSEC2M_IN_GMII ) 560 #endif 561 562 /* 563 * System performance 564 */ 565 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 566 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 567 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 568 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 569 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 570 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 571 572 /* 573 * System IO Config 574 */ 575 #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 576 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 577 578 #define CONFIG_SYS_HID0_INIT 0x000000000 579 #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT 580 581 #define CONFIG_SYS_HID2 HID2_HBE 582 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 583 584 /* DDR */ 585 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 586 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 587 588 /* PCI */ 589 #ifdef CONFIG_PCI 590 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 591 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 592 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 593 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 594 #else 595 #define CONFIG_SYS_IBAT1L 0 596 #define CONFIG_SYS_IBAT1U 0 597 #define CONFIG_SYS_IBAT2L 0 598 #define CONFIG_SYS_IBAT2U 0 599 #endif 600 601 #ifdef CONFIG_MPC83XX_PCI2 602 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 603 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 604 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 605 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 606 #else 607 #define CONFIG_SYS_IBAT3L 0 608 #define CONFIG_SYS_IBAT3U 0 609 #define CONFIG_SYS_IBAT4L 0 610 #define CONFIG_SYS_IBAT4U 0 611 #endif 612 613 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 614 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 615 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 616 617 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 618 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 619 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 620 621 #define CONFIG_SYS_IBAT7L 0 622 #define CONFIG_SYS_IBAT7U 0 623 624 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 625 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 626 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 627 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 628 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 629 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 630 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 631 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 632 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 633 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 634 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 635 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 636 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 637 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 638 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 639 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 640 641 /* 642 * Internal Definitions 643 * 644 * Boot Flags 645 */ 646 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 647 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 648 649 #if defined(CONFIG_CMD_KGDB) 650 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 651 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 652 #endif 653 654 655 /* 656 * Environment Configuration 657 */ 658 #define CONFIG_ENV_OVERWRITE 659 660 #ifdef CONFIG_HAS_ETH0 661 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 662 #endif 663 664 #ifdef CONFIG_HAS_ETH1 665 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 666 #endif 667 668 #define CONFIG_IPADDR 192.168.1.253 669 #define CONFIG_SERVERIP 192.168.1.1 670 #define CONFIG_GATEWAYIP 192.168.1.1 671 #define CONFIG_NETMASK 255.255.252.0 672 #define CONFIG_NETDEV eth0 673 674 #ifdef CONFIG_MPC8349ITX 675 #define CONFIG_HOSTNAME mpc8349emitx 676 #else 677 #define CONFIG_HOSTNAME mpc8349emitxgp 678 #endif 679 680 /* Default path and filenames */ 681 #define CONFIG_ROOTPATH /nfsroot/rootfs 682 #define CONFIG_BOOTFILE uImage 683 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 684 685 #ifdef CONFIG_MPC8349ITX 686 #define CONFIG_FDTFILE mpc8349emitx.dtb 687 #else 688 #define CONFIG_FDTFILE mpc8349emitxgp.dtb 689 #endif 690 691 #define CONFIG_BOOTDELAY 0 692 693 #define XMK_STR(x) #x 694 #define MK_STR(x) XMK_STR(x) 695 696 #define CONFIG_BOOTARGS \ 697 "root=/dev/nfs rw" \ 698 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 699 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 700 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 701 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 702 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 703 704 #define CONFIG_EXTRA_ENV_SETTINGS \ 705 "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 706 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 707 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 708 "tftpflash=tftpboot $loadaddr $uboot; " \ 709 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 710 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 711 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 712 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 713 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 714 "fdtaddr=400000\0" \ 715 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 716 717 #define CONFIG_NFSBOOTCOMMAND \ 718 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 719 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 720 " console=$console,$baudrate $othbootargs; " \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr - $fdtaddr" 724 725 #define CONFIG_RAMBOOTCOMMAND \ 726 "setenv bootargs root=/dev/ram rw" \ 727 " console=$console,$baudrate $othbootargs; " \ 728 "tftp $ramdiskaddr $ramdiskfile;" \ 729 "tftp $loadaddr $bootfile;" \ 730 "tftp $fdtaddr $fdtfile;" \ 731 "bootm $loadaddr $ramdiskaddr $fdtaddr" 732 733 #undef MK_STR 734 #undef XMK_STR 735 736 #endif 737