1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 9 10 Memory map: 11 12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 19 0xF001_0000-0xF001_FFFF Local bus expansion slot 20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 23 24 I2C address list: 25 Align. Board 26 Bus Addr Part No. Description Length Location 27 ---------------------------------------------------------------- 28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 29 30 I2C1 0x20 PCF8574 I2C Expander 0 U8 31 I2C1 0x21 PCF8574 I2C Expander 0 U10 32 I2C1 0x38 PCF8574A I2C Expander 0 U8 33 I2C1 0x39 PCF8574A I2C Expander 0 U10 34 I2C1 0x51 (DDR) DDR EEPROM 1 U1 35 I2C1 0x68 DS1339 RTC 1 U68 36 37 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 38 */ 39 40 #ifndef __CONFIG_H 41 #define __CONFIG_H 42 43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 44 #define CONFIG_SYS_LOWBOOT 45 #endif 46 47 /* 48 * High Level Configuration Options 49 */ 50 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 51 #define CONFIG_MPC8349 /* MPC8349 specific */ 52 53 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 54 55 #define CONFIG_MISC_INIT_F 56 #define CONFIG_MISC_INIT_R 57 58 /* 59 * On-board devices 60 */ 61 62 #ifdef CONFIG_MPC8349ITX 63 /* The CF card interface on the back of the board */ 64 #define CONFIG_COMPACT_FLASH 65 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 66 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 67 #endif 68 69 #define CONFIG_RTC_DS1337 70 #define CONFIG_SYS_I2C 71 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 72 73 /* 74 * Device configurations 75 */ 76 77 /* I2C */ 78 #ifdef CONFIG_SYS_I2C 79 #define CONFIG_SYS_I2C_FSL 80 #define CONFIG_SYS_FSL_I2C_SPEED 400000 81 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 82 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 83 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 84 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 85 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 86 87 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 88 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 89 90 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 91 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 92 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 93 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 94 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 95 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 96 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 97 98 /* Don't probe these addresses: */ 99 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 100 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 101 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 102 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 103 /* Bit definitions for the 8574[A] I2C expander */ 104 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 105 #define I2C_8574_REVISION 0x03 106 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 107 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 108 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 109 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 110 111 #endif 112 113 /* Compact Flash */ 114 #ifdef CONFIG_COMPACT_FLASH 115 116 #define CONFIG_SYS_IDE_MAXBUS 1 117 #define CONFIG_SYS_IDE_MAXDEVICE 1 118 119 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 120 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 121 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 122 #define CONFIG_SYS_ATA_REG_OFFSET 0 123 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 124 #define CONFIG_SYS_ATA_STRIDE 2 125 126 /* If a CF card is not inserted, time out quickly */ 127 #define ATA_RESET_TIME 1 128 129 #endif 130 131 /* 132 * SATA 133 */ 134 #ifdef CONFIG_SATA_SIL3114 135 136 #define CONFIG_SYS_SATA_MAX_DEVICE 4 137 #define CONFIG_LBA48 138 139 #endif 140 141 #ifdef CONFIG_SYS_USB_HOST 142 /* 143 * Support USB 144 */ 145 #define CONFIG_USB_EHCI_FSL 146 147 /* Current USB implementation supports the only USB controller, 148 * so we have to choose between the MPH or the DR ones */ 149 #if 1 150 #define CONFIG_HAS_FSL_MPH_USB 151 #else 152 #define CONFIG_HAS_FSL_DR_USB 153 #endif 154 155 #endif 156 157 /* 158 * DDR Setup 159 */ 160 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 161 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 162 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 163 #define CONFIG_SYS_83XX_DDR_USES_CS0 164 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 165 #define CONFIG_SYS_MEMTEST_END 0x2000 166 167 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 168 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 169 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 172 173 #ifdef CONFIG_SYS_I2C 174 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 175 #endif 176 177 /* No SPD? Then manually set up DDR parameters */ 178 #ifndef CONFIG_SPD_EEPROM 179 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 180 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 181 | CSCONFIG_ROW_BIT_13 \ 182 | CSCONFIG_COL_BIT_10) 183 184 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 185 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 186 #endif 187 188 /* 189 *Flash on the Local Bus 190 */ 191 192 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 193 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 194 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 /* 127 64KB sectors + 8 8KB sectors per device */ 197 #define CONFIG_SYS_MAX_FLASH_SECT 135 198 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 200 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 201 202 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 203 boards, we say we have two, but don't display a message if we find only one. */ 204 #define CONFIG_SYS_FLASH_QUIET_TEST 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CONFIG_SYS_FLASH_BANKS_LIST \ 207 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 208 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 209 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 210 211 /* Vitesse 7385 */ 212 213 #ifdef CONFIG_VSC7385_ENET 214 215 #define CONFIG_TSEC2 216 217 /* The flash address and size of the VSC7385 firmware image */ 218 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 219 #define CONFIG_VSC7385_IMAGE_SIZE 8192 220 221 #endif 222 223 /* 224 * BRx, ORx, LBLAWBARx, and LBLAWARx 225 */ 226 227 /* Flash */ 228 229 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 230 | BR_PS_16 \ 231 | BR_MS_GPCM \ 232 | BR_V) 233 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 234 | OR_UPM_XAM \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_ACS_DIV2 \ 237 | OR_GPCM_XACS \ 238 | OR_GPCM_SCY_15 \ 239 | OR_GPCM_TRLX_SET \ 240 | OR_GPCM_EHTR_SET \ 241 | OR_GPCM_EAD) 242 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 243 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 244 245 /* Vitesse 7385 */ 246 247 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 248 249 #ifdef CONFIG_VSC7385_ENET 250 251 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 252 | BR_PS_8 \ 253 | BR_MS_GPCM \ 254 | BR_V) 255 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 256 | OR_GPCM_CSNT \ 257 | OR_GPCM_XACS \ 258 | OR_GPCM_SCY_15 \ 259 | OR_GPCM_SETA \ 260 | OR_GPCM_TRLX_SET \ 261 | OR_GPCM_EHTR_SET \ 262 | OR_GPCM_EAD) 263 264 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 265 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 266 267 #endif 268 269 /* LED */ 270 271 #define CONFIG_SYS_LED_BASE 0xF9000000 272 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 273 | BR_PS_8 \ 274 | BR_MS_GPCM \ 275 | BR_V) 276 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 277 | OR_GPCM_CSNT \ 278 | OR_GPCM_ACS_DIV2 \ 279 | OR_GPCM_XACS \ 280 | OR_GPCM_SCY_9 \ 281 | OR_GPCM_TRLX_SET \ 282 | OR_GPCM_EHTR_SET \ 283 | OR_GPCM_EAD) 284 285 /* Compact Flash */ 286 287 #ifdef CONFIG_COMPACT_FLASH 288 289 #define CONFIG_SYS_CF_BASE 0xF0000000 290 291 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 292 | BR_PS_16 \ 293 | BR_MS_UPMA \ 294 | BR_V) 295 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 296 297 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 298 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 299 300 #endif 301 302 /* 303 * U-Boot memory configuration 304 */ 305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 306 307 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 308 #define CONFIG_SYS_RAMBOOT 309 #else 310 #undef CONFIG_SYS_RAMBOOT 311 #endif 312 313 #define CONFIG_SYS_INIT_RAM_LOCK 314 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 315 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 316 317 #define CONFIG_SYS_GBL_DATA_OFFSET \ 318 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 319 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 320 321 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 322 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 323 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 324 325 /* 326 * Local Bus LCRR and LBCR regs 327 * LCRR: DLL bypass, Clock divider is 4 328 * External Local Bus rate is 329 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 330 */ 331 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 332 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 333 #define CONFIG_SYS_LBC_LBCR 0x00000000 334 335 /* LB sdram refresh timer, about 6us */ 336 #define CONFIG_SYS_LBC_LSRT 0x32000000 337 /* LB refresh timer prescal, 266MHz/32*/ 338 #define CONFIG_SYS_LBC_MRTPR 0x20000000 339 340 /* 341 * Serial Port 342 */ 343 #define CONFIG_SYS_NS16550_SERIAL 344 #define CONFIG_SYS_NS16550_REG_SIZE 1 345 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 346 347 #define CONFIG_SYS_BAUDRATE_TABLE \ 348 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 349 350 #define CONSOLE ttyS0 351 352 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 353 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 354 355 /* 356 * PCI 357 */ 358 #ifdef CONFIG_PCI 359 #define CONFIG_PCI_INDIRECT_BRIDGE 360 361 #define CONFIG_MPC83XX_PCI2 362 363 /* 364 * General PCI 365 * Addresses are mapped 1-1. 366 */ 367 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 368 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 369 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 370 #define CONFIG_SYS_PCI1_MMIO_BASE \ 371 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 372 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 373 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 374 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 375 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 376 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 377 378 #ifdef CONFIG_MPC83XX_PCI2 379 #define CONFIG_SYS_PCI2_MEM_BASE \ 380 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 381 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 382 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 383 #define CONFIG_SYS_PCI2_MMIO_BASE \ 384 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 385 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 386 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 387 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 388 #define CONFIG_SYS_PCI2_IO_PHYS \ 389 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 390 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 391 #endif 392 393 #ifndef CONFIG_PCI_PNP 394 #define PCI_ENET0_IOADDR 0x00000000 395 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 396 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 397 #endif 398 399 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 400 401 #endif 402 403 #define CONFIG_PCI_66M 404 #ifdef CONFIG_PCI_66M 405 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 406 #else 407 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 408 #endif 409 410 /* TSEC */ 411 412 #ifdef CONFIG_TSEC_ENET 413 414 #define CONFIG_MII 415 416 #define CONFIG_TSEC1 417 418 #ifdef CONFIG_TSEC1 419 #define CONFIG_HAS_ETH0 420 #define CONFIG_TSEC1_NAME "TSEC0" 421 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 422 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 423 #define TSEC1_PHYIDX 0 424 #define TSEC1_FLAGS TSEC_GIGABIT 425 #endif 426 427 #ifdef CONFIG_TSEC2 428 #define CONFIG_HAS_ETH1 429 #define CONFIG_TSEC2_NAME "TSEC1" 430 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 431 432 #define TSEC2_PHY_ADDR 4 433 #define TSEC2_PHYIDX 0 434 #define TSEC2_FLAGS TSEC_GIGABIT 435 #endif 436 437 #define CONFIG_ETHPRIME "Freescale TSEC" 438 439 #endif 440 441 /* 442 * Environment 443 */ 444 #define CONFIG_ENV_OVERWRITE 445 446 #ifndef CONFIG_SYS_RAMBOOT 447 #define CONFIG_ENV_ADDR \ 448 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 449 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 450 #define CONFIG_ENV_SIZE 0x2000 451 #else 452 #undef CONFIG_FLASH_CFI_DRIVER 453 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 454 #define CONFIG_ENV_SIZE 0x2000 455 #endif 456 457 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 458 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 459 460 /* 461 * BOOTP options 462 */ 463 #define CONFIG_BOOTP_BOOTFILESIZE 464 465 /* Watchdog */ 466 #undef CONFIG_WATCHDOG /* watchdog disabled */ 467 468 /* 469 * Miscellaneous configurable options 470 */ 471 472 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 473 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 474 475 /* 476 * For booting Linux, the board info and command line data 477 * have to be in the first 256 MB of memory, since this is 478 * the maximum mapped by the Linux kernel during initialization. 479 */ 480 /* Initial Memory map for Linux*/ 481 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 482 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 483 484 #define CONFIG_SYS_HRCW_LOW (\ 485 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 486 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 487 HRCWL_CSB_TO_CLKIN_4X1 |\ 488 HRCWL_VCO_1X2 |\ 489 HRCWL_CORE_TO_CSB_2X1) 490 491 #ifdef CONFIG_SYS_LOWBOOT 492 #define CONFIG_SYS_HRCW_HIGH (\ 493 HRCWH_PCI_HOST |\ 494 HRCWH_32_BIT_PCI |\ 495 HRCWH_PCI1_ARBITER_ENABLE |\ 496 HRCWH_PCI2_ARBITER_ENABLE |\ 497 HRCWH_CORE_ENABLE |\ 498 HRCWH_FROM_0X00000100 |\ 499 HRCWH_BOOTSEQ_DISABLE |\ 500 HRCWH_SW_WATCHDOG_DISABLE |\ 501 HRCWH_ROM_LOC_LOCAL_16BIT |\ 502 HRCWH_TSEC1M_IN_GMII |\ 503 HRCWH_TSEC2M_IN_GMII) 504 #else 505 #define CONFIG_SYS_HRCW_HIGH (\ 506 HRCWH_PCI_HOST |\ 507 HRCWH_32_BIT_PCI |\ 508 HRCWH_PCI1_ARBITER_ENABLE |\ 509 HRCWH_PCI2_ARBITER_ENABLE |\ 510 HRCWH_CORE_ENABLE |\ 511 HRCWH_FROM_0XFFF00100 |\ 512 HRCWH_BOOTSEQ_DISABLE |\ 513 HRCWH_SW_WATCHDOG_DISABLE |\ 514 HRCWH_ROM_LOC_LOCAL_16BIT |\ 515 HRCWH_TSEC1M_IN_GMII |\ 516 HRCWH_TSEC2M_IN_GMII) 517 #endif 518 519 /* 520 * System performance 521 */ 522 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 523 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 524 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 525 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 526 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 527 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 528 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 529 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 530 531 /* 532 * System IO Config 533 */ 534 /* Needed for gigabit to work on TSEC 1 */ 535 #define CONFIG_SYS_SICRH SICRH_TSOBI1 536 /* USB DR as device + USB MPH as host */ 537 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 538 539 #define CONFIG_SYS_HID0_INIT 0x00000000 540 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 541 542 #define CONFIG_SYS_HID2 HID2_HBE 543 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 544 545 /* DDR */ 546 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 547 | BATL_PP_RW \ 548 | BATL_MEMCOHERENCE) 549 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 550 | BATU_BL_256M \ 551 | BATU_VS \ 552 | BATU_VP) 553 554 /* PCI */ 555 #ifdef CONFIG_PCI 556 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 557 | BATL_PP_RW \ 558 | BATL_MEMCOHERENCE) 559 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 560 | BATU_BL_256M \ 561 | BATU_VS \ 562 | BATU_VP) 563 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 564 | BATL_PP_RW \ 565 | BATL_CACHEINHIBIT \ 566 | BATL_GUARDEDSTORAGE) 567 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 568 | BATU_BL_256M \ 569 | BATU_VS \ 570 | BATU_VP) 571 #else 572 #define CONFIG_SYS_IBAT1L 0 573 #define CONFIG_SYS_IBAT1U 0 574 #define CONFIG_SYS_IBAT2L 0 575 #define CONFIG_SYS_IBAT2U 0 576 #endif 577 578 #ifdef CONFIG_MPC83XX_PCI2 579 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 580 | BATL_PP_RW \ 581 | BATL_MEMCOHERENCE) 582 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 583 | BATU_BL_256M \ 584 | BATU_VS \ 585 | BATU_VP) 586 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 587 | BATL_PP_RW \ 588 | BATL_CACHEINHIBIT \ 589 | BATL_GUARDEDSTORAGE) 590 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 591 | BATU_BL_256M \ 592 | BATU_VS \ 593 | BATU_VP) 594 #else 595 #define CONFIG_SYS_IBAT3L 0 596 #define CONFIG_SYS_IBAT3U 0 597 #define CONFIG_SYS_IBAT4L 0 598 #define CONFIG_SYS_IBAT4U 0 599 #endif 600 601 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 602 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 603 | BATL_PP_RW \ 604 | BATL_CACHEINHIBIT \ 605 | BATL_GUARDEDSTORAGE) 606 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 607 | BATU_BL_256M \ 608 | BATU_VS \ 609 | BATU_VP) 610 611 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 612 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 613 | BATL_PP_RW \ 614 | BATL_MEMCOHERENCE \ 615 | BATL_GUARDEDSTORAGE) 616 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 617 | BATU_BL_256M \ 618 | BATU_VS \ 619 | BATU_VP) 620 621 #define CONFIG_SYS_IBAT7L 0 622 #define CONFIG_SYS_IBAT7U 0 623 624 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 625 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 626 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 627 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 628 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 629 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 630 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 631 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 632 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 633 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 634 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 635 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 636 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 637 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 638 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 639 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 640 641 #if defined(CONFIG_CMD_KGDB) 642 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 643 #endif 644 645 /* 646 * Environment Configuration 647 */ 648 #define CONFIG_ENV_OVERWRITE 649 650 #define CONFIG_NETDEV "eth0" 651 652 /* Default path and filenames */ 653 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 654 #define CONFIG_BOOTFILE "uImage" 655 /* U-Boot image on TFTP server */ 656 #define CONFIG_UBOOTPATH "u-boot.bin" 657 658 #ifdef CONFIG_MPC8349ITX 659 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 660 #else 661 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 662 #endif 663 664 665 #define CONFIG_EXTRA_ENV_SETTINGS \ 666 "console=" __stringify(CONSOLE) "\0" \ 667 "netdev=" CONFIG_NETDEV "\0" \ 668 "uboot=" CONFIG_UBOOTPATH "\0" \ 669 "tftpflash=tftpboot $loadaddr $uboot; " \ 670 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 671 " +$filesize; " \ 672 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 673 " +$filesize; " \ 674 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 675 " $filesize; " \ 676 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 677 " +$filesize; " \ 678 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 679 " $filesize\0" \ 680 "fdtaddr=780000\0" \ 681 "fdtfile=" CONFIG_FDTFILE "\0" 682 683 #define CONFIG_NFSBOOTCOMMAND \ 684 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 685 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 686 " console=$console,$baudrate $othbootargs; " \ 687 "tftp $loadaddr $bootfile;" \ 688 "tftp $fdtaddr $fdtfile;" \ 689 "bootm $loadaddr - $fdtaddr" 690 691 #define CONFIG_RAMBOOTCOMMAND \ 692 "setenv bootargs root=/dev/ram rw" \ 693 " console=$console,$baudrate $othbootargs; " \ 694 "tftp $ramdiskaddr $ramdiskfile;" \ 695 "tftp $loadaddr $bootfile;" \ 696 "tftp $fdtaddr $fdtfile;" \ 697 "bootm $loadaddr $ramdiskaddr $fdtaddr" 698 699 #endif 700