1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 60 #define CONFIG_SYS_LOWBOOT 61 #endif 62 63 /* 64 * High Level Configuration Options 65 */ 66 #define CONFIG_MPC83xx 1 67 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 68 #define CONFIG_MPC8349 /* MPC8349 specific */ 69 70 #ifndef CONFIG_SYS_TEXT_BASE 71 #define CONFIG_SYS_TEXT_BASE 0xFEF00000 72 #endif 73 74 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 75 76 #define CONFIG_MISC_INIT_F 77 #define CONFIG_MISC_INIT_R 78 79 /* 80 * On-board devices 81 */ 82 83 #ifdef CONFIG_MPC8349ITX 84 /* The CF card interface on the back of the board */ 85 #define CONFIG_COMPACT_FLASH 86 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 87 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 88 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 89 #endif 90 91 #define CONFIG_PCI 92 #define CONFIG_RTC_DS1337 93 #define CONFIG_HARD_I2C 94 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 95 96 /* 97 * Device configurations 98 */ 99 100 /* I2C */ 101 #ifdef CONFIG_HARD_I2C 102 103 #define CONFIG_FSL_I2C 104 #define CONFIG_I2C_MULTI_BUS 105 #define CONFIG_SYS_I2C_OFFSET 0x3000 106 #define CONFIG_SYS_I2C2_OFFSET 0x3100 107 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 108 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 109 110 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 111 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 112 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 113 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 114 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 115 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 116 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 117 118 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 119 #define CONFIG_SYS_I2C_SLAVE 0x7F 120 121 /* Don't probe these addresses: */ 122 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 123 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 124 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 125 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 126 /* Bit definitions for the 8574[A] I2C expander */ 127 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 128 #define I2C_8574_REVISION 0x03 129 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 130 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 131 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 132 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 133 134 #endif 135 136 /* Compact Flash */ 137 #ifdef CONFIG_COMPACT_FLASH 138 139 #define CONFIG_SYS_IDE_MAXBUS 1 140 #define CONFIG_SYS_IDE_MAXDEVICE 1 141 142 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 143 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 144 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 145 #define CONFIG_SYS_ATA_REG_OFFSET 0 146 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 147 #define CONFIG_SYS_ATA_STRIDE 2 148 149 /* If a CF card is not inserted, time out quickly */ 150 #define ATA_RESET_TIME 1 151 152 #endif 153 154 /* 155 * SATA 156 */ 157 #ifdef CONFIG_SATA_SIL3114 158 159 #define CONFIG_SYS_SATA_MAX_DEVICE 4 160 #define CONFIG_LIBATA 161 #define CONFIG_LBA48 162 163 #endif 164 165 #ifdef CONFIG_SYS_USB_HOST 166 /* 167 * Support USB 168 */ 169 #define CONFIG_CMD_USB 170 #define CONFIG_USB_STORAGE 171 #define CONFIG_USB_EHCI 172 #define CONFIG_USB_EHCI_FSL 173 174 /* Current USB implementation supports the only USB controller, 175 * so we have to choose between the MPH or the DR ones */ 176 #if 1 177 #define CONFIG_HAS_FSL_MPH_USB 178 #else 179 #define CONFIG_HAS_FSL_DR_USB 180 #endif 181 182 #endif 183 184 /* 185 * DDR Setup 186 */ 187 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 189 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 190 #define CONFIG_SYS_83XX_DDR_USES_CS0 191 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 192 #define CONFIG_SYS_MEMTEST_END 0x2000 193 194 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 195 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 196 197 #define CONFIG_VERY_BIG_RAM 198 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 199 200 #ifdef CONFIG_HARD_I2C 201 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 202 #endif 203 204 /* No SPD? Then manually set up DDR parameters */ 205 #ifndef CONFIG_SPD_EEPROM 206 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 207 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 208 | CSCONFIG_ROW_BIT_13 \ 209 | CSCONFIG_COL_BIT_10) 210 211 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 212 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 213 #endif 214 215 /* 216 *Flash on the Local Bus 217 */ 218 219 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 220 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 221 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 222 #define CONFIG_SYS_FLASH_EMPTY_INFO 223 /* 127 64KB sectors + 8 8KB sectors per device */ 224 #define CONFIG_SYS_MAX_FLASH_SECT 135 225 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 226 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 227 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 228 229 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 230 boards, we say we have two, but don't display a message if we find only one. */ 231 #define CONFIG_SYS_FLASH_QUIET_TEST 232 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 233 #define CONFIG_SYS_FLASH_BANKS_LIST \ 234 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 235 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 236 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 237 238 /* Vitesse 7385 */ 239 240 #ifdef CONFIG_VSC7385_ENET 241 242 #define CONFIG_TSEC2 243 244 /* The flash address and size of the VSC7385 firmware image */ 245 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 246 #define CONFIG_VSC7385_IMAGE_SIZE 8192 247 248 #endif 249 250 /* 251 * BRx, ORx, LBLAWBARx, and LBLAWARx 252 */ 253 254 /* Flash */ 255 256 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 257 | BR_PS_16 \ 258 | BR_MS_GPCM \ 259 | BR_V) 260 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 261 | OR_UPM_XAM \ 262 | OR_GPCM_CSNT \ 263 | OR_GPCM_ACS_DIV2 \ 264 | OR_GPCM_XACS \ 265 | OR_GPCM_SCY_15 \ 266 | OR_GPCM_TRLX_SET \ 267 | OR_GPCM_EHTR_SET \ 268 | OR_GPCM_EAD) 269 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 270 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 271 272 /* Vitesse 7385 */ 273 274 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 275 276 #ifdef CONFIG_VSC7385_ENET 277 278 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 279 | BR_PS_8 \ 280 | BR_MS_GPCM \ 281 | BR_V) 282 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 283 | OR_GPCM_CSNT \ 284 | OR_GPCM_XACS \ 285 | OR_GPCM_SCY_15 \ 286 | OR_GPCM_SETA \ 287 | OR_GPCM_TRLX_SET \ 288 | OR_GPCM_EHTR_SET \ 289 | OR_GPCM_EAD) 290 291 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 292 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 293 294 #endif 295 296 /* LED */ 297 298 #define CONFIG_SYS_LED_BASE 0xF9000000 299 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 300 | BR_PS_8 \ 301 | BR_MS_GPCM \ 302 | BR_V) 303 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 304 | OR_GPCM_CSNT \ 305 | OR_GPCM_ACS_DIV2 \ 306 | OR_GPCM_XACS \ 307 | OR_GPCM_SCY_9 \ 308 | OR_GPCM_TRLX_SET \ 309 | OR_GPCM_EHTR_SET \ 310 | OR_GPCM_EAD) 311 312 /* Compact Flash */ 313 314 #ifdef CONFIG_COMPACT_FLASH 315 316 #define CONFIG_SYS_CF_BASE 0xF0000000 317 318 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 319 | BR_PS_16 \ 320 | BR_MS_UPMA \ 321 | BR_V) 322 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 323 324 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 325 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 326 327 #endif 328 329 /* 330 * U-Boot memory configuration 331 */ 332 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 333 334 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 335 #define CONFIG_SYS_RAMBOOT 336 #else 337 #undef CONFIG_SYS_RAMBOOT 338 #endif 339 340 #define CONFIG_SYS_INIT_RAM_LOCK 341 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 342 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 343 344 #define CONFIG_SYS_GBL_DATA_OFFSET \ 345 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 346 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 347 348 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 349 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 350 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 351 352 /* 353 * Local Bus LCRR and LBCR regs 354 * LCRR: DLL bypass, Clock divider is 4 355 * External Local Bus rate is 356 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 357 */ 358 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 359 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 360 #define CONFIG_SYS_LBC_LBCR 0x00000000 361 362 /* LB sdram refresh timer, about 6us */ 363 #define CONFIG_SYS_LBC_LSRT 0x32000000 364 /* LB refresh timer prescal, 266MHz/32*/ 365 #define CONFIG_SYS_LBC_MRTPR 0x20000000 366 367 /* 368 * Serial Port 369 */ 370 #define CONFIG_CONS_INDEX 1 371 #define CONFIG_SYS_NS16550 372 #define CONFIG_SYS_NS16550_SERIAL 373 #define CONFIG_SYS_NS16550_REG_SIZE 1 374 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 375 376 #define CONFIG_SYS_BAUDRATE_TABLE \ 377 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 378 379 #define CONFIG_CONSOLE ttyS0 380 #define CONFIG_BAUDRATE 115200 381 382 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 383 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 384 385 /* pass open firmware flat tree */ 386 #define CONFIG_OF_LIBFDT 1 387 #define CONFIG_OF_BOARD_SETUP 1 388 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 389 390 /* 391 * PCI 392 */ 393 #ifdef CONFIG_PCI 394 #define CONFIG_PCI_INDIRECT_BRIDGE 395 396 #define CONFIG_MPC83XX_PCI2 397 398 /* 399 * General PCI 400 * Addresses are mapped 1-1. 401 */ 402 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 403 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 404 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 405 #define CONFIG_SYS_PCI1_MMIO_BASE \ 406 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 407 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 408 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 409 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 410 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 411 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 412 413 #ifdef CONFIG_MPC83XX_PCI2 414 #define CONFIG_SYS_PCI2_MEM_BASE \ 415 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 416 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 417 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 418 #define CONFIG_SYS_PCI2_MMIO_BASE \ 419 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 420 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 421 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 422 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 423 #define CONFIG_SYS_PCI2_IO_PHYS \ 424 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 425 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 426 #endif 427 428 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 429 430 #ifndef CONFIG_PCI_PNP 431 #define PCI_ENET0_IOADDR 0x00000000 432 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 433 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 434 #endif 435 436 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 437 438 #endif 439 440 #define CONFIG_PCI_66M 441 #ifdef CONFIG_PCI_66M 442 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 443 #else 444 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 445 #endif 446 447 /* TSEC */ 448 449 #ifdef CONFIG_TSEC_ENET 450 451 #define CONFIG_MII 452 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 453 454 #define CONFIG_TSEC1 455 456 #ifdef CONFIG_TSEC1 457 #define CONFIG_HAS_ETH0 458 #define CONFIG_TSEC1_NAME "TSEC0" 459 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 460 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 461 #define TSEC1_PHYIDX 0 462 #define TSEC1_FLAGS TSEC_GIGABIT 463 #endif 464 465 #ifdef CONFIG_TSEC2 466 #define CONFIG_HAS_ETH1 467 #define CONFIG_TSEC2_NAME "TSEC1" 468 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 469 470 #define TSEC2_PHY_ADDR 4 471 #define TSEC2_PHYIDX 0 472 #define TSEC2_FLAGS TSEC_GIGABIT 473 #endif 474 475 #define CONFIG_ETHPRIME "Freescale TSEC" 476 477 #endif 478 479 /* 480 * Environment 481 */ 482 #define CONFIG_ENV_OVERWRITE 483 484 #ifndef CONFIG_SYS_RAMBOOT 485 #define CONFIG_ENV_IS_IN_FLASH 486 #define CONFIG_ENV_ADDR \ 487 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 488 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 489 #define CONFIG_ENV_SIZE 0x2000 490 #else 491 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 492 #undef CONFIG_FLASH_CFI_DRIVER 493 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 494 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 495 #define CONFIG_ENV_SIZE 0x2000 496 #endif 497 498 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 499 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 500 501 /* 502 * BOOTP options 503 */ 504 #define CONFIG_BOOTP_BOOTFILESIZE 505 #define CONFIG_BOOTP_BOOTPATH 506 #define CONFIG_BOOTP_GATEWAY 507 #define CONFIG_BOOTP_HOSTNAME 508 509 510 /* 511 * Command line configuration. 512 */ 513 #include <config_cmd_default.h> 514 515 #define CONFIG_CMD_CACHE 516 #define CONFIG_CMD_DATE 517 #define CONFIG_CMD_IRQ 518 #define CONFIG_CMD_NET 519 #define CONFIG_CMD_PING 520 #define CONFIG_CMD_DHCP 521 #define CONFIG_CMD_SDRAM 522 523 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 524 || defined(CONFIG_USB_STORAGE) 525 #define CONFIG_DOS_PARTITION 526 #define CONFIG_CMD_FAT 527 #define CONFIG_SUPPORT_VFAT 528 #endif 529 530 #ifdef CONFIG_COMPACT_FLASH 531 #define CONFIG_CMD_IDE 532 #endif 533 534 #ifdef CONFIG_SATA_SIL3114 535 #define CONFIG_CMD_SATA 536 #endif 537 538 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 539 #define CONFIG_CMD_EXT2 540 #endif 541 542 #ifdef CONFIG_PCI 543 #define CONFIG_CMD_PCI 544 #endif 545 546 #ifdef CONFIG_HARD_I2C 547 #define CONFIG_CMD_I2C 548 #endif 549 550 /* Watchdog */ 551 #undef CONFIG_WATCHDOG /* watchdog disabled */ 552 553 /* 554 * Miscellaneous configurable options 555 */ 556 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 557 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 558 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 559 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 560 561 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 562 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 563 564 #ifdef CONFIG_MPC8349ITX 565 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 566 #else 567 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 568 #endif 569 570 #if defined(CONFIG_CMD_KGDB) 571 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 572 #else 573 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 574 #endif 575 576 /* Print Buffer Size */ 577 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 578 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 579 /* Boot Argument Buffer Size */ 580 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 581 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 582 583 /* 584 * For booting Linux, the board info and command line data 585 * have to be in the first 256 MB of memory, since this is 586 * the maximum mapped by the Linux kernel during initialization. 587 */ 588 /* Initial Memory map for Linux*/ 589 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 590 591 #define CONFIG_SYS_HRCW_LOW (\ 592 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 593 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 594 HRCWL_CSB_TO_CLKIN_4X1 |\ 595 HRCWL_VCO_1X2 |\ 596 HRCWL_CORE_TO_CSB_2X1) 597 598 #ifdef CONFIG_SYS_LOWBOOT 599 #define CONFIG_SYS_HRCW_HIGH (\ 600 HRCWH_PCI_HOST |\ 601 HRCWH_32_BIT_PCI |\ 602 HRCWH_PCI1_ARBITER_ENABLE |\ 603 HRCWH_PCI2_ARBITER_ENABLE |\ 604 HRCWH_CORE_ENABLE |\ 605 HRCWH_FROM_0X00000100 |\ 606 HRCWH_BOOTSEQ_DISABLE |\ 607 HRCWH_SW_WATCHDOG_DISABLE |\ 608 HRCWH_ROM_LOC_LOCAL_16BIT |\ 609 HRCWH_TSEC1M_IN_GMII |\ 610 HRCWH_TSEC2M_IN_GMII) 611 #else 612 #define CONFIG_SYS_HRCW_HIGH (\ 613 HRCWH_PCI_HOST |\ 614 HRCWH_32_BIT_PCI |\ 615 HRCWH_PCI1_ARBITER_ENABLE |\ 616 HRCWH_PCI2_ARBITER_ENABLE |\ 617 HRCWH_CORE_ENABLE |\ 618 HRCWH_FROM_0XFFF00100 |\ 619 HRCWH_BOOTSEQ_DISABLE |\ 620 HRCWH_SW_WATCHDOG_DISABLE |\ 621 HRCWH_ROM_LOC_LOCAL_16BIT |\ 622 HRCWH_TSEC1M_IN_GMII |\ 623 HRCWH_TSEC2M_IN_GMII) 624 #endif 625 626 /* 627 * System performance 628 */ 629 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 630 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 631 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 632 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 633 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 634 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 635 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 636 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 637 638 /* 639 * System IO Config 640 */ 641 /* Needed for gigabit to work on TSEC 1 */ 642 #define CONFIG_SYS_SICRH SICRH_TSOBI1 643 /* USB DR as device + USB MPH as host */ 644 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 645 646 #define CONFIG_SYS_HID0_INIT 0x00000000 647 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 648 649 #define CONFIG_SYS_HID2 HID2_HBE 650 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 651 652 /* DDR */ 653 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 654 | BATL_PP_RW \ 655 | BATL_MEMCOHERENCE) 656 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 657 | BATU_BL_256M \ 658 | BATU_VS \ 659 | BATU_VP) 660 661 /* PCI */ 662 #ifdef CONFIG_PCI 663 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 664 | BATL_PP_RW \ 665 | BATL_MEMCOHERENCE) 666 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 667 | BATU_BL_256M \ 668 | BATU_VS \ 669 | BATU_VP) 670 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 671 | BATL_PP_RW \ 672 | BATL_CACHEINHIBIT \ 673 | BATL_GUARDEDSTORAGE) 674 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 675 | BATU_BL_256M \ 676 | BATU_VS \ 677 | BATU_VP) 678 #else 679 #define CONFIG_SYS_IBAT1L 0 680 #define CONFIG_SYS_IBAT1U 0 681 #define CONFIG_SYS_IBAT2L 0 682 #define CONFIG_SYS_IBAT2U 0 683 #endif 684 685 #ifdef CONFIG_MPC83XX_PCI2 686 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 687 | BATL_PP_RW \ 688 | BATL_MEMCOHERENCE) 689 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 690 | BATU_BL_256M \ 691 | BATU_VS \ 692 | BATU_VP) 693 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 694 | BATL_PP_RW \ 695 | BATL_CACHEINHIBIT \ 696 | BATL_GUARDEDSTORAGE) 697 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 698 | BATU_BL_256M \ 699 | BATU_VS \ 700 | BATU_VP) 701 #else 702 #define CONFIG_SYS_IBAT3L 0 703 #define CONFIG_SYS_IBAT3U 0 704 #define CONFIG_SYS_IBAT4L 0 705 #define CONFIG_SYS_IBAT4U 0 706 #endif 707 708 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 709 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 710 | BATL_PP_RW \ 711 | BATL_CACHEINHIBIT \ 712 | BATL_GUARDEDSTORAGE) 713 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 714 | BATU_BL_256M \ 715 | BATU_VS \ 716 | BATU_VP) 717 718 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 719 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 720 | BATL_PP_RW \ 721 | BATL_MEMCOHERENCE \ 722 | BATL_GUARDEDSTORAGE) 723 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 724 | BATU_BL_256M \ 725 | BATU_VS \ 726 | BATU_VP) 727 728 #define CONFIG_SYS_IBAT7L 0 729 #define CONFIG_SYS_IBAT7U 0 730 731 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 732 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 733 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 734 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 735 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 736 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 737 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 738 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 739 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 740 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 741 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 742 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 743 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 744 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 745 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 746 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 747 748 #if defined(CONFIG_CMD_KGDB) 749 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 750 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 751 #endif 752 753 754 /* 755 * Environment Configuration 756 */ 757 #define CONFIG_ENV_OVERWRITE 758 759 #define CONFIG_NETDEV "eth0" 760 761 #ifdef CONFIG_MPC8349ITX 762 #define CONFIG_HOSTNAME "mpc8349emitx" 763 #else 764 #define CONFIG_HOSTNAME "mpc8349emitxgp" 765 #endif 766 767 /* Default path and filenames */ 768 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 769 #define CONFIG_BOOTFILE "uImage" 770 /* U-Boot image on TFTP server */ 771 #define CONFIG_UBOOTPATH "u-boot.bin" 772 773 #ifdef CONFIG_MPC8349ITX 774 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 775 #else 776 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 777 #endif 778 779 #define CONFIG_BOOTDELAY 6 780 781 #define CONFIG_BOOTARGS \ 782 "root=/dev/nfs rw" \ 783 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 784 " ip=" __stringify(CONFIG_IPADDR) ":" \ 785 __stringify(CONFIG_SERVERIP) ":" \ 786 __stringify(CONFIG_GATEWAYIP) ":" \ 787 __stringify(CONFIG_NETMASK) ":" \ 788 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 789 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 790 791 #define CONFIG_EXTRA_ENV_SETTINGS \ 792 "console=" __stringify(CONFIG_CONSOLE) "\0" \ 793 "netdev=" CONFIG_NETDEV "\0" \ 794 "uboot=" CONFIG_UBOOTPATH "\0" \ 795 "tftpflash=tftpboot $loadaddr $uboot; " \ 796 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 797 " +$filesize; " \ 798 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 799 " +$filesize; " \ 800 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 801 " $filesize; " \ 802 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 803 " +$filesize; " \ 804 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 805 " $filesize\0" \ 806 "fdtaddr=780000\0" \ 807 "fdtfile=" CONFIG_FDTFILE "\0" 808 809 #define CONFIG_NFSBOOTCOMMAND \ 810 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 811 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 812 " console=$console,$baudrate $othbootargs; " \ 813 "tftp $loadaddr $bootfile;" \ 814 "tftp $fdtaddr $fdtfile;" \ 815 "bootm $loadaddr - $fdtaddr" 816 817 #define CONFIG_RAMBOOTCOMMAND \ 818 "setenv bootargs root=/dev/ram rw" \ 819 " console=$console,$baudrate $othbootargs; " \ 820 "tftp $ramdiskaddr $ramdiskfile;" \ 821 "tftp $loadaddr $bootfile;" \ 822 "tftp $fdtaddr $fdtfile;" \ 823 "bootm $loadaddr $ramdiskaddr $fdtaddr" 824 825 #endif 826