1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 9 10 Memory map: 11 12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 19 0xF001_0000-0xF001_FFFF Local bus expansion slot 20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 23 24 I2C address list: 25 Align. Board 26 Bus Addr Part No. Description Length Location 27 ---------------------------------------------------------------- 28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 29 30 I2C1 0x20 PCF8574 I2C Expander 0 U8 31 I2C1 0x21 PCF8574 I2C Expander 0 U10 32 I2C1 0x38 PCF8574A I2C Expander 0 U8 33 I2C1 0x39 PCF8574A I2C Expander 0 U10 34 I2C1 0x51 (DDR) DDR EEPROM 1 U1 35 I2C1 0x68 DS1339 RTC 1 U68 36 37 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 38 */ 39 40 #ifndef __CONFIG_H 41 #define __CONFIG_H 42 43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 44 #define CONFIG_SYS_LOWBOOT 45 #endif 46 47 /* 48 * High Level Configuration Options 49 */ 50 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 51 #define CONFIG_MPC8349 /* MPC8349 specific */ 52 53 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 54 55 #define CONFIG_MISC_INIT_F 56 #define CONFIG_MISC_INIT_R 57 58 /* 59 * On-board devices 60 */ 61 62 #ifdef CONFIG_MPC8349ITX 63 /* The CF card interface on the back of the board */ 64 #define CONFIG_COMPACT_FLASH 65 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 66 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 67 #endif 68 69 #define CONFIG_RTC_DS1337 70 #define CONFIG_SYS_I2C 71 72 /* 73 * Device configurations 74 */ 75 76 /* I2C */ 77 #ifdef CONFIG_SYS_I2C 78 #define CONFIG_SYS_I2C_FSL 79 #define CONFIG_SYS_FSL_I2C_SPEED 400000 80 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 81 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 82 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 83 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 84 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 85 86 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 87 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 88 89 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 90 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 91 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 92 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 93 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 94 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 95 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 96 97 /* Don't probe these addresses: */ 98 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 99 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 100 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 101 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 102 /* Bit definitions for the 8574[A] I2C expander */ 103 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 104 #define I2C_8574_REVISION 0x03 105 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 106 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 107 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 108 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 109 110 #endif 111 112 /* Compact Flash */ 113 #ifdef CONFIG_COMPACT_FLASH 114 115 #define CONFIG_SYS_IDE_MAXBUS 1 116 #define CONFIG_SYS_IDE_MAXDEVICE 1 117 118 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 119 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 120 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 121 #define CONFIG_SYS_ATA_REG_OFFSET 0 122 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 123 #define CONFIG_SYS_ATA_STRIDE 2 124 125 /* If a CF card is not inserted, time out quickly */ 126 #define ATA_RESET_TIME 1 127 128 #endif 129 130 /* 131 * SATA 132 */ 133 #ifdef CONFIG_SATA_SIL3114 134 135 #define CONFIG_SYS_SATA_MAX_DEVICE 4 136 #define CONFIG_LBA48 137 138 #endif 139 140 #ifdef CONFIG_SYS_USB_HOST 141 /* 142 * Support USB 143 */ 144 #define CONFIG_USB_EHCI_FSL 145 146 /* Current USB implementation supports the only USB controller, 147 * so we have to choose between the MPH or the DR ones */ 148 #if 1 149 #define CONFIG_HAS_FSL_MPH_USB 150 #else 151 #define CONFIG_HAS_FSL_DR_USB 152 #endif 153 154 #endif 155 156 /* 157 * DDR Setup 158 */ 159 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 161 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 162 #define CONFIG_SYS_83XX_DDR_USES_CS0 163 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 164 #define CONFIG_SYS_MEMTEST_END 0x2000 165 166 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 167 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 168 169 #define CONFIG_VERY_BIG_RAM 170 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 171 172 #ifdef CONFIG_SYS_I2C 173 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 174 #endif 175 176 /* No SPD? Then manually set up DDR parameters */ 177 #ifndef CONFIG_SPD_EEPROM 178 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 179 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 180 | CSCONFIG_ROW_BIT_13 \ 181 | CSCONFIG_COL_BIT_10) 182 183 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 184 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 185 #endif 186 187 /* 188 *Flash on the Local Bus 189 */ 190 191 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 192 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 193 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 /* 127 64KB sectors + 8 8KB sectors per device */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 135 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 199 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 200 201 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 202 boards, we say we have two, but don't display a message if we find only one. */ 203 #define CONFIG_SYS_FLASH_QUIET_TEST 204 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 205 #define CONFIG_SYS_FLASH_BANKS_LIST \ 206 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 207 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 208 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 209 210 /* Vitesse 7385 */ 211 212 #ifdef CONFIG_VSC7385_ENET 213 214 #define CONFIG_TSEC2 215 216 /* The flash address and size of the VSC7385 firmware image */ 217 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 218 #define CONFIG_VSC7385_IMAGE_SIZE 8192 219 220 #endif 221 222 /* 223 * BRx, ORx, LBLAWBARx, and LBLAWARx 224 */ 225 226 /* Flash */ 227 228 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 229 | BR_PS_16 \ 230 | BR_MS_GPCM \ 231 | BR_V) 232 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 233 | OR_UPM_XAM \ 234 | OR_GPCM_CSNT \ 235 | OR_GPCM_ACS_DIV2 \ 236 | OR_GPCM_XACS \ 237 | OR_GPCM_SCY_15 \ 238 | OR_GPCM_TRLX_SET \ 239 | OR_GPCM_EHTR_SET \ 240 | OR_GPCM_EAD) 241 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 242 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 243 244 /* Vitesse 7385 */ 245 246 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 247 248 #ifdef CONFIG_VSC7385_ENET 249 250 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 251 | BR_PS_8 \ 252 | BR_MS_GPCM \ 253 | BR_V) 254 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 255 | OR_GPCM_CSNT \ 256 | OR_GPCM_XACS \ 257 | OR_GPCM_SCY_15 \ 258 | OR_GPCM_SETA \ 259 | OR_GPCM_TRLX_SET \ 260 | OR_GPCM_EHTR_SET \ 261 | OR_GPCM_EAD) 262 263 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 264 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 265 266 #endif 267 268 /* LED */ 269 270 #define CONFIG_SYS_LED_BASE 0xF9000000 271 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 272 | BR_PS_8 \ 273 | BR_MS_GPCM \ 274 | BR_V) 275 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 276 | OR_GPCM_CSNT \ 277 | OR_GPCM_ACS_DIV2 \ 278 | OR_GPCM_XACS \ 279 | OR_GPCM_SCY_9 \ 280 | OR_GPCM_TRLX_SET \ 281 | OR_GPCM_EHTR_SET \ 282 | OR_GPCM_EAD) 283 284 /* Compact Flash */ 285 286 #ifdef CONFIG_COMPACT_FLASH 287 288 #define CONFIG_SYS_CF_BASE 0xF0000000 289 290 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 291 | BR_PS_16 \ 292 | BR_MS_UPMA \ 293 | BR_V) 294 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 295 296 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 297 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 298 299 #endif 300 301 /* 302 * U-Boot memory configuration 303 */ 304 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 305 306 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 307 #define CONFIG_SYS_RAMBOOT 308 #else 309 #undef CONFIG_SYS_RAMBOOT 310 #endif 311 312 #define CONFIG_SYS_INIT_RAM_LOCK 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 314 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 315 316 #define CONFIG_SYS_GBL_DATA_OFFSET \ 317 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 318 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 319 320 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 321 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 322 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 323 324 /* 325 * Local Bus LCRR and LBCR regs 326 * LCRR: DLL bypass, Clock divider is 4 327 * External Local Bus rate is 328 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 329 */ 330 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 331 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 332 #define CONFIG_SYS_LBC_LBCR 0x00000000 333 334 /* LB sdram refresh timer, about 6us */ 335 #define CONFIG_SYS_LBC_LSRT 0x32000000 336 /* LB refresh timer prescal, 266MHz/32*/ 337 #define CONFIG_SYS_LBC_MRTPR 0x20000000 338 339 /* 340 * Serial Port 341 */ 342 #define CONFIG_SYS_NS16550_SERIAL 343 #define CONFIG_SYS_NS16550_REG_SIZE 1 344 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 345 346 #define CONFIG_SYS_BAUDRATE_TABLE \ 347 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 348 349 #define CONSOLE ttyS0 350 351 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 352 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 353 354 /* 355 * PCI 356 */ 357 #ifdef CONFIG_PCI 358 #define CONFIG_PCI_INDIRECT_BRIDGE 359 360 #define CONFIG_MPC83XX_PCI2 361 362 /* 363 * General PCI 364 * Addresses are mapped 1-1. 365 */ 366 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 367 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 368 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 369 #define CONFIG_SYS_PCI1_MMIO_BASE \ 370 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 371 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 372 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 373 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 374 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 375 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 376 377 #ifdef CONFIG_MPC83XX_PCI2 378 #define CONFIG_SYS_PCI2_MEM_BASE \ 379 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 380 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 381 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 382 #define CONFIG_SYS_PCI2_MMIO_BASE \ 383 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 384 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 385 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 386 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 387 #define CONFIG_SYS_PCI2_IO_PHYS \ 388 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 389 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 390 #endif 391 392 #ifndef CONFIG_PCI_PNP 393 #define PCI_ENET0_IOADDR 0x00000000 394 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 395 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 396 #endif 397 398 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 399 400 #endif 401 402 #define CONFIG_PCI_66M 403 #ifdef CONFIG_PCI_66M 404 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 405 #else 406 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 407 #endif 408 409 /* TSEC */ 410 411 #ifdef CONFIG_TSEC_ENET 412 413 #define CONFIG_MII 414 415 #define CONFIG_TSEC1 416 417 #ifdef CONFIG_TSEC1 418 #define CONFIG_HAS_ETH0 419 #define CONFIG_TSEC1_NAME "TSEC0" 420 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 421 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 422 #define TSEC1_PHYIDX 0 423 #define TSEC1_FLAGS TSEC_GIGABIT 424 #endif 425 426 #ifdef CONFIG_TSEC2 427 #define CONFIG_HAS_ETH1 428 #define CONFIG_TSEC2_NAME "TSEC1" 429 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 430 431 #define TSEC2_PHY_ADDR 4 432 #define TSEC2_PHYIDX 0 433 #define TSEC2_FLAGS TSEC_GIGABIT 434 #endif 435 436 #define CONFIG_ETHPRIME "Freescale TSEC" 437 438 #endif 439 440 /* 441 * Environment 442 */ 443 #define CONFIG_ENV_OVERWRITE 444 445 #ifndef CONFIG_SYS_RAMBOOT 446 #define CONFIG_ENV_ADDR \ 447 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 448 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 449 #define CONFIG_ENV_SIZE 0x2000 450 #else 451 #undef CONFIG_FLASH_CFI_DRIVER 452 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 453 #define CONFIG_ENV_SIZE 0x2000 454 #endif 455 456 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 457 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 458 459 /* 460 * BOOTP options 461 */ 462 #define CONFIG_BOOTP_BOOTFILESIZE 463 464 /* Watchdog */ 465 #undef CONFIG_WATCHDOG /* watchdog disabled */ 466 467 /* 468 * Miscellaneous configurable options 469 */ 470 471 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 472 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 473 474 /* 475 * For booting Linux, the board info and command line data 476 * have to be in the first 256 MB of memory, since this is 477 * the maximum mapped by the Linux kernel during initialization. 478 */ 479 /* Initial Memory map for Linux*/ 480 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 481 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 482 483 #define CONFIG_SYS_HRCW_LOW (\ 484 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 485 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 486 HRCWL_CSB_TO_CLKIN_4X1 |\ 487 HRCWL_VCO_1X2 |\ 488 HRCWL_CORE_TO_CSB_2X1) 489 490 #ifdef CONFIG_SYS_LOWBOOT 491 #define CONFIG_SYS_HRCW_HIGH (\ 492 HRCWH_PCI_HOST |\ 493 HRCWH_32_BIT_PCI |\ 494 HRCWH_PCI1_ARBITER_ENABLE |\ 495 HRCWH_PCI2_ARBITER_ENABLE |\ 496 HRCWH_CORE_ENABLE |\ 497 HRCWH_FROM_0X00000100 |\ 498 HRCWH_BOOTSEQ_DISABLE |\ 499 HRCWH_SW_WATCHDOG_DISABLE |\ 500 HRCWH_ROM_LOC_LOCAL_16BIT |\ 501 HRCWH_TSEC1M_IN_GMII |\ 502 HRCWH_TSEC2M_IN_GMII) 503 #else 504 #define CONFIG_SYS_HRCW_HIGH (\ 505 HRCWH_PCI_HOST |\ 506 HRCWH_32_BIT_PCI |\ 507 HRCWH_PCI1_ARBITER_ENABLE |\ 508 HRCWH_PCI2_ARBITER_ENABLE |\ 509 HRCWH_CORE_ENABLE |\ 510 HRCWH_FROM_0XFFF00100 |\ 511 HRCWH_BOOTSEQ_DISABLE |\ 512 HRCWH_SW_WATCHDOG_DISABLE |\ 513 HRCWH_ROM_LOC_LOCAL_16BIT |\ 514 HRCWH_TSEC1M_IN_GMII |\ 515 HRCWH_TSEC2M_IN_GMII) 516 #endif 517 518 /* 519 * System performance 520 */ 521 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 522 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 523 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 524 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 525 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 526 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 527 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 528 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 529 530 /* 531 * System IO Config 532 */ 533 /* Needed for gigabit to work on TSEC 1 */ 534 #define CONFIG_SYS_SICRH SICRH_TSOBI1 535 /* USB DR as device + USB MPH as host */ 536 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 537 538 #define CONFIG_SYS_HID0_INIT 0x00000000 539 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 540 541 #define CONFIG_SYS_HID2 HID2_HBE 542 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 543 544 /* DDR */ 545 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 546 | BATL_PP_RW \ 547 | BATL_MEMCOHERENCE) 548 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 549 | BATU_BL_256M \ 550 | BATU_VS \ 551 | BATU_VP) 552 553 /* PCI */ 554 #ifdef CONFIG_PCI 555 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 556 | BATL_PP_RW \ 557 | BATL_MEMCOHERENCE) 558 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 559 | BATU_BL_256M \ 560 | BATU_VS \ 561 | BATU_VP) 562 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 563 | BATL_PP_RW \ 564 | BATL_CACHEINHIBIT \ 565 | BATL_GUARDEDSTORAGE) 566 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 567 | BATU_BL_256M \ 568 | BATU_VS \ 569 | BATU_VP) 570 #else 571 #define CONFIG_SYS_IBAT1L 0 572 #define CONFIG_SYS_IBAT1U 0 573 #define CONFIG_SYS_IBAT2L 0 574 #define CONFIG_SYS_IBAT2U 0 575 #endif 576 577 #ifdef CONFIG_MPC83XX_PCI2 578 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 579 | BATL_PP_RW \ 580 | BATL_MEMCOHERENCE) 581 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 582 | BATU_BL_256M \ 583 | BATU_VS \ 584 | BATU_VP) 585 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 586 | BATL_PP_RW \ 587 | BATL_CACHEINHIBIT \ 588 | BATL_GUARDEDSTORAGE) 589 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 590 | BATU_BL_256M \ 591 | BATU_VS \ 592 | BATU_VP) 593 #else 594 #define CONFIG_SYS_IBAT3L 0 595 #define CONFIG_SYS_IBAT3U 0 596 #define CONFIG_SYS_IBAT4L 0 597 #define CONFIG_SYS_IBAT4U 0 598 #endif 599 600 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 601 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 602 | BATL_PP_RW \ 603 | BATL_CACHEINHIBIT \ 604 | BATL_GUARDEDSTORAGE) 605 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 606 | BATU_BL_256M \ 607 | BATU_VS \ 608 | BATU_VP) 609 610 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 611 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 612 | BATL_PP_RW \ 613 | BATL_MEMCOHERENCE \ 614 | BATL_GUARDEDSTORAGE) 615 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 616 | BATU_BL_256M \ 617 | BATU_VS \ 618 | BATU_VP) 619 620 #define CONFIG_SYS_IBAT7L 0 621 #define CONFIG_SYS_IBAT7U 0 622 623 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 624 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 625 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 626 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 627 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 628 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 629 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 630 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 631 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 632 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 633 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 634 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 635 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 636 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 637 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 638 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 639 640 #if defined(CONFIG_CMD_KGDB) 641 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 642 #endif 643 644 /* 645 * Environment Configuration 646 */ 647 #define CONFIG_ENV_OVERWRITE 648 649 #define CONFIG_NETDEV "eth0" 650 651 /* Default path and filenames */ 652 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 653 #define CONFIG_BOOTFILE "uImage" 654 /* U-Boot image on TFTP server */ 655 #define CONFIG_UBOOTPATH "u-boot.bin" 656 657 #ifdef CONFIG_MPC8349ITX 658 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 659 #else 660 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 661 #endif 662 663 664 #define CONFIG_EXTRA_ENV_SETTINGS \ 665 "console=" __stringify(CONSOLE) "\0" \ 666 "netdev=" CONFIG_NETDEV "\0" \ 667 "uboot=" CONFIG_UBOOTPATH "\0" \ 668 "tftpflash=tftpboot $loadaddr $uboot; " \ 669 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 670 " +$filesize; " \ 671 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 672 " +$filesize; " \ 673 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 674 " $filesize; " \ 675 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 676 " +$filesize; " \ 677 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 678 " $filesize\0" \ 679 "fdtaddr=780000\0" \ 680 "fdtfile=" CONFIG_FDTFILE "\0" 681 682 #define CONFIG_NFSBOOTCOMMAND \ 683 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 684 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 685 " console=$console,$baudrate $othbootargs; " \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr - $fdtaddr" 689 690 #define CONFIG_RAMBOOTCOMMAND \ 691 "setenv bootargs root=/dev/ram rw" \ 692 " console=$console,$baudrate $othbootargs; " \ 693 "tftp $ramdiskaddr $ramdiskfile;" \ 694 "tftp $loadaddr $bootfile;" \ 695 "tftp $fdtaddr $fdtfile;" \ 696 "bootm $loadaddr $ramdiskaddr $fdtaddr" 697 698 #endif 699