1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 */ 5 6 /* 7 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 8 9 Memory map: 10 11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 18 0xF001_0000-0xF001_FFFF Local bus expansion slot 19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 22 23 I2C address list: 24 Align. Board 25 Bus Addr Part No. Description Length Location 26 ---------------------------------------------------------------- 27 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 28 29 I2C1 0x20 PCF8574 I2C Expander 0 U8 30 I2C1 0x21 PCF8574 I2C Expander 0 U10 31 I2C1 0x38 PCF8574A I2C Expander 0 U8 32 I2C1 0x39 PCF8574A I2C Expander 0 U10 33 I2C1 0x51 (DDR) DDR EEPROM 1 U1 34 I2C1 0x68 DS1339 RTC 1 U68 35 36 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 37 */ 38 39 #ifndef __CONFIG_H 40 #define __CONFIG_H 41 42 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 43 #define CONFIG_SYS_LOWBOOT 44 #endif 45 46 /* 47 * High Level Configuration Options 48 */ 49 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 50 #define CONFIG_MPC8349 /* MPC8349 specific */ 51 52 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 53 54 #define CONFIG_MISC_INIT_F 55 #define CONFIG_MISC_INIT_R 56 57 /* 58 * On-board devices 59 */ 60 61 #ifdef CONFIG_MPC8349ITX 62 /* The CF card interface on the back of the board */ 63 #define CONFIG_COMPACT_FLASH 64 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 65 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 66 #endif 67 68 #define CONFIG_RTC_DS1337 69 #define CONFIG_SYS_I2C 70 71 /* 72 * Device configurations 73 */ 74 75 /* I2C */ 76 #ifdef CONFIG_SYS_I2C 77 #define CONFIG_SYS_I2C_FSL 78 #define CONFIG_SYS_FSL_I2C_SPEED 400000 79 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 80 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 81 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 82 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 83 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 84 85 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 86 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 87 88 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 89 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 90 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 91 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 92 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 93 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 94 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 95 96 /* Don't probe these addresses: */ 97 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 98 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 99 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 100 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 101 /* Bit definitions for the 8574[A] I2C expander */ 102 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 103 #define I2C_8574_REVISION 0x03 104 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 105 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 106 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 107 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 108 109 #endif 110 111 /* Compact Flash */ 112 #ifdef CONFIG_COMPACT_FLASH 113 114 #define CONFIG_SYS_IDE_MAXBUS 1 115 #define CONFIG_SYS_IDE_MAXDEVICE 1 116 117 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 118 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 119 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 120 #define CONFIG_SYS_ATA_REG_OFFSET 0 121 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 122 #define CONFIG_SYS_ATA_STRIDE 2 123 124 /* If a CF card is not inserted, time out quickly */ 125 #define ATA_RESET_TIME 1 126 127 #endif 128 129 /* 130 * SATA 131 */ 132 #ifdef CONFIG_SATA_SIL3114 133 134 #define CONFIG_SYS_SATA_MAX_DEVICE 4 135 #define CONFIG_LBA48 136 137 #endif 138 139 #ifdef CONFIG_SYS_USB_HOST 140 /* 141 * Support USB 142 */ 143 #define CONFIG_USB_EHCI_FSL 144 145 /* Current USB implementation supports the only USB controller, 146 * so we have to choose between the MPH or the DR ones */ 147 #if 1 148 #define CONFIG_HAS_FSL_MPH_USB 149 #else 150 #define CONFIG_HAS_FSL_DR_USB 151 #endif 152 153 #endif 154 155 /* 156 * DDR Setup 157 */ 158 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 159 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 160 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 161 #define CONFIG_SYS_83XX_DDR_USES_CS0 162 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 163 #define CONFIG_SYS_MEMTEST_END 0x2000 164 165 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 166 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 167 168 #define CONFIG_VERY_BIG_RAM 169 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 170 171 #ifdef CONFIG_SYS_I2C 172 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 173 #endif 174 175 /* No SPD? Then manually set up DDR parameters */ 176 #ifndef CONFIG_SPD_EEPROM 177 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 178 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 179 | CSCONFIG_ROW_BIT_13 \ 180 | CSCONFIG_COL_BIT_10) 181 182 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 183 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 184 #endif 185 186 /* 187 *Flash on the Local Bus 188 */ 189 190 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 191 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 192 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 193 #define CONFIG_SYS_FLASH_EMPTY_INFO 194 /* 127 64KB sectors + 8 8KB sectors per device */ 195 #define CONFIG_SYS_MAX_FLASH_SECT 135 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 199 200 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 201 boards, we say we have two, but don't display a message if we find only one. */ 202 #define CONFIG_SYS_FLASH_QUIET_TEST 203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 204 #define CONFIG_SYS_FLASH_BANKS_LIST \ 205 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 206 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 207 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 208 209 /* Vitesse 7385 */ 210 211 #ifdef CONFIG_VSC7385_ENET 212 213 #define CONFIG_TSEC2 214 215 /* The flash address and size of the VSC7385 firmware image */ 216 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 217 #define CONFIG_VSC7385_IMAGE_SIZE 8192 218 219 #endif 220 221 /* 222 * BRx, ORx, LBLAWBARx, and LBLAWARx 223 */ 224 225 /* Flash */ 226 227 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 228 | BR_PS_16 \ 229 | BR_MS_GPCM \ 230 | BR_V) 231 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 232 | OR_UPM_XAM \ 233 | OR_GPCM_CSNT \ 234 | OR_GPCM_ACS_DIV2 \ 235 | OR_GPCM_XACS \ 236 | OR_GPCM_SCY_15 \ 237 | OR_GPCM_TRLX_SET \ 238 | OR_GPCM_EHTR_SET \ 239 | OR_GPCM_EAD) 240 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 241 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 242 243 /* Vitesse 7385 */ 244 245 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 246 247 #ifdef CONFIG_VSC7385_ENET 248 249 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 250 | BR_PS_8 \ 251 | BR_MS_GPCM \ 252 | BR_V) 253 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 254 | OR_GPCM_CSNT \ 255 | OR_GPCM_XACS \ 256 | OR_GPCM_SCY_15 \ 257 | OR_GPCM_SETA \ 258 | OR_GPCM_TRLX_SET \ 259 | OR_GPCM_EHTR_SET \ 260 | OR_GPCM_EAD) 261 262 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 263 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 264 265 #endif 266 267 /* LED */ 268 269 #define CONFIG_SYS_LED_BASE 0xF9000000 270 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 271 | BR_PS_8 \ 272 | BR_MS_GPCM \ 273 | BR_V) 274 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 275 | OR_GPCM_CSNT \ 276 | OR_GPCM_ACS_DIV2 \ 277 | OR_GPCM_XACS \ 278 | OR_GPCM_SCY_9 \ 279 | OR_GPCM_TRLX_SET \ 280 | OR_GPCM_EHTR_SET \ 281 | OR_GPCM_EAD) 282 283 /* Compact Flash */ 284 285 #ifdef CONFIG_COMPACT_FLASH 286 287 #define CONFIG_SYS_CF_BASE 0xF0000000 288 289 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 290 | BR_PS_16 \ 291 | BR_MS_UPMA \ 292 | BR_V) 293 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 294 295 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 296 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 297 298 #endif 299 300 /* 301 * U-Boot memory configuration 302 */ 303 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 304 305 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 306 #define CONFIG_SYS_RAMBOOT 307 #else 308 #undef CONFIG_SYS_RAMBOOT 309 #endif 310 311 #define CONFIG_SYS_INIT_RAM_LOCK 312 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 313 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 314 315 #define CONFIG_SYS_GBL_DATA_OFFSET \ 316 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 317 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 318 319 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 320 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 321 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 322 323 /* 324 * Local Bus LCRR and LBCR regs 325 * LCRR: DLL bypass, Clock divider is 4 326 * External Local Bus rate is 327 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 328 */ 329 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 330 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 331 #define CONFIG_SYS_LBC_LBCR 0x00000000 332 333 /* LB sdram refresh timer, about 6us */ 334 #define CONFIG_SYS_LBC_LSRT 0x32000000 335 /* LB refresh timer prescal, 266MHz/32*/ 336 #define CONFIG_SYS_LBC_MRTPR 0x20000000 337 338 /* 339 * Serial Port 340 */ 341 #define CONFIG_SYS_NS16550_SERIAL 342 #define CONFIG_SYS_NS16550_REG_SIZE 1 343 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 344 345 #define CONFIG_SYS_BAUDRATE_TABLE \ 346 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 347 348 #define CONSOLE ttyS0 349 350 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 351 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 352 353 /* 354 * PCI 355 */ 356 #ifdef CONFIG_PCI 357 #define CONFIG_PCI_INDIRECT_BRIDGE 358 359 #define CONFIG_MPC83XX_PCI2 360 361 /* 362 * General PCI 363 * Addresses are mapped 1-1. 364 */ 365 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 366 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 367 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 368 #define CONFIG_SYS_PCI1_MMIO_BASE \ 369 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 370 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 371 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 372 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 373 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 374 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 375 376 #ifdef CONFIG_MPC83XX_PCI2 377 #define CONFIG_SYS_PCI2_MEM_BASE \ 378 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 379 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 380 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 381 #define CONFIG_SYS_PCI2_MMIO_BASE \ 382 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 383 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 384 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 385 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 386 #define CONFIG_SYS_PCI2_IO_PHYS \ 387 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 388 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 389 #endif 390 391 #ifndef CONFIG_PCI_PNP 392 #define PCI_ENET0_IOADDR 0x00000000 393 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 394 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 395 #endif 396 397 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 398 399 #endif 400 401 #define CONFIG_PCI_66M 402 #ifdef CONFIG_PCI_66M 403 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 404 #else 405 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 406 #endif 407 408 /* TSEC */ 409 410 #ifdef CONFIG_TSEC_ENET 411 412 #define CONFIG_MII 413 414 #define CONFIG_TSEC1 415 416 #ifdef CONFIG_TSEC1 417 #define CONFIG_HAS_ETH0 418 #define CONFIG_TSEC1_NAME "TSEC0" 419 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 420 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 421 #define TSEC1_PHYIDX 0 422 #define TSEC1_FLAGS TSEC_GIGABIT 423 #endif 424 425 #ifdef CONFIG_TSEC2 426 #define CONFIG_HAS_ETH1 427 #define CONFIG_TSEC2_NAME "TSEC1" 428 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 429 430 #define TSEC2_PHY_ADDR 4 431 #define TSEC2_PHYIDX 0 432 #define TSEC2_FLAGS TSEC_GIGABIT 433 #endif 434 435 #define CONFIG_ETHPRIME "Freescale TSEC" 436 437 #endif 438 439 /* 440 * Environment 441 */ 442 #define CONFIG_ENV_OVERWRITE 443 444 #ifndef CONFIG_SYS_RAMBOOT 445 #define CONFIG_ENV_ADDR \ 446 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 447 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 448 #define CONFIG_ENV_SIZE 0x2000 449 #else 450 #undef CONFIG_FLASH_CFI_DRIVER 451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 452 #define CONFIG_ENV_SIZE 0x2000 453 #endif 454 455 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 456 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 457 458 /* 459 * BOOTP options 460 */ 461 #define CONFIG_BOOTP_BOOTFILESIZE 462 463 /* Watchdog */ 464 #undef CONFIG_WATCHDOG /* watchdog disabled */ 465 466 /* 467 * Miscellaneous configurable options 468 */ 469 470 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 471 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 472 473 /* 474 * For booting Linux, the board info and command line data 475 * have to be in the first 256 MB of memory, since this is 476 * the maximum mapped by the Linux kernel during initialization. 477 */ 478 /* Initial Memory map for Linux*/ 479 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 480 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 481 482 #define CONFIG_SYS_HRCW_LOW (\ 483 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 484 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 485 HRCWL_CSB_TO_CLKIN_4X1 |\ 486 HRCWL_VCO_1X2 |\ 487 HRCWL_CORE_TO_CSB_2X1) 488 489 #ifdef CONFIG_SYS_LOWBOOT 490 #define CONFIG_SYS_HRCW_HIGH (\ 491 HRCWH_PCI_HOST |\ 492 HRCWH_32_BIT_PCI |\ 493 HRCWH_PCI1_ARBITER_ENABLE |\ 494 HRCWH_PCI2_ARBITER_ENABLE |\ 495 HRCWH_CORE_ENABLE |\ 496 HRCWH_FROM_0X00000100 |\ 497 HRCWH_BOOTSEQ_DISABLE |\ 498 HRCWH_SW_WATCHDOG_DISABLE |\ 499 HRCWH_ROM_LOC_LOCAL_16BIT |\ 500 HRCWH_TSEC1M_IN_GMII |\ 501 HRCWH_TSEC2M_IN_GMII) 502 #else 503 #define CONFIG_SYS_HRCW_HIGH (\ 504 HRCWH_PCI_HOST |\ 505 HRCWH_32_BIT_PCI |\ 506 HRCWH_PCI1_ARBITER_ENABLE |\ 507 HRCWH_PCI2_ARBITER_ENABLE |\ 508 HRCWH_CORE_ENABLE |\ 509 HRCWH_FROM_0XFFF00100 |\ 510 HRCWH_BOOTSEQ_DISABLE |\ 511 HRCWH_SW_WATCHDOG_DISABLE |\ 512 HRCWH_ROM_LOC_LOCAL_16BIT |\ 513 HRCWH_TSEC1M_IN_GMII |\ 514 HRCWH_TSEC2M_IN_GMII) 515 #endif 516 517 /* 518 * System performance 519 */ 520 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 521 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 522 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 523 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 524 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 525 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 526 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 527 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 528 529 /* 530 * System IO Config 531 */ 532 /* Needed for gigabit to work on TSEC 1 */ 533 #define CONFIG_SYS_SICRH SICRH_TSOBI1 534 /* USB DR as device + USB MPH as host */ 535 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 536 537 #define CONFIG_SYS_HID0_INIT 0x00000000 538 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 539 540 #define CONFIG_SYS_HID2 HID2_HBE 541 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 542 543 /* DDR */ 544 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 545 | BATL_PP_RW \ 546 | BATL_MEMCOHERENCE) 547 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 548 | BATU_BL_256M \ 549 | BATU_VS \ 550 | BATU_VP) 551 552 /* PCI */ 553 #ifdef CONFIG_PCI 554 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 555 | BATL_PP_RW \ 556 | BATL_MEMCOHERENCE) 557 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 558 | BATU_BL_256M \ 559 | BATU_VS \ 560 | BATU_VP) 561 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 562 | BATL_PP_RW \ 563 | BATL_CACHEINHIBIT \ 564 | BATL_GUARDEDSTORAGE) 565 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 566 | BATU_BL_256M \ 567 | BATU_VS \ 568 | BATU_VP) 569 #else 570 #define CONFIG_SYS_IBAT1L 0 571 #define CONFIG_SYS_IBAT1U 0 572 #define CONFIG_SYS_IBAT2L 0 573 #define CONFIG_SYS_IBAT2U 0 574 #endif 575 576 #ifdef CONFIG_MPC83XX_PCI2 577 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 578 | BATL_PP_RW \ 579 | BATL_MEMCOHERENCE) 580 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 581 | BATU_BL_256M \ 582 | BATU_VS \ 583 | BATU_VP) 584 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 585 | BATL_PP_RW \ 586 | BATL_CACHEINHIBIT \ 587 | BATL_GUARDEDSTORAGE) 588 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 589 | BATU_BL_256M \ 590 | BATU_VS \ 591 | BATU_VP) 592 #else 593 #define CONFIG_SYS_IBAT3L 0 594 #define CONFIG_SYS_IBAT3U 0 595 #define CONFIG_SYS_IBAT4L 0 596 #define CONFIG_SYS_IBAT4U 0 597 #endif 598 599 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 600 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 601 | BATL_PP_RW \ 602 | BATL_CACHEINHIBIT \ 603 | BATL_GUARDEDSTORAGE) 604 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 605 | BATU_BL_256M \ 606 | BATU_VS \ 607 | BATU_VP) 608 609 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 610 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 611 | BATL_PP_RW \ 612 | BATL_MEMCOHERENCE \ 613 | BATL_GUARDEDSTORAGE) 614 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 615 | BATU_BL_256M \ 616 | BATU_VS \ 617 | BATU_VP) 618 619 #define CONFIG_SYS_IBAT7L 0 620 #define CONFIG_SYS_IBAT7U 0 621 622 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 623 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 624 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 625 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 626 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 627 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 628 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 629 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 630 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 631 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 632 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 633 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 634 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 635 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 636 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 637 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 638 639 #if defined(CONFIG_CMD_KGDB) 640 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 641 #endif 642 643 /* 644 * Environment Configuration 645 */ 646 #define CONFIG_ENV_OVERWRITE 647 648 #define CONFIG_NETDEV "eth0" 649 650 /* Default path and filenames */ 651 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 652 #define CONFIG_BOOTFILE "uImage" 653 /* U-Boot image on TFTP server */ 654 #define CONFIG_UBOOTPATH "u-boot.bin" 655 656 #ifdef CONFIG_MPC8349ITX 657 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 658 #else 659 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 660 #endif 661 662 663 #define CONFIG_EXTRA_ENV_SETTINGS \ 664 "console=" __stringify(CONSOLE) "\0" \ 665 "netdev=" CONFIG_NETDEV "\0" \ 666 "uboot=" CONFIG_UBOOTPATH "\0" \ 667 "tftpflash=tftpboot $loadaddr $uboot; " \ 668 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 669 " +$filesize; " \ 670 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 671 " +$filesize; " \ 672 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 673 " $filesize; " \ 674 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 675 " +$filesize; " \ 676 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 677 " $filesize\0" \ 678 "fdtaddr=780000\0" \ 679 "fdtfile=" CONFIG_FDTFILE "\0" 680 681 #define CONFIG_NFSBOOTCOMMAND \ 682 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 683 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 684 " console=$console,$baudrate $othbootargs; " \ 685 "tftp $loadaddr $bootfile;" \ 686 "tftp $fdtaddr $fdtfile;" \ 687 "bootm $loadaddr - $fdtaddr" 688 689 #define CONFIG_RAMBOOTCOMMAND \ 690 "setenv bootargs root=/dev/ram rw" \ 691 " console=$console,$baudrate $othbootargs; " \ 692 "tftp $ramdiskaddr $ramdiskfile;" \ 693 "tftp $loadaddr $bootfile;" \ 694 "tftp $fdtaddr $fdtfile;" \ 695 "bootm $loadaddr $ramdiskaddr $fdtaddr" 696 697 #endif 698