1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 */ 5 6 /* 7 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 8 9 Memory map: 10 11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 18 0xF001_0000-0xF001_FFFF Local bus expansion slot 19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 22 23 I2C address list: 24 Align. Board 25 Bus Addr Part No. Description Length Location 26 ---------------------------------------------------------------- 27 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 28 29 I2C1 0x20 PCF8574 I2C Expander 0 U8 30 I2C1 0x21 PCF8574 I2C Expander 0 U10 31 I2C1 0x38 PCF8574A I2C Expander 0 U8 32 I2C1 0x39 PCF8574A I2C Expander 0 U10 33 I2C1 0x51 (DDR) DDR EEPROM 1 U1 34 I2C1 0x68 DS1339 RTC 1 U68 35 36 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 37 */ 38 39 #ifndef __CONFIG_H 40 #define __CONFIG_H 41 42 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 43 #define CONFIG_SYS_LOWBOOT 44 #endif 45 46 /* 47 * High Level Configuration Options 48 */ 49 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 50 #define CONFIG_MPC8349 /* MPC8349 specific */ 51 52 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 53 54 #define CONFIG_MISC_INIT_F 55 56 /* 57 * On-board devices 58 */ 59 60 #ifdef CONFIG_MPC8349ITX 61 /* The CF card interface on the back of the board */ 62 #define CONFIG_COMPACT_FLASH 63 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 64 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 65 #endif 66 67 #define CONFIG_RTC_DS1337 68 #define CONFIG_SYS_I2C 69 70 /* 71 * Device configurations 72 */ 73 74 /* I2C */ 75 #ifdef CONFIG_SYS_I2C 76 #define CONFIG_SYS_I2C_FSL 77 #define CONFIG_SYS_FSL_I2C_SPEED 400000 78 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 79 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 80 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 81 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 82 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 83 84 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 85 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 86 87 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 88 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 89 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 90 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 91 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 92 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 93 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 94 95 /* Don't probe these addresses: */ 96 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 97 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 98 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 99 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 100 /* Bit definitions for the 8574[A] I2C expander */ 101 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 102 #define I2C_8574_REVISION 0x03 103 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 104 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 105 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 106 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 107 108 #endif 109 110 /* Compact Flash */ 111 #ifdef CONFIG_COMPACT_FLASH 112 113 #define CONFIG_SYS_IDE_MAXBUS 1 114 #define CONFIG_SYS_IDE_MAXDEVICE 1 115 116 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 117 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 118 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 119 #define CONFIG_SYS_ATA_REG_OFFSET 0 120 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 121 #define CONFIG_SYS_ATA_STRIDE 2 122 123 /* If a CF card is not inserted, time out quickly */ 124 #define ATA_RESET_TIME 1 125 126 #endif 127 128 /* 129 * SATA 130 */ 131 #ifdef CONFIG_SATA_SIL3114 132 133 #define CONFIG_SYS_SATA_MAX_DEVICE 4 134 #define CONFIG_LBA48 135 136 #endif 137 138 #ifdef CONFIG_SYS_USB_HOST 139 /* 140 * Support USB 141 */ 142 #define CONFIG_USB_EHCI_FSL 143 144 /* Current USB implementation supports the only USB controller, 145 * so we have to choose between the MPH or the DR ones */ 146 #if 1 147 #define CONFIG_HAS_FSL_MPH_USB 148 #else 149 #define CONFIG_HAS_FSL_DR_USB 150 #endif 151 152 #endif 153 154 /* 155 * DDR Setup 156 */ 157 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 159 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 160 #define CONFIG_SYS_83XX_DDR_USES_CS0 161 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 162 #define CONFIG_SYS_MEMTEST_END 0x2000 163 164 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 165 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 166 167 #define CONFIG_VERY_BIG_RAM 168 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 169 170 #ifdef CONFIG_SYS_I2C 171 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 172 #endif 173 174 /* No SPD? Then manually set up DDR parameters */ 175 #ifndef CONFIG_SPD_EEPROM 176 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 177 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 178 | CSCONFIG_ROW_BIT_13 \ 179 | CSCONFIG_COL_BIT_10) 180 181 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 182 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 183 #endif 184 185 /* 186 *Flash on the Local Bus 187 */ 188 189 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 190 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 191 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 192 #define CONFIG_SYS_FLASH_EMPTY_INFO 193 /* 127 64KB sectors + 8 8KB sectors per device */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 135 195 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 198 199 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 200 boards, we say we have two, but don't display a message if we find only one. */ 201 #define CONFIG_SYS_FLASH_QUIET_TEST 202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 203 #define CONFIG_SYS_FLASH_BANKS_LIST \ 204 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 205 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 206 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 207 208 /* Vitesse 7385 */ 209 210 #ifdef CONFIG_VSC7385_ENET 211 212 #define CONFIG_TSEC2 213 214 /* The flash address and size of the VSC7385 firmware image */ 215 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 216 #define CONFIG_VSC7385_IMAGE_SIZE 8192 217 218 #endif 219 220 /* 221 * BRx, ORx, LBLAWBARx, and LBLAWARx 222 */ 223 224 /* Flash */ 225 226 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 227 | BR_PS_16 \ 228 | BR_MS_GPCM \ 229 | BR_V) 230 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 231 | OR_UPM_XAM \ 232 | OR_GPCM_CSNT \ 233 | OR_GPCM_ACS_DIV2 \ 234 | OR_GPCM_XACS \ 235 | OR_GPCM_SCY_15 \ 236 | OR_GPCM_TRLX_SET \ 237 | OR_GPCM_EHTR_SET \ 238 | OR_GPCM_EAD) 239 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 240 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 241 242 /* Vitesse 7385 */ 243 244 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 245 246 #ifdef CONFIG_VSC7385_ENET 247 248 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 249 | BR_PS_8 \ 250 | BR_MS_GPCM \ 251 | BR_V) 252 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 253 | OR_GPCM_CSNT \ 254 | OR_GPCM_XACS \ 255 | OR_GPCM_SCY_15 \ 256 | OR_GPCM_SETA \ 257 | OR_GPCM_TRLX_SET \ 258 | OR_GPCM_EHTR_SET \ 259 | OR_GPCM_EAD) 260 261 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 262 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 263 264 #endif 265 266 /* LED */ 267 268 #define CONFIG_SYS_LED_BASE 0xF9000000 269 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 270 | BR_PS_8 \ 271 | BR_MS_GPCM \ 272 | BR_V) 273 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 274 | OR_GPCM_CSNT \ 275 | OR_GPCM_ACS_DIV2 \ 276 | OR_GPCM_XACS \ 277 | OR_GPCM_SCY_9 \ 278 | OR_GPCM_TRLX_SET \ 279 | OR_GPCM_EHTR_SET \ 280 | OR_GPCM_EAD) 281 282 /* Compact Flash */ 283 284 #ifdef CONFIG_COMPACT_FLASH 285 286 #define CONFIG_SYS_CF_BASE 0xF0000000 287 288 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 289 | BR_PS_16 \ 290 | BR_MS_UPMA \ 291 | BR_V) 292 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 293 294 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 295 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 296 297 #endif 298 299 /* 300 * U-Boot memory configuration 301 */ 302 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 303 304 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 305 #define CONFIG_SYS_RAMBOOT 306 #else 307 #undef CONFIG_SYS_RAMBOOT 308 #endif 309 310 #define CONFIG_SYS_INIT_RAM_LOCK 311 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 312 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 313 314 #define CONFIG_SYS_GBL_DATA_OFFSET \ 315 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317 318 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 319 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 320 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 321 322 /* 323 * Local Bus LCRR and LBCR regs 324 * LCRR: DLL bypass, Clock divider is 4 325 * External Local Bus rate is 326 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 327 */ 328 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 329 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 330 #define CONFIG_SYS_LBC_LBCR 0x00000000 331 332 /* LB sdram refresh timer, about 6us */ 333 #define CONFIG_SYS_LBC_LSRT 0x32000000 334 /* LB refresh timer prescal, 266MHz/32*/ 335 #define CONFIG_SYS_LBC_MRTPR 0x20000000 336 337 /* 338 * Serial Port 339 */ 340 #define CONFIG_SYS_NS16550_SERIAL 341 #define CONFIG_SYS_NS16550_REG_SIZE 1 342 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 343 344 #define CONFIG_SYS_BAUDRATE_TABLE \ 345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 346 347 #define CONSOLE ttyS0 348 349 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 350 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 351 352 /* 353 * PCI 354 */ 355 #ifdef CONFIG_PCI 356 #define CONFIG_PCI_INDIRECT_BRIDGE 357 358 #define CONFIG_MPC83XX_PCI2 359 360 /* 361 * General PCI 362 * Addresses are mapped 1-1. 363 */ 364 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 365 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 366 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI1_MMIO_BASE \ 368 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 369 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 370 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 371 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 372 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 373 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 374 375 #ifdef CONFIG_MPC83XX_PCI2 376 #define CONFIG_SYS_PCI2_MEM_BASE \ 377 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 378 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 379 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 380 #define CONFIG_SYS_PCI2_MMIO_BASE \ 381 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 382 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 383 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 384 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 385 #define CONFIG_SYS_PCI2_IO_PHYS \ 386 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 387 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 388 #endif 389 390 #ifndef CONFIG_PCI_PNP 391 #define PCI_ENET0_IOADDR 0x00000000 392 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 393 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 394 #endif 395 396 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 397 398 #endif 399 400 #define CONFIG_PCI_66M 401 #ifdef CONFIG_PCI_66M 402 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 403 #else 404 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 405 #endif 406 407 /* TSEC */ 408 409 #ifdef CONFIG_TSEC_ENET 410 #define CONFIG_TSEC1 411 412 #ifdef CONFIG_TSEC1 413 #define CONFIG_HAS_ETH0 414 #define CONFIG_TSEC1_NAME "TSEC0" 415 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 416 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 417 #define TSEC1_PHYIDX 0 418 #define TSEC1_FLAGS TSEC_GIGABIT 419 #endif 420 421 #ifdef CONFIG_TSEC2 422 #define CONFIG_HAS_ETH1 423 #define CONFIG_TSEC2_NAME "TSEC1" 424 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 425 426 #define TSEC2_PHY_ADDR 4 427 #define TSEC2_PHYIDX 0 428 #define TSEC2_FLAGS TSEC_GIGABIT 429 #endif 430 431 #define CONFIG_ETHPRIME "Freescale TSEC" 432 433 #endif 434 435 /* 436 * Environment 437 */ 438 #define CONFIG_ENV_OVERWRITE 439 440 #ifndef CONFIG_SYS_RAMBOOT 441 #define CONFIG_ENV_ADDR \ 442 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 443 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 444 #define CONFIG_ENV_SIZE 0x2000 445 #else 446 #undef CONFIG_FLASH_CFI_DRIVER 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 448 #define CONFIG_ENV_SIZE 0x2000 449 #endif 450 451 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 452 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 453 454 /* 455 * BOOTP options 456 */ 457 #define CONFIG_BOOTP_BOOTFILESIZE 458 459 /* Watchdog */ 460 #undef CONFIG_WATCHDOG /* watchdog disabled */ 461 462 /* 463 * Miscellaneous configurable options 464 */ 465 466 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 467 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 468 469 /* 470 * For booting Linux, the board info and command line data 471 * have to be in the first 256 MB of memory, since this is 472 * the maximum mapped by the Linux kernel during initialization. 473 */ 474 /* Initial Memory map for Linux*/ 475 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 476 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 477 478 #define CONFIG_SYS_HRCW_LOW (\ 479 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 480 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 481 HRCWL_CSB_TO_CLKIN_4X1 |\ 482 HRCWL_VCO_1X2 |\ 483 HRCWL_CORE_TO_CSB_2X1) 484 485 #ifdef CONFIG_SYS_LOWBOOT 486 #define CONFIG_SYS_HRCW_HIGH (\ 487 HRCWH_PCI_HOST |\ 488 HRCWH_32_BIT_PCI |\ 489 HRCWH_PCI1_ARBITER_ENABLE |\ 490 HRCWH_PCI2_ARBITER_ENABLE |\ 491 HRCWH_CORE_ENABLE |\ 492 HRCWH_FROM_0X00000100 |\ 493 HRCWH_BOOTSEQ_DISABLE |\ 494 HRCWH_SW_WATCHDOG_DISABLE |\ 495 HRCWH_ROM_LOC_LOCAL_16BIT |\ 496 HRCWH_TSEC1M_IN_GMII |\ 497 HRCWH_TSEC2M_IN_GMII) 498 #else 499 #define CONFIG_SYS_HRCW_HIGH (\ 500 HRCWH_PCI_HOST |\ 501 HRCWH_32_BIT_PCI |\ 502 HRCWH_PCI1_ARBITER_ENABLE |\ 503 HRCWH_PCI2_ARBITER_ENABLE |\ 504 HRCWH_CORE_ENABLE |\ 505 HRCWH_FROM_0XFFF00100 |\ 506 HRCWH_BOOTSEQ_DISABLE |\ 507 HRCWH_SW_WATCHDOG_DISABLE |\ 508 HRCWH_ROM_LOC_LOCAL_16BIT |\ 509 HRCWH_TSEC1M_IN_GMII |\ 510 HRCWH_TSEC2M_IN_GMII) 511 #endif 512 513 /* 514 * System performance 515 */ 516 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 517 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 518 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 519 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 520 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 521 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 522 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 523 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 524 525 /* 526 * System IO Config 527 */ 528 /* Needed for gigabit to work on TSEC 1 */ 529 #define CONFIG_SYS_SICRH SICRH_TSOBI1 530 /* USB DR as device + USB MPH as host */ 531 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 532 533 #define CONFIG_SYS_HID0_INIT 0x00000000 534 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 535 536 #define CONFIG_SYS_HID2 HID2_HBE 537 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 538 539 /* DDR */ 540 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 541 | BATL_PP_RW \ 542 | BATL_MEMCOHERENCE) 543 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 544 | BATU_BL_256M \ 545 | BATU_VS \ 546 | BATU_VP) 547 548 /* PCI */ 549 #ifdef CONFIG_PCI 550 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 551 | BATL_PP_RW \ 552 | BATL_MEMCOHERENCE) 553 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 554 | BATU_BL_256M \ 555 | BATU_VS \ 556 | BATU_VP) 557 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 558 | BATL_PP_RW \ 559 | BATL_CACHEINHIBIT \ 560 | BATL_GUARDEDSTORAGE) 561 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 562 | BATU_BL_256M \ 563 | BATU_VS \ 564 | BATU_VP) 565 #else 566 #define CONFIG_SYS_IBAT1L 0 567 #define CONFIG_SYS_IBAT1U 0 568 #define CONFIG_SYS_IBAT2L 0 569 #define CONFIG_SYS_IBAT2U 0 570 #endif 571 572 #ifdef CONFIG_MPC83XX_PCI2 573 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 574 | BATL_PP_RW \ 575 | BATL_MEMCOHERENCE) 576 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 577 | BATU_BL_256M \ 578 | BATU_VS \ 579 | BATU_VP) 580 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 581 | BATL_PP_RW \ 582 | BATL_CACHEINHIBIT \ 583 | BATL_GUARDEDSTORAGE) 584 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 585 | BATU_BL_256M \ 586 | BATU_VS \ 587 | BATU_VP) 588 #else 589 #define CONFIG_SYS_IBAT3L 0 590 #define CONFIG_SYS_IBAT3U 0 591 #define CONFIG_SYS_IBAT4L 0 592 #define CONFIG_SYS_IBAT4U 0 593 #endif 594 595 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 596 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 597 | BATL_PP_RW \ 598 | BATL_CACHEINHIBIT \ 599 | BATL_GUARDEDSTORAGE) 600 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 601 | BATU_BL_256M \ 602 | BATU_VS \ 603 | BATU_VP) 604 605 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 606 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 607 | BATL_PP_RW \ 608 | BATL_MEMCOHERENCE \ 609 | BATL_GUARDEDSTORAGE) 610 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 611 | BATU_BL_256M \ 612 | BATU_VS \ 613 | BATU_VP) 614 615 #define CONFIG_SYS_IBAT7L 0 616 #define CONFIG_SYS_IBAT7U 0 617 618 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 619 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 620 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 621 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 622 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 623 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 624 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 625 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 626 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 627 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 628 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 629 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 630 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 631 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 632 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 633 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 634 635 #if defined(CONFIG_CMD_KGDB) 636 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 637 #endif 638 639 /* 640 * Environment Configuration 641 */ 642 #define CONFIG_ENV_OVERWRITE 643 644 #define CONFIG_NETDEV "eth0" 645 646 /* Default path and filenames */ 647 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 648 #define CONFIG_BOOTFILE "uImage" 649 /* U-Boot image on TFTP server */ 650 #define CONFIG_UBOOTPATH "u-boot.bin" 651 652 #ifdef CONFIG_MPC8349ITX 653 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 654 #else 655 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 656 #endif 657 658 659 #define CONFIG_EXTRA_ENV_SETTINGS \ 660 "console=" __stringify(CONSOLE) "\0" \ 661 "netdev=" CONFIG_NETDEV "\0" \ 662 "uboot=" CONFIG_UBOOTPATH "\0" \ 663 "tftpflash=tftpboot $loadaddr $uboot; " \ 664 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 665 " +$filesize; " \ 666 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 667 " +$filesize; " \ 668 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 669 " $filesize; " \ 670 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 671 " +$filesize; " \ 672 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 673 " $filesize\0" \ 674 "fdtaddr=780000\0" \ 675 "fdtfile=" CONFIG_FDTFILE "\0" 676 677 #define CONFIG_NFSBOOTCOMMAND \ 678 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 679 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 680 " console=$console,$baudrate $othbootargs; " \ 681 "tftp $loadaddr $bootfile;" \ 682 "tftp $fdtaddr $fdtfile;" \ 683 "bootm $loadaddr - $fdtaddr" 684 685 #define CONFIG_RAMBOOTCOMMAND \ 686 "setenv bootargs root=/dev/ram rw" \ 687 " console=$console,$baudrate $othbootargs; " \ 688 "tftp $ramdiskaddr $ramdiskfile;" \ 689 "tftp $loadaddr $bootfile;" \ 690 "tftp $fdtaddr $fdtfile;" \ 691 "bootm $loadaddr $ramdiskaddr $fdtaddr" 692 693 #endif 694