1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 9 10 Memory map: 11 12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 19 0xF001_0000-0xF001_FFFF Local bus expansion slot 20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 23 24 I2C address list: 25 Align. Board 26 Bus Addr Part No. Description Length Location 27 ---------------------------------------------------------------- 28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 29 30 I2C1 0x20 PCF8574 I2C Expander 0 U8 31 I2C1 0x21 PCF8574 I2C Expander 0 U10 32 I2C1 0x38 PCF8574A I2C Expander 0 U8 33 I2C1 0x39 PCF8574A I2C Expander 0 U10 34 I2C1 0x51 (DDR) DDR EEPROM 1 U1 35 I2C1 0x68 DS1339 RTC 1 U68 36 37 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 38 */ 39 40 #ifndef __CONFIG_H 41 #define __CONFIG_H 42 43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 44 #define CONFIG_SYS_LOWBOOT 45 #endif 46 47 /* 48 * High Level Configuration Options 49 */ 50 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 51 #define CONFIG_MPC8349 /* MPC8349 specific */ 52 53 #ifndef CONFIG_SYS_TEXT_BASE 54 #define CONFIG_SYS_TEXT_BASE 0xFEF00000 55 #endif 56 57 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 58 59 #define CONFIG_MISC_INIT_F 60 #define CONFIG_MISC_INIT_R 61 62 /* 63 * On-board devices 64 */ 65 66 #ifdef CONFIG_MPC8349ITX 67 /* The CF card interface on the back of the board */ 68 #define CONFIG_COMPACT_FLASH 69 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 70 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 71 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 72 #endif 73 74 #define CONFIG_PCI 75 #define CONFIG_RTC_DS1337 76 #define CONFIG_SYS_I2C 77 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 78 79 /* 80 * Device configurations 81 */ 82 83 /* I2C */ 84 #ifdef CONFIG_SYS_I2C 85 #define CONFIG_SYS_I2C_FSL 86 #define CONFIG_SYS_FSL_I2C_SPEED 400000 87 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 88 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 89 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 90 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 91 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 92 93 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 94 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 95 96 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 97 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 98 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 99 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 100 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 101 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 102 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 103 104 /* Don't probe these addresses: */ 105 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 106 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 107 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 108 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 109 /* Bit definitions for the 8574[A] I2C expander */ 110 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 111 #define I2C_8574_REVISION 0x03 112 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 113 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 114 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 115 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 116 117 #endif 118 119 /* Compact Flash */ 120 #ifdef CONFIG_COMPACT_FLASH 121 122 #define CONFIG_SYS_IDE_MAXBUS 1 123 #define CONFIG_SYS_IDE_MAXDEVICE 1 124 125 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 126 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 127 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 128 #define CONFIG_SYS_ATA_REG_OFFSET 0 129 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 130 #define CONFIG_SYS_ATA_STRIDE 2 131 132 /* If a CF card is not inserted, time out quickly */ 133 #define ATA_RESET_TIME 1 134 135 #endif 136 137 /* 138 * SATA 139 */ 140 #ifdef CONFIG_SATA_SIL3114 141 142 #define CONFIG_SYS_SATA_MAX_DEVICE 4 143 #define CONFIG_LIBATA 144 #define CONFIG_LBA48 145 146 #endif 147 148 #ifdef CONFIG_SYS_USB_HOST 149 /* 150 * Support USB 151 */ 152 #define CONFIG_CMD_USB 153 #define CONFIG_USB_STORAGE 154 #define CONFIG_USB_EHCI 155 #define CONFIG_USB_EHCI_FSL 156 157 /* Current USB implementation supports the only USB controller, 158 * so we have to choose between the MPH or the DR ones */ 159 #if 1 160 #define CONFIG_HAS_FSL_MPH_USB 161 #else 162 #define CONFIG_HAS_FSL_DR_USB 163 #endif 164 165 #endif 166 167 /* 168 * DDR Setup 169 */ 170 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 172 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 173 #define CONFIG_SYS_83XX_DDR_USES_CS0 174 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 175 #define CONFIG_SYS_MEMTEST_END 0x2000 176 177 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 178 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 179 180 #define CONFIG_VERY_BIG_RAM 181 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 182 183 #ifdef CONFIG_SYS_I2C 184 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 185 #endif 186 187 /* No SPD? Then manually set up DDR parameters */ 188 #ifndef CONFIG_SPD_EEPROM 189 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 190 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 191 | CSCONFIG_ROW_BIT_13 \ 192 | CSCONFIG_COL_BIT_10) 193 194 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 195 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 196 #endif 197 198 /* 199 *Flash on the Local Bus 200 */ 201 202 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 203 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 204 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 205 #define CONFIG_SYS_FLASH_EMPTY_INFO 206 /* 127 64KB sectors + 8 8KB sectors per device */ 207 #define CONFIG_SYS_MAX_FLASH_SECT 135 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 210 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 211 212 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 213 boards, we say we have two, but don't display a message if we find only one. */ 214 #define CONFIG_SYS_FLASH_QUIET_TEST 215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 216 #define CONFIG_SYS_FLASH_BANKS_LIST \ 217 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 218 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 219 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 220 221 /* Vitesse 7385 */ 222 223 #ifdef CONFIG_VSC7385_ENET 224 225 #define CONFIG_TSEC2 226 227 /* The flash address and size of the VSC7385 firmware image */ 228 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 229 #define CONFIG_VSC7385_IMAGE_SIZE 8192 230 231 #endif 232 233 /* 234 * BRx, ORx, LBLAWBARx, and LBLAWARx 235 */ 236 237 /* Flash */ 238 239 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 240 | BR_PS_16 \ 241 | BR_MS_GPCM \ 242 | BR_V) 243 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 244 | OR_UPM_XAM \ 245 | OR_GPCM_CSNT \ 246 | OR_GPCM_ACS_DIV2 \ 247 | OR_GPCM_XACS \ 248 | OR_GPCM_SCY_15 \ 249 | OR_GPCM_TRLX_SET \ 250 | OR_GPCM_EHTR_SET \ 251 | OR_GPCM_EAD) 252 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 253 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 254 255 /* Vitesse 7385 */ 256 257 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 258 259 #ifdef CONFIG_VSC7385_ENET 260 261 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 262 | BR_PS_8 \ 263 | BR_MS_GPCM \ 264 | BR_V) 265 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 266 | OR_GPCM_CSNT \ 267 | OR_GPCM_XACS \ 268 | OR_GPCM_SCY_15 \ 269 | OR_GPCM_SETA \ 270 | OR_GPCM_TRLX_SET \ 271 | OR_GPCM_EHTR_SET \ 272 | OR_GPCM_EAD) 273 274 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 275 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 276 277 #endif 278 279 /* LED */ 280 281 #define CONFIG_SYS_LED_BASE 0xF9000000 282 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 283 | BR_PS_8 \ 284 | BR_MS_GPCM \ 285 | BR_V) 286 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 287 | OR_GPCM_CSNT \ 288 | OR_GPCM_ACS_DIV2 \ 289 | OR_GPCM_XACS \ 290 | OR_GPCM_SCY_9 \ 291 | OR_GPCM_TRLX_SET \ 292 | OR_GPCM_EHTR_SET \ 293 | OR_GPCM_EAD) 294 295 /* Compact Flash */ 296 297 #ifdef CONFIG_COMPACT_FLASH 298 299 #define CONFIG_SYS_CF_BASE 0xF0000000 300 301 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 302 | BR_PS_16 \ 303 | BR_MS_UPMA \ 304 | BR_V) 305 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 306 307 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 308 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 309 310 #endif 311 312 /* 313 * U-Boot memory configuration 314 */ 315 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 316 317 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 318 #define CONFIG_SYS_RAMBOOT 319 #else 320 #undef CONFIG_SYS_RAMBOOT 321 #endif 322 323 #define CONFIG_SYS_INIT_RAM_LOCK 324 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 325 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 326 327 #define CONFIG_SYS_GBL_DATA_OFFSET \ 328 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 329 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 330 331 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 332 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 333 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 334 335 /* 336 * Local Bus LCRR and LBCR regs 337 * LCRR: DLL bypass, Clock divider is 4 338 * External Local Bus rate is 339 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 340 */ 341 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 342 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 343 #define CONFIG_SYS_LBC_LBCR 0x00000000 344 345 /* LB sdram refresh timer, about 6us */ 346 #define CONFIG_SYS_LBC_LSRT 0x32000000 347 /* LB refresh timer prescal, 266MHz/32*/ 348 #define CONFIG_SYS_LBC_MRTPR 0x20000000 349 350 /* 351 * Serial Port 352 */ 353 #define CONFIG_CONS_INDEX 1 354 #define CONFIG_SYS_NS16550 355 #define CONFIG_SYS_NS16550_SERIAL 356 #define CONFIG_SYS_NS16550_REG_SIZE 1 357 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 358 359 #define CONFIG_SYS_BAUDRATE_TABLE \ 360 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 361 362 #define CONFIG_CONSOLE ttyS0 363 #define CONFIG_BAUDRATE 115200 364 365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 367 368 /* pass open firmware flat tree */ 369 #define CONFIG_OF_LIBFDT 1 370 #define CONFIG_OF_BOARD_SETUP 1 371 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 372 373 /* 374 * PCI 375 */ 376 #ifdef CONFIG_PCI 377 #define CONFIG_PCI_INDIRECT_BRIDGE 378 379 #define CONFIG_MPC83XX_PCI2 380 381 /* 382 * General PCI 383 * Addresses are mapped 1-1. 384 */ 385 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 386 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 387 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 388 #define CONFIG_SYS_PCI1_MMIO_BASE \ 389 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 390 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 391 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 392 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 393 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 394 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 395 396 #ifdef CONFIG_MPC83XX_PCI2 397 #define CONFIG_SYS_PCI2_MEM_BASE \ 398 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 399 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 400 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 401 #define CONFIG_SYS_PCI2_MMIO_BASE \ 402 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 403 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 404 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 405 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 406 #define CONFIG_SYS_PCI2_IO_PHYS \ 407 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 408 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 409 #endif 410 411 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 412 413 #ifndef CONFIG_PCI_PNP 414 #define PCI_ENET0_IOADDR 0x00000000 415 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 416 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 417 #endif 418 419 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 420 421 #endif 422 423 #define CONFIG_PCI_66M 424 #ifdef CONFIG_PCI_66M 425 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 426 #else 427 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 428 #endif 429 430 /* TSEC */ 431 432 #ifdef CONFIG_TSEC_ENET 433 434 #define CONFIG_MII 435 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 436 437 #define CONFIG_TSEC1 438 439 #ifdef CONFIG_TSEC1 440 #define CONFIG_HAS_ETH0 441 #define CONFIG_TSEC1_NAME "TSEC0" 442 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 443 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 444 #define TSEC1_PHYIDX 0 445 #define TSEC1_FLAGS TSEC_GIGABIT 446 #endif 447 448 #ifdef CONFIG_TSEC2 449 #define CONFIG_HAS_ETH1 450 #define CONFIG_TSEC2_NAME "TSEC1" 451 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 452 453 #define TSEC2_PHY_ADDR 4 454 #define TSEC2_PHYIDX 0 455 #define TSEC2_FLAGS TSEC_GIGABIT 456 #endif 457 458 #define CONFIG_ETHPRIME "Freescale TSEC" 459 460 #endif 461 462 /* 463 * Environment 464 */ 465 #define CONFIG_ENV_OVERWRITE 466 467 #ifndef CONFIG_SYS_RAMBOOT 468 #define CONFIG_ENV_IS_IN_FLASH 469 #define CONFIG_ENV_ADDR \ 470 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 471 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 472 #define CONFIG_ENV_SIZE 0x2000 473 #else 474 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 475 #undef CONFIG_FLASH_CFI_DRIVER 476 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 477 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 478 #define CONFIG_ENV_SIZE 0x2000 479 #endif 480 481 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 482 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 483 484 /* 485 * BOOTP options 486 */ 487 #define CONFIG_BOOTP_BOOTFILESIZE 488 #define CONFIG_BOOTP_BOOTPATH 489 #define CONFIG_BOOTP_GATEWAY 490 #define CONFIG_BOOTP_HOSTNAME 491 492 493 /* 494 * Command line configuration. 495 */ 496 #include <config_cmd_default.h> 497 498 #define CONFIG_CMD_CACHE 499 #define CONFIG_CMD_DATE 500 #define CONFIG_CMD_IRQ 501 #define CONFIG_CMD_NET 502 #define CONFIG_CMD_PING 503 #define CONFIG_CMD_DHCP 504 #define CONFIG_CMD_SDRAM 505 506 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 507 || defined(CONFIG_USB_STORAGE) 508 #define CONFIG_DOS_PARTITION 509 #define CONFIG_CMD_FAT 510 #define CONFIG_SUPPORT_VFAT 511 #endif 512 513 #ifdef CONFIG_COMPACT_FLASH 514 #define CONFIG_CMD_IDE 515 #endif 516 517 #ifdef CONFIG_SATA_SIL3114 518 #define CONFIG_CMD_SATA 519 #endif 520 521 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 522 #define CONFIG_CMD_EXT2 523 #endif 524 525 #ifdef CONFIG_PCI 526 #define CONFIG_CMD_PCI 527 #endif 528 529 #ifdef CONFIG_SYS_I2C 530 #define CONFIG_CMD_I2C 531 #endif 532 533 /* Watchdog */ 534 #undef CONFIG_WATCHDOG /* watchdog disabled */ 535 536 /* 537 * Miscellaneous configurable options 538 */ 539 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 540 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 541 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 542 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 543 544 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 545 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 546 547 #ifdef CONFIG_MPC8349ITX 548 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 549 #else 550 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 551 #endif 552 553 #if defined(CONFIG_CMD_KGDB) 554 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 555 #else 556 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 557 #endif 558 559 /* Print Buffer Size */ 560 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 561 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 562 /* Boot Argument Buffer Size */ 563 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 564 565 /* 566 * For booting Linux, the board info and command line data 567 * have to be in the first 256 MB of memory, since this is 568 * the maximum mapped by the Linux kernel during initialization. 569 */ 570 /* Initial Memory map for Linux*/ 571 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 572 573 #define CONFIG_SYS_HRCW_LOW (\ 574 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 575 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 576 HRCWL_CSB_TO_CLKIN_4X1 |\ 577 HRCWL_VCO_1X2 |\ 578 HRCWL_CORE_TO_CSB_2X1) 579 580 #ifdef CONFIG_SYS_LOWBOOT 581 #define CONFIG_SYS_HRCW_HIGH (\ 582 HRCWH_PCI_HOST |\ 583 HRCWH_32_BIT_PCI |\ 584 HRCWH_PCI1_ARBITER_ENABLE |\ 585 HRCWH_PCI2_ARBITER_ENABLE |\ 586 HRCWH_CORE_ENABLE |\ 587 HRCWH_FROM_0X00000100 |\ 588 HRCWH_BOOTSEQ_DISABLE |\ 589 HRCWH_SW_WATCHDOG_DISABLE |\ 590 HRCWH_ROM_LOC_LOCAL_16BIT |\ 591 HRCWH_TSEC1M_IN_GMII |\ 592 HRCWH_TSEC2M_IN_GMII) 593 #else 594 #define CONFIG_SYS_HRCW_HIGH (\ 595 HRCWH_PCI_HOST |\ 596 HRCWH_32_BIT_PCI |\ 597 HRCWH_PCI1_ARBITER_ENABLE |\ 598 HRCWH_PCI2_ARBITER_ENABLE |\ 599 HRCWH_CORE_ENABLE |\ 600 HRCWH_FROM_0XFFF00100 |\ 601 HRCWH_BOOTSEQ_DISABLE |\ 602 HRCWH_SW_WATCHDOG_DISABLE |\ 603 HRCWH_ROM_LOC_LOCAL_16BIT |\ 604 HRCWH_TSEC1M_IN_GMII |\ 605 HRCWH_TSEC2M_IN_GMII) 606 #endif 607 608 /* 609 * System performance 610 */ 611 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 612 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 613 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 614 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 615 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 616 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 617 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 618 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 619 620 /* 621 * System IO Config 622 */ 623 /* Needed for gigabit to work on TSEC 1 */ 624 #define CONFIG_SYS_SICRH SICRH_TSOBI1 625 /* USB DR as device + USB MPH as host */ 626 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 627 628 #define CONFIG_SYS_HID0_INIT 0x00000000 629 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 630 631 #define CONFIG_SYS_HID2 HID2_HBE 632 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 633 634 /* DDR */ 635 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 636 | BATL_PP_RW \ 637 | BATL_MEMCOHERENCE) 638 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 639 | BATU_BL_256M \ 640 | BATU_VS \ 641 | BATU_VP) 642 643 /* PCI */ 644 #ifdef CONFIG_PCI 645 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 646 | BATL_PP_RW \ 647 | BATL_MEMCOHERENCE) 648 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 649 | BATU_BL_256M \ 650 | BATU_VS \ 651 | BATU_VP) 652 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 653 | BATL_PP_RW \ 654 | BATL_CACHEINHIBIT \ 655 | BATL_GUARDEDSTORAGE) 656 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 657 | BATU_BL_256M \ 658 | BATU_VS \ 659 | BATU_VP) 660 #else 661 #define CONFIG_SYS_IBAT1L 0 662 #define CONFIG_SYS_IBAT1U 0 663 #define CONFIG_SYS_IBAT2L 0 664 #define CONFIG_SYS_IBAT2U 0 665 #endif 666 667 #ifdef CONFIG_MPC83XX_PCI2 668 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 669 | BATL_PP_RW \ 670 | BATL_MEMCOHERENCE) 671 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 672 | BATU_BL_256M \ 673 | BATU_VS \ 674 | BATU_VP) 675 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 676 | BATL_PP_RW \ 677 | BATL_CACHEINHIBIT \ 678 | BATL_GUARDEDSTORAGE) 679 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 680 | BATU_BL_256M \ 681 | BATU_VS \ 682 | BATU_VP) 683 #else 684 #define CONFIG_SYS_IBAT3L 0 685 #define CONFIG_SYS_IBAT3U 0 686 #define CONFIG_SYS_IBAT4L 0 687 #define CONFIG_SYS_IBAT4U 0 688 #endif 689 690 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 691 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 692 | BATL_PP_RW \ 693 | BATL_CACHEINHIBIT \ 694 | BATL_GUARDEDSTORAGE) 695 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 696 | BATU_BL_256M \ 697 | BATU_VS \ 698 | BATU_VP) 699 700 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 701 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 702 | BATL_PP_RW \ 703 | BATL_MEMCOHERENCE \ 704 | BATL_GUARDEDSTORAGE) 705 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 706 | BATU_BL_256M \ 707 | BATU_VS \ 708 | BATU_VP) 709 710 #define CONFIG_SYS_IBAT7L 0 711 #define CONFIG_SYS_IBAT7U 0 712 713 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 714 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 715 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 716 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 717 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 718 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 719 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 720 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 721 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 722 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 723 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 724 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 725 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 726 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 727 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 728 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 729 730 #if defined(CONFIG_CMD_KGDB) 731 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 732 #endif 733 734 735 /* 736 * Environment Configuration 737 */ 738 #define CONFIG_ENV_OVERWRITE 739 740 #define CONFIG_NETDEV "eth0" 741 742 #ifdef CONFIG_MPC8349ITX 743 #define CONFIG_HOSTNAME "mpc8349emitx" 744 #else 745 #define CONFIG_HOSTNAME "mpc8349emitxgp" 746 #endif 747 748 /* Default path and filenames */ 749 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 750 #define CONFIG_BOOTFILE "uImage" 751 /* U-Boot image on TFTP server */ 752 #define CONFIG_UBOOTPATH "u-boot.bin" 753 754 #ifdef CONFIG_MPC8349ITX 755 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 756 #else 757 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 758 #endif 759 760 #define CONFIG_BOOTDELAY 6 761 762 #define CONFIG_BOOTARGS \ 763 "root=/dev/nfs rw" \ 764 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 765 " ip=" __stringify(CONFIG_IPADDR) ":" \ 766 __stringify(CONFIG_SERVERIP) ":" \ 767 __stringify(CONFIG_GATEWAYIP) ":" \ 768 __stringify(CONFIG_NETMASK) ":" \ 769 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 770 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 771 772 #define CONFIG_EXTRA_ENV_SETTINGS \ 773 "console=" __stringify(CONFIG_CONSOLE) "\0" \ 774 "netdev=" CONFIG_NETDEV "\0" \ 775 "uboot=" CONFIG_UBOOTPATH "\0" \ 776 "tftpflash=tftpboot $loadaddr $uboot; " \ 777 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 778 " +$filesize; " \ 779 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 780 " +$filesize; " \ 781 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 782 " $filesize; " \ 783 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 784 " +$filesize; " \ 785 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 786 " $filesize\0" \ 787 "fdtaddr=780000\0" \ 788 "fdtfile=" CONFIG_FDTFILE "\0" 789 790 #define CONFIG_NFSBOOTCOMMAND \ 791 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 792 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 793 " console=$console,$baudrate $othbootargs; " \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr - $fdtaddr" 797 798 #define CONFIG_RAMBOOTCOMMAND \ 799 "setenv bootargs root=/dev/ram rw" \ 800 " console=$console,$baudrate $othbootargs; " \ 801 "tftp $ramdiskaddr $ramdiskfile;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr $ramdiskaddr $fdtaddr" 805 806 #endif 807