1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 9 10 Memory map: 11 12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 19 0xF001_0000-0xF001_FFFF Local bus expansion slot 20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 23 24 I2C address list: 25 Align. Board 26 Bus Addr Part No. Description Length Location 27 ---------------------------------------------------------------- 28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 29 30 I2C1 0x20 PCF8574 I2C Expander 0 U8 31 I2C1 0x21 PCF8574 I2C Expander 0 U10 32 I2C1 0x38 PCF8574A I2C Expander 0 U8 33 I2C1 0x39 PCF8574A I2C Expander 0 U10 34 I2C1 0x51 (DDR) DDR EEPROM 1 U1 35 I2C1 0x68 DS1339 RTC 1 U68 36 37 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 38 */ 39 40 #ifndef __CONFIG_H 41 #define __CONFIG_H 42 43 #define CONFIG_DISPLAY_BOARDINFO 44 45 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 46 #define CONFIG_SYS_LOWBOOT 47 #endif 48 49 /* 50 * High Level Configuration Options 51 */ 52 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 53 #define CONFIG_MPC8349 /* MPC8349 specific */ 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xFEF00000 57 #endif 58 59 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 60 61 #define CONFIG_MISC_INIT_F 62 #define CONFIG_MISC_INIT_R 63 64 /* 65 * On-board devices 66 */ 67 68 #ifdef CONFIG_MPC8349ITX 69 /* The CF card interface on the back of the board */ 70 #define CONFIG_COMPACT_FLASH 71 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 72 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 73 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 74 #endif 75 76 #define CONFIG_PCI 77 #define CONFIG_RTC_DS1337 78 #define CONFIG_SYS_I2C 79 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 80 81 /* 82 * Device configurations 83 */ 84 85 /* I2C */ 86 #ifdef CONFIG_SYS_I2C 87 #define CONFIG_SYS_I2C_FSL 88 #define CONFIG_SYS_FSL_I2C_SPEED 400000 89 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 90 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 91 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 92 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 93 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 94 95 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 96 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 97 98 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 99 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 100 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 101 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 102 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 103 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 104 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 105 106 /* Don't probe these addresses: */ 107 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 108 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 109 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 110 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 111 /* Bit definitions for the 8574[A] I2C expander */ 112 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 113 #define I2C_8574_REVISION 0x03 114 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 115 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 116 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 117 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 118 119 #endif 120 121 /* Compact Flash */ 122 #ifdef CONFIG_COMPACT_FLASH 123 124 #define CONFIG_SYS_IDE_MAXBUS 1 125 #define CONFIG_SYS_IDE_MAXDEVICE 1 126 127 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 128 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 129 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 130 #define CONFIG_SYS_ATA_REG_OFFSET 0 131 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 132 #define CONFIG_SYS_ATA_STRIDE 2 133 134 /* If a CF card is not inserted, time out quickly */ 135 #define ATA_RESET_TIME 1 136 137 #endif 138 139 /* 140 * SATA 141 */ 142 #ifdef CONFIG_SATA_SIL3114 143 144 #define CONFIG_SYS_SATA_MAX_DEVICE 4 145 #define CONFIG_LIBATA 146 #define CONFIG_LBA48 147 148 #endif 149 150 #ifdef CONFIG_SYS_USB_HOST 151 /* 152 * Support USB 153 */ 154 #define CONFIG_CMD_USB 155 #define CONFIG_USB_STORAGE 156 #define CONFIG_USB_EHCI 157 #define CONFIG_USB_EHCI_FSL 158 159 /* Current USB implementation supports the only USB controller, 160 * so we have to choose between the MPH or the DR ones */ 161 #if 1 162 #define CONFIG_HAS_FSL_MPH_USB 163 #else 164 #define CONFIG_HAS_FSL_DR_USB 165 #endif 166 167 #endif 168 169 /* 170 * DDR Setup 171 */ 172 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 174 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 175 #define CONFIG_SYS_83XX_DDR_USES_CS0 176 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 177 #define CONFIG_SYS_MEMTEST_END 0x2000 178 179 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 180 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 181 182 #define CONFIG_VERY_BIG_RAM 183 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 184 185 #ifdef CONFIG_SYS_I2C 186 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 187 #endif 188 189 /* No SPD? Then manually set up DDR parameters */ 190 #ifndef CONFIG_SPD_EEPROM 191 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 192 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 193 | CSCONFIG_ROW_BIT_13 \ 194 | CSCONFIG_COL_BIT_10) 195 196 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 197 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 198 #endif 199 200 /* 201 *Flash on the Local Bus 202 */ 203 204 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 205 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 206 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 207 #define CONFIG_SYS_FLASH_EMPTY_INFO 208 /* 127 64KB sectors + 8 8KB sectors per device */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 135 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 212 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 213 214 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 215 boards, we say we have two, but don't display a message if we find only one. */ 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 218 #define CONFIG_SYS_FLASH_BANKS_LIST \ 219 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 220 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 221 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 222 223 /* Vitesse 7385 */ 224 225 #ifdef CONFIG_VSC7385_ENET 226 227 #define CONFIG_TSEC2 228 229 /* The flash address and size of the VSC7385 firmware image */ 230 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 231 #define CONFIG_VSC7385_IMAGE_SIZE 8192 232 233 #endif 234 235 /* 236 * BRx, ORx, LBLAWBARx, and LBLAWARx 237 */ 238 239 /* Flash */ 240 241 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 242 | BR_PS_16 \ 243 | BR_MS_GPCM \ 244 | BR_V) 245 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 246 | OR_UPM_XAM \ 247 | OR_GPCM_CSNT \ 248 | OR_GPCM_ACS_DIV2 \ 249 | OR_GPCM_XACS \ 250 | OR_GPCM_SCY_15 \ 251 | OR_GPCM_TRLX_SET \ 252 | OR_GPCM_EHTR_SET \ 253 | OR_GPCM_EAD) 254 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 255 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 256 257 /* Vitesse 7385 */ 258 259 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 260 261 #ifdef CONFIG_VSC7385_ENET 262 263 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 264 | BR_PS_8 \ 265 | BR_MS_GPCM \ 266 | BR_V) 267 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 268 | OR_GPCM_CSNT \ 269 | OR_GPCM_XACS \ 270 | OR_GPCM_SCY_15 \ 271 | OR_GPCM_SETA \ 272 | OR_GPCM_TRLX_SET \ 273 | OR_GPCM_EHTR_SET \ 274 | OR_GPCM_EAD) 275 276 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 277 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 278 279 #endif 280 281 /* LED */ 282 283 #define CONFIG_SYS_LED_BASE 0xF9000000 284 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 285 | BR_PS_8 \ 286 | BR_MS_GPCM \ 287 | BR_V) 288 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 289 | OR_GPCM_CSNT \ 290 | OR_GPCM_ACS_DIV2 \ 291 | OR_GPCM_XACS \ 292 | OR_GPCM_SCY_9 \ 293 | OR_GPCM_TRLX_SET \ 294 | OR_GPCM_EHTR_SET \ 295 | OR_GPCM_EAD) 296 297 /* Compact Flash */ 298 299 #ifdef CONFIG_COMPACT_FLASH 300 301 #define CONFIG_SYS_CF_BASE 0xF0000000 302 303 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 304 | BR_PS_16 \ 305 | BR_MS_UPMA \ 306 | BR_V) 307 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 308 309 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 310 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 311 312 #endif 313 314 /* 315 * U-Boot memory configuration 316 */ 317 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 318 319 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 320 #define CONFIG_SYS_RAMBOOT 321 #else 322 #undef CONFIG_SYS_RAMBOOT 323 #endif 324 325 #define CONFIG_SYS_INIT_RAM_LOCK 326 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 327 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 328 329 #define CONFIG_SYS_GBL_DATA_OFFSET \ 330 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 331 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 332 333 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 334 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 335 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 336 337 /* 338 * Local Bus LCRR and LBCR regs 339 * LCRR: DLL bypass, Clock divider is 4 340 * External Local Bus rate is 341 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 342 */ 343 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 344 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 345 #define CONFIG_SYS_LBC_LBCR 0x00000000 346 347 /* LB sdram refresh timer, about 6us */ 348 #define CONFIG_SYS_LBC_LSRT 0x32000000 349 /* LB refresh timer prescal, 266MHz/32*/ 350 #define CONFIG_SYS_LBC_MRTPR 0x20000000 351 352 /* 353 * Serial Port 354 */ 355 #define CONFIG_CONS_INDEX 1 356 #define CONFIG_SYS_NS16550 357 #define CONFIG_SYS_NS16550_SERIAL 358 #define CONFIG_SYS_NS16550_REG_SIZE 1 359 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 360 361 #define CONFIG_SYS_BAUDRATE_TABLE \ 362 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 363 364 #define CONFIG_CONSOLE ttyS0 365 #define CONFIG_BAUDRATE 115200 366 367 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 368 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 369 370 /* pass open firmware flat tree */ 371 #define CONFIG_OF_LIBFDT 1 372 #define CONFIG_OF_BOARD_SETUP 1 373 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 374 375 /* 376 * PCI 377 */ 378 #ifdef CONFIG_PCI 379 #define CONFIG_PCI_INDIRECT_BRIDGE 380 381 #define CONFIG_MPC83XX_PCI2 382 383 /* 384 * General PCI 385 * Addresses are mapped 1-1. 386 */ 387 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 388 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 389 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 390 #define CONFIG_SYS_PCI1_MMIO_BASE \ 391 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 392 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 393 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 394 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 395 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 396 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 397 398 #ifdef CONFIG_MPC83XX_PCI2 399 #define CONFIG_SYS_PCI2_MEM_BASE \ 400 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 401 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 402 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 403 #define CONFIG_SYS_PCI2_MMIO_BASE \ 404 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 405 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 406 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 407 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 408 #define CONFIG_SYS_PCI2_IO_PHYS \ 409 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 410 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 411 #endif 412 413 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 414 415 #ifndef CONFIG_PCI_PNP 416 #define PCI_ENET0_IOADDR 0x00000000 417 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 418 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 419 #endif 420 421 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 422 423 #endif 424 425 #define CONFIG_PCI_66M 426 #ifdef CONFIG_PCI_66M 427 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 428 #else 429 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 430 #endif 431 432 /* TSEC */ 433 434 #ifdef CONFIG_TSEC_ENET 435 436 #define CONFIG_MII 437 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 438 439 #define CONFIG_TSEC1 440 441 #ifdef CONFIG_TSEC1 442 #define CONFIG_HAS_ETH0 443 #define CONFIG_TSEC1_NAME "TSEC0" 444 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 445 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 446 #define TSEC1_PHYIDX 0 447 #define TSEC1_FLAGS TSEC_GIGABIT 448 #endif 449 450 #ifdef CONFIG_TSEC2 451 #define CONFIG_HAS_ETH1 452 #define CONFIG_TSEC2_NAME "TSEC1" 453 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 454 455 #define TSEC2_PHY_ADDR 4 456 #define TSEC2_PHYIDX 0 457 #define TSEC2_FLAGS TSEC_GIGABIT 458 #endif 459 460 #define CONFIG_ETHPRIME "Freescale TSEC" 461 462 #endif 463 464 /* 465 * Environment 466 */ 467 #define CONFIG_ENV_OVERWRITE 468 469 #ifndef CONFIG_SYS_RAMBOOT 470 #define CONFIG_ENV_IS_IN_FLASH 471 #define CONFIG_ENV_ADDR \ 472 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 473 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 474 #define CONFIG_ENV_SIZE 0x2000 475 #else 476 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 477 #undef CONFIG_FLASH_CFI_DRIVER 478 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 479 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 480 #define CONFIG_ENV_SIZE 0x2000 481 #endif 482 483 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 484 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 485 486 /* 487 * BOOTP options 488 */ 489 #define CONFIG_BOOTP_BOOTFILESIZE 490 #define CONFIG_BOOTP_BOOTPATH 491 #define CONFIG_BOOTP_GATEWAY 492 #define CONFIG_BOOTP_HOSTNAME 493 494 495 /* 496 * Command line configuration. 497 */ 498 #define CONFIG_CMD_CACHE 499 #define CONFIG_CMD_DATE 500 #define CONFIG_CMD_IRQ 501 #define CONFIG_CMD_PING 502 #define CONFIG_CMD_DHCP 503 #define CONFIG_CMD_SDRAM 504 505 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 506 || defined(CONFIG_USB_STORAGE) 507 #define CONFIG_DOS_PARTITION 508 #define CONFIG_CMD_FAT 509 #define CONFIG_SUPPORT_VFAT 510 #endif 511 512 #ifdef CONFIG_COMPACT_FLASH 513 #define CONFIG_CMD_IDE 514 #endif 515 516 #ifdef CONFIG_SATA_SIL3114 517 #define CONFIG_CMD_SATA 518 #endif 519 520 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 521 #define CONFIG_CMD_EXT2 522 #endif 523 524 #ifdef CONFIG_PCI 525 #define CONFIG_CMD_PCI 526 #endif 527 528 #ifdef CONFIG_SYS_I2C 529 #define CONFIG_CMD_I2C 530 #endif 531 532 /* Watchdog */ 533 #undef CONFIG_WATCHDOG /* watchdog disabled */ 534 535 /* 536 * Miscellaneous configurable options 537 */ 538 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 539 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 540 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 541 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 542 543 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 544 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 545 546 #if defined(CONFIG_CMD_KGDB) 547 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 548 #else 549 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 550 #endif 551 552 /* Print Buffer Size */ 553 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 554 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 555 /* Boot Argument Buffer Size */ 556 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 557 558 /* 559 * For booting Linux, the board info and command line data 560 * have to be in the first 256 MB of memory, since this is 561 * the maximum mapped by the Linux kernel during initialization. 562 */ 563 /* Initial Memory map for Linux*/ 564 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 565 566 #define CONFIG_SYS_HRCW_LOW (\ 567 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 568 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 569 HRCWL_CSB_TO_CLKIN_4X1 |\ 570 HRCWL_VCO_1X2 |\ 571 HRCWL_CORE_TO_CSB_2X1) 572 573 #ifdef CONFIG_SYS_LOWBOOT 574 #define CONFIG_SYS_HRCW_HIGH (\ 575 HRCWH_PCI_HOST |\ 576 HRCWH_32_BIT_PCI |\ 577 HRCWH_PCI1_ARBITER_ENABLE |\ 578 HRCWH_PCI2_ARBITER_ENABLE |\ 579 HRCWH_CORE_ENABLE |\ 580 HRCWH_FROM_0X00000100 |\ 581 HRCWH_BOOTSEQ_DISABLE |\ 582 HRCWH_SW_WATCHDOG_DISABLE |\ 583 HRCWH_ROM_LOC_LOCAL_16BIT |\ 584 HRCWH_TSEC1M_IN_GMII |\ 585 HRCWH_TSEC2M_IN_GMII) 586 #else 587 #define CONFIG_SYS_HRCW_HIGH (\ 588 HRCWH_PCI_HOST |\ 589 HRCWH_32_BIT_PCI |\ 590 HRCWH_PCI1_ARBITER_ENABLE |\ 591 HRCWH_PCI2_ARBITER_ENABLE |\ 592 HRCWH_CORE_ENABLE |\ 593 HRCWH_FROM_0XFFF00100 |\ 594 HRCWH_BOOTSEQ_DISABLE |\ 595 HRCWH_SW_WATCHDOG_DISABLE |\ 596 HRCWH_ROM_LOC_LOCAL_16BIT |\ 597 HRCWH_TSEC1M_IN_GMII |\ 598 HRCWH_TSEC2M_IN_GMII) 599 #endif 600 601 /* 602 * System performance 603 */ 604 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 605 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 606 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 607 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 608 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 609 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 610 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 611 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 612 613 /* 614 * System IO Config 615 */ 616 /* Needed for gigabit to work on TSEC 1 */ 617 #define CONFIG_SYS_SICRH SICRH_TSOBI1 618 /* USB DR as device + USB MPH as host */ 619 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 620 621 #define CONFIG_SYS_HID0_INIT 0x00000000 622 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 623 624 #define CONFIG_SYS_HID2 HID2_HBE 625 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 626 627 /* DDR */ 628 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 629 | BATL_PP_RW \ 630 | BATL_MEMCOHERENCE) 631 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 632 | BATU_BL_256M \ 633 | BATU_VS \ 634 | BATU_VP) 635 636 /* PCI */ 637 #ifdef CONFIG_PCI 638 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 639 | BATL_PP_RW \ 640 | BATL_MEMCOHERENCE) 641 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 642 | BATU_BL_256M \ 643 | BATU_VS \ 644 | BATU_VP) 645 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 646 | BATL_PP_RW \ 647 | BATL_CACHEINHIBIT \ 648 | BATL_GUARDEDSTORAGE) 649 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 650 | BATU_BL_256M \ 651 | BATU_VS \ 652 | BATU_VP) 653 #else 654 #define CONFIG_SYS_IBAT1L 0 655 #define CONFIG_SYS_IBAT1U 0 656 #define CONFIG_SYS_IBAT2L 0 657 #define CONFIG_SYS_IBAT2U 0 658 #endif 659 660 #ifdef CONFIG_MPC83XX_PCI2 661 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 662 | BATL_PP_RW \ 663 | BATL_MEMCOHERENCE) 664 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 665 | BATU_BL_256M \ 666 | BATU_VS \ 667 | BATU_VP) 668 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 669 | BATL_PP_RW \ 670 | BATL_CACHEINHIBIT \ 671 | BATL_GUARDEDSTORAGE) 672 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 673 | BATU_BL_256M \ 674 | BATU_VS \ 675 | BATU_VP) 676 #else 677 #define CONFIG_SYS_IBAT3L 0 678 #define CONFIG_SYS_IBAT3U 0 679 #define CONFIG_SYS_IBAT4L 0 680 #define CONFIG_SYS_IBAT4U 0 681 #endif 682 683 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 684 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 685 | BATL_PP_RW \ 686 | BATL_CACHEINHIBIT \ 687 | BATL_GUARDEDSTORAGE) 688 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 689 | BATU_BL_256M \ 690 | BATU_VS \ 691 | BATU_VP) 692 693 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 694 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 695 | BATL_PP_RW \ 696 | BATL_MEMCOHERENCE \ 697 | BATL_GUARDEDSTORAGE) 698 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 699 | BATU_BL_256M \ 700 | BATU_VS \ 701 | BATU_VP) 702 703 #define CONFIG_SYS_IBAT7L 0 704 #define CONFIG_SYS_IBAT7U 0 705 706 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 707 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 708 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 709 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 710 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 711 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 712 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 713 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 714 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 715 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 716 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 717 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 718 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 719 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 720 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 721 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 722 723 #if defined(CONFIG_CMD_KGDB) 724 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 725 #endif 726 727 728 /* 729 * Environment Configuration 730 */ 731 #define CONFIG_ENV_OVERWRITE 732 733 #define CONFIG_NETDEV "eth0" 734 735 #ifdef CONFIG_MPC8349ITX 736 #define CONFIG_HOSTNAME "mpc8349emitx" 737 #else 738 #define CONFIG_HOSTNAME "mpc8349emitxgp" 739 #endif 740 741 /* Default path and filenames */ 742 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 743 #define CONFIG_BOOTFILE "uImage" 744 /* U-Boot image on TFTP server */ 745 #define CONFIG_UBOOTPATH "u-boot.bin" 746 747 #ifdef CONFIG_MPC8349ITX 748 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 749 #else 750 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 751 #endif 752 753 #define CONFIG_BOOTDELAY 6 754 755 #define CONFIG_BOOTARGS \ 756 "root=/dev/nfs rw" \ 757 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 758 " ip=" __stringify(CONFIG_IPADDR) ":" \ 759 __stringify(CONFIG_SERVERIP) ":" \ 760 __stringify(CONFIG_GATEWAYIP) ":" \ 761 __stringify(CONFIG_NETMASK) ":" \ 762 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 763 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 764 765 #define CONFIG_EXTRA_ENV_SETTINGS \ 766 "console=" __stringify(CONFIG_CONSOLE) "\0" \ 767 "netdev=" CONFIG_NETDEV "\0" \ 768 "uboot=" CONFIG_UBOOTPATH "\0" \ 769 "tftpflash=tftpboot $loadaddr $uboot; " \ 770 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 771 " +$filesize; " \ 772 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 773 " +$filesize; " \ 774 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 775 " $filesize; " \ 776 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 777 " +$filesize; " \ 778 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 779 " $filesize\0" \ 780 "fdtaddr=780000\0" \ 781 "fdtfile=" CONFIG_FDTFILE "\0" 782 783 #define CONFIG_NFSBOOTCOMMAND \ 784 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 785 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 786 " console=$console,$baudrate $othbootargs; " \ 787 "tftp $loadaddr $bootfile;" \ 788 "tftp $fdtaddr $fdtfile;" \ 789 "bootm $loadaddr - $fdtaddr" 790 791 #define CONFIG_RAMBOOTCOMMAND \ 792 "setenv bootargs root=/dev/ram rw" \ 793 " console=$console,$baudrate $othbootargs; " \ 794 "tftp $ramdiskaddr $ramdiskfile;" \ 795 "tftp $loadaddr $bootfile;" \ 796 "tftp $fdtaddr $fdtfile;" \ 797 "bootm $loadaddr $ramdiskaddr $fdtaddr" 798 799 #endif 800