1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #if (TEXT_BASE == 0xFE000000) 60 #define CFG_LOWBOOT 61 #endif 62 63 /* 64 * High Level Configuration Options 65 */ 66 #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ 67 #define CONFIG_MPC8349 /* MPC8349 specific */ 68 69 #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ 70 71 72 /* On-board devices */ 73 74 #ifdef CONFIG_MPC8349ITX 75 #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 76 #define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ 77 #endif 78 79 #define CONFIG_PCI 80 #define CONFIG_RTC_DS1337 81 #define CONFIG_HARD_I2C 82 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 83 84 /* 85 * Device configurations 86 */ 87 88 /* I2C */ 89 #ifdef CONFIG_HARD_I2C 90 91 #define CONFIG_MISC_INIT_F 92 #define CONFIG_MISC_INIT_R 93 94 #define CONFIG_FSL_I2C 95 #define CONFIG_I2C_MULTI_BUS 96 #define CONFIG_I2C_CMD_TREE 97 #define CFG_I2C_OFFSET 0x3000 98 #define CFG_I2C2_OFFSET 0x3100 99 #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 100 101 #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 102 #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 103 #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 104 #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 105 #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 106 #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 107 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 108 109 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 110 #define CFG_I2C_SLAVE 0x7F 111 112 /* Don't probe these addresses: */ 113 #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ 114 {1, CFG_I2C_8574_ADDR2}, \ 115 {1, CFG_I2C_8574A_ADDR1}, \ 116 {1, CFG_I2C_8574A_ADDR2}} 117 /* Bit definitions for the 8574[A] I2C expander */ 118 #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 119 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 120 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 121 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 122 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 123 124 #undef CONFIG_SOFT_I2C 125 126 #endif 127 128 /* Compact Flash */ 129 #ifdef CONFIG_COMPACT_FLASH 130 131 #define CFG_IDE_MAXBUS 1 132 #define CFG_IDE_MAXDEVICE 1 133 134 #define CFG_ATA_IDE0_OFFSET 0x0000 135 #define CFG_ATA_BASE_ADDR CFG_CF_BASE 136 #define CFG_ATA_DATA_OFFSET 0x0000 137 #define CFG_ATA_REG_OFFSET 0 138 #define CFG_ATA_ALT_OFFSET 0x0200 139 #define CFG_ATA_STRIDE 2 140 141 #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 142 143 #define CONFIG_DOS_PARTITION 144 145 #endif 146 147 /* 148 * DDR Setup 149 */ 150 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ 151 #define CFG_SDRAM_BASE CFG_DDR_BASE 152 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE 153 #define CFG_83XX_DDR_USES_CS0 154 #define CFG_MEMTEST_START 0x1000 /* memtest region */ 155 #define CFG_MEMTEST_END 0x2000 156 157 #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 158 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 159 160 #ifdef CONFIG_HARD_I2C 161 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 162 #endif 163 164 #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 165 #define CFG_DDR_SIZE 256 /* Mb */ 166 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 167 168 #define CFG_DDR_TIMING_1 0x26242321 169 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 170 #endif 171 172 /* 173 *Flash on the Local Bus 174 */ 175 176 #define CFG_FLASH_CFI /* use the Common Flash Interface */ 177 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ 178 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ 179 #define CFG_FLASH_EMPTY_INFO 180 #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 181 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 182 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 183 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 184 185 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 186 boards, we say we have two, but don't display a message if we find only one. */ 187 #define CFG_FLASH_QUIET_TEST 188 #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 189 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} 190 #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ 191 #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 192 193 /* 194 * BRx, ORx, LBLAWBARx, and LBLAWARx 195 */ 196 197 /* Flash */ 198 199 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) 200 #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 201 OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 202 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 203 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE 204 #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) 205 206 /* Vitesse 7385 */ 207 208 #ifdef CONFIG_VSC7385 209 210 #define CFG_VSC7385_BASE 0xF8000000 211 212 #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) 213 #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 214 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 215 OR_GPCM_EHTR | OR_GPCM_EAD) 216 217 #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE 218 #define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 219 220 #endif 221 222 /* LED */ 223 224 #define CFG_LED_BASE 0xF9000000 225 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) 226 #define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ 227 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 228 OR_GPCM_EHTR | OR_GPCM_EAD) 229 230 /* Compact Flash */ 231 232 #ifdef CONFIG_COMPACT_FLASH 233 234 #define CFG_CF_BASE 0xF0000000 235 236 #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 237 #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 238 239 #define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE 240 #define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 241 242 #endif 243 244 /* 245 * U-Boot memory configuration 246 */ 247 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 248 249 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) 250 #define CFG_RAMBOOT 251 #else 252 #undef CFG_RAMBOOT 253 #endif 254 255 #define CONFIG_L1_INIT_RAM 256 #define CFG_INIT_RAM_LOCK 257 #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 258 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 259 260 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 261 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 262 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 263 264 /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ 265 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 266 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 267 268 /* 269 * Local Bus LCRR and LBCR regs 270 * LCRR: DLL bypass, Clock divider is 4 271 * External Local Bus rate is 272 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 273 */ 274 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 275 #define CFG_LBC_LBCR 0x00000000 276 277 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 278 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 279 280 /* 281 * Serial Port 282 */ 283 #define CONFIG_CONS_INDEX 1 284 #undef CONFIG_SERIAL_SOFTWARE_FIFO 285 #define CFG_NS16550 286 #define CFG_NS16550_SERIAL 287 #define CFG_NS16550_REG_SIZE 1 288 #define CFG_NS16550_CLK get_bus_freq(0) 289 290 #define CFG_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 292 293 #define CONFIG_CONSOLE ttyS0 294 #define CONFIG_BAUDRATE 115200 295 296 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) 297 #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) 298 299 /* pass open firmware flat tree */ 300 #define CONFIG_OF_LIBFDT 1 301 #define CONFIG_OF_BOARD_SETUP 1 302 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 303 304 /* 305 * PCI 306 */ 307 #ifdef CONFIG_PCI 308 309 #define CONFIG_MPC83XX_PCI2 310 311 /* 312 * General PCI 313 * Addresses are mapped 1-1. 314 */ 315 #define CFG_PCI1_MEM_BASE 0x80000000 316 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE 317 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ 318 #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) 319 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE 320 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 321 #define CFG_PCI1_IO_BASE 0x00000000 322 #define CFG_PCI1_IO_PHYS 0xE2000000 323 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ 324 325 #ifdef CONFIG_MPC83XX_PCI2 326 #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) 327 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE 328 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ 329 #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) 330 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE 331 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 332 #define CFG_PCI2_IO_BASE 0x00000000 333 #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) 334 #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ 335 #endif 336 337 #define _IO_BASE 0x00000000 /* points to PCI I/O space */ 338 339 #define CONFIG_NET_MULTI 340 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 341 342 #ifdef CONFIG_RTL8139 343 /* This macro is used by RTL8139 but not defined in PPC architecture */ 344 #define KSEG1ADDR(x) (x) 345 #endif 346 347 #ifndef CONFIG_PCI_PNP 348 #define PCI_ENET0_IOADDR 0x00000000 349 #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE 350 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 351 #endif 352 353 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 354 355 #endif 356 357 #define PCI_66M 358 #ifdef PCI_66M 359 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 360 #else 361 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 362 #endif 363 364 /* TSEC */ 365 366 #ifdef CONFIG_TSEC_ENET 367 368 #define CONFIG_NET_MULTI 369 #define CONFIG_MII 370 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 371 372 #define CONFIG_TSEC1 373 374 #ifdef CONFIG_TSEC1 375 #define CONFIG_HAS_ETH0 376 #define CONFIG_TSEC1_NAME "TSEC0" 377 #define CFG_TSEC1_OFFSET 0x24000 378 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 379 #define TSEC1_PHYIDX 0 380 #define TSEC1_FLAGS TSEC_GIGABIT 381 #endif 382 383 #ifdef CONFIG_TSEC2 384 #define CONFIG_HAS_ETH1 385 #define CONFIG_TSEC2_NAME "TSEC1" 386 #define CFG_TSEC2_OFFSET 0x25000 387 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ 388 #define TSEC2_PHY_ADDR 4 389 #define TSEC2_PHYIDX 0 390 #define TSEC2_FLAGS TSEC_GIGABIT 391 #endif 392 393 #define CONFIG_ETHPRIME "Freescale TSEC" 394 395 #endif 396 397 /* 398 * Environment 399 */ 400 #define CONFIG_ENV_OVERWRITE 401 402 #ifndef CFG_RAMBOOT 403 #define CFG_ENV_IS_IN_FLASH 404 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) 405 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 406 #define CFG_ENV_SIZE 0x2000 407 #else 408 #define CFG_NO_FLASH /* Flash is not usable now */ 409 #undef CFG_FLASH_CFI_DRIVER 410 #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ 411 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) 412 #define CFG_ENV_SIZE 0x2000 413 #endif 414 415 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 416 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ 417 418 /* 419 * BOOTP options 420 */ 421 #define CONFIG_BOOTP_BOOTFILESIZE 422 #define CONFIG_BOOTP_BOOTPATH 423 #define CONFIG_BOOTP_GATEWAY 424 #define CONFIG_BOOTP_HOSTNAME 425 426 427 /* 428 * Command line configuration. 429 */ 430 #include <config_cmd_default.h> 431 432 #define CONFIG_CMD_CACHE 433 #define CONFIG_CMD_DATE 434 #define CONFIG_CMD_IRQ 435 #define CONFIG_CMD_NET 436 #define CONFIG_CMD_PING 437 #define CONFIG_CMD_SDRAM 438 439 #ifdef CONFIG_COMPACT_FLASH 440 #define CONFIG_CMD_IDE 441 #define CONFIG_CMD_FAT 442 #endif 443 444 #ifdef CONFIG_PCI 445 #define CONFIG_CMD_PCI 446 #endif 447 448 #ifdef CONFIG_HARD_I2C 449 #define CONFIG_CMD_I2C 450 #endif 451 452 /* Watchdog */ 453 #undef CONFIG_WATCHDOG /* watchdog disabled */ 454 455 /* 456 * Miscellaneous configurable options 457 */ 458 #define CFG_LONGHELP /* undef to save memory */ 459 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 460 #define CFG_HUSH_PARSER /* Use the HUSH parser */ 461 #define CFG_PROMPT_HUSH_PS2 "> " 462 463 #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 464 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 465 466 #ifdef CONFIG_MPC8349ITX 467 #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 468 #else 469 #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 470 #endif 471 472 #if defined(CONFIG_CMD_KGDB) 473 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 474 #else 475 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 476 #endif 477 478 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ 479 #define CFG_MAXARGS 16 /* max number of command args */ 480 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 481 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 482 483 /* 484 * For booting Linux, the board info and command line data 485 * have to be in the first 8 MB of memory, since this is 486 * the maximum mapped by the Linux kernel during initialization. 487 */ 488 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 489 490 #define CFG_HRCW_LOW (\ 491 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 492 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 493 HRCWL_CSB_TO_CLKIN_4X1 |\ 494 HRCWL_VCO_1X2 |\ 495 HRCWL_CORE_TO_CSB_2X1) 496 497 #ifdef CFG_LOWBOOT 498 #define CFG_HRCW_HIGH (\ 499 HRCWH_PCI_HOST |\ 500 HRCWH_32_BIT_PCI |\ 501 HRCWH_PCI1_ARBITER_ENABLE |\ 502 HRCWH_PCI2_ARBITER_ENABLE |\ 503 HRCWH_CORE_ENABLE |\ 504 HRCWH_FROM_0X00000100 |\ 505 HRCWH_BOOTSEQ_DISABLE |\ 506 HRCWH_SW_WATCHDOG_DISABLE |\ 507 HRCWH_ROM_LOC_LOCAL_16BIT |\ 508 HRCWH_TSEC1M_IN_GMII |\ 509 HRCWH_TSEC2M_IN_GMII ) 510 #else 511 #define CFG_HRCW_HIGH (\ 512 HRCWH_PCI_HOST |\ 513 HRCWH_32_BIT_PCI |\ 514 HRCWH_PCI1_ARBITER_ENABLE |\ 515 HRCWH_PCI2_ARBITER_ENABLE |\ 516 HRCWH_CORE_ENABLE |\ 517 HRCWH_FROM_0XFFF00100 |\ 518 HRCWH_BOOTSEQ_DISABLE |\ 519 HRCWH_SW_WATCHDOG_DISABLE |\ 520 HRCWH_ROM_LOC_LOCAL_16BIT |\ 521 HRCWH_TSEC1M_IN_GMII |\ 522 HRCWH_TSEC2M_IN_GMII ) 523 #endif 524 525 /* 526 * System performance 527 */ 528 #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 529 #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 530 #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 531 #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 532 #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 533 #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 534 535 /* 536 * System IO Config 537 */ 538 #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 539 #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) 540 541 #define CFG_HID0_INIT 0x000000000 542 #define CFG_HID0_FINAL CFG_HID0_INIT 543 544 #define CFG_HID2 HID2_HBE 545 546 /* DDR */ 547 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 548 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 549 550 /* PCI */ 551 #ifdef CONFIG_PCI 552 #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 553 #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 554 #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 555 #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 556 #else 557 #define CFG_IBAT1L 0 558 #define CFG_IBAT1U 0 559 #define CFG_IBAT2L 0 560 #define CFG_IBAT2U 0 561 #endif 562 563 #ifdef CONFIG_MPC83XX_PCI2 564 #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 565 #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 566 #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 567 #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 568 #else 569 #define CFG_IBAT3L 0 570 #define CFG_IBAT3U 0 571 #define CFG_IBAT4L 0 572 #define CFG_IBAT4U 0 573 #endif 574 575 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 576 #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 577 #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 578 579 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 580 #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 581 #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 582 583 #define CFG_IBAT7L 0 584 #define CFG_IBAT7U 0 585 586 #define CFG_DBAT0L CFG_IBAT0L 587 #define CFG_DBAT0U CFG_IBAT0U 588 #define CFG_DBAT1L CFG_IBAT1L 589 #define CFG_DBAT1U CFG_IBAT1U 590 #define CFG_DBAT2L CFG_IBAT2L 591 #define CFG_DBAT2U CFG_IBAT2U 592 #define CFG_DBAT3L CFG_IBAT3L 593 #define CFG_DBAT3U CFG_IBAT3U 594 #define CFG_DBAT4L CFG_IBAT4L 595 #define CFG_DBAT4U CFG_IBAT4U 596 #define CFG_DBAT5L CFG_IBAT5L 597 #define CFG_DBAT5U CFG_IBAT5U 598 #define CFG_DBAT6L CFG_IBAT6L 599 #define CFG_DBAT6U CFG_IBAT6U 600 #define CFG_DBAT7L CFG_IBAT7L 601 #define CFG_DBAT7U CFG_IBAT7U 602 603 /* 604 * Internal Definitions 605 * 606 * Boot Flags 607 */ 608 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 609 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 610 611 #if defined(CONFIG_CMD_KGDB) 612 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 613 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 614 #endif 615 616 617 /* 618 * Environment Configuration 619 */ 620 #define CONFIG_ENV_OVERWRITE 621 622 #ifdef CONFIG_TSEC1 623 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 624 #endif 625 626 #ifdef CONFIG_TSEC2 627 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 628 #endif 629 630 #define CONFIG_IPADDR 192.168.1.253 631 #define CONFIG_SERVERIP 192.168.1.1 632 #define CONFIG_GATEWAYIP 192.168.1.1 633 #define CONFIG_NETMASK 255.255.252.0 634 #define CONFIG_NETDEV eth0 635 636 #ifdef CONFIG_MPC8349ITX 637 #define CONFIG_HOSTNAME mpc8349emitx 638 #else 639 #define CONFIG_HOSTNAME mpc8349emitxgp 640 #endif 641 642 /* Default path and filenames */ 643 #define CONFIG_ROOTPATH /nfsroot/rootfs 644 #define CONFIG_BOOTFILE uImage 645 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 646 647 #ifdef CONFIG_MPC8349ITX 648 #define CONFIG_FDTFILE mpc8349emitx.dtb 649 #else 650 #define CONFIG_FDTFILE mpc8349emitxgp.dtb 651 #endif 652 653 #define CONFIG_BOOTDELAY 0 654 655 #define XMK_STR(x) #x 656 #define MK_STR(x) XMK_STR(x) 657 658 #define CONFIG_BOOTARGS \ 659 "root=/dev/nfs rw" \ 660 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 661 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 662 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 663 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 664 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 665 666 #define CONFIG_EXTRA_ENV_SETTINGS \ 667 "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 668 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 669 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 670 "tftpflash=tftpboot $loadaddr $uboot; " \ 671 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 672 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 673 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 674 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 675 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 676 "fdtaddr=400000\0" \ 677 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 678 679 #define CONFIG_NFSBOOTCOMMAND \ 680 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 681 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 682 " console=$console,$baudrate $othbootargs; " \ 683 "tftp $loadaddr $bootfile;" \ 684 "tftp $fdtaddr $fdtfile;" \ 685 "bootm $loadaddr - $fdtaddr" 686 687 #define CONFIG_RAMBOOTCOMMAND \ 688 "setenv bootargs root=/dev/ram rw" \ 689 " console=$console,$baudrate $othbootargs; " \ 690 "tftp $ramdiskaddr $ramdiskfile;" \ 691 "tftp $loadaddr $bootfile;" \ 692 "tftp $fdtaddr $fdtfile;" \ 693 "bootm $loadaddr $ramdiskaddr $fdtaddr" 694 695 #undef MK_STR 696 #undef XMK_STR 697 698 #endif 699