1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 9 10 Memory map: 11 12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 19 0xF001_0000-0xF001_FFFF Local bus expansion slot 20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 23 24 I2C address list: 25 Align. Board 26 Bus Addr Part No. Description Length Location 27 ---------------------------------------------------------------- 28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 29 30 I2C1 0x20 PCF8574 I2C Expander 0 U8 31 I2C1 0x21 PCF8574 I2C Expander 0 U10 32 I2C1 0x38 PCF8574A I2C Expander 0 U8 33 I2C1 0x39 PCF8574A I2C Expander 0 U10 34 I2C1 0x51 (DDR) DDR EEPROM 1 U1 35 I2C1 0x68 DS1339 RTC 1 U68 36 37 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 38 */ 39 40 #ifndef __CONFIG_H 41 #define __CONFIG_H 42 43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 44 #define CONFIG_SYS_LOWBOOT 45 #endif 46 47 /* 48 * High Level Configuration Options 49 */ 50 #define CONFIG_MPC83xx 1 51 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 52 #define CONFIG_MPC8349 /* MPC8349 specific */ 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xFEF00000 56 #endif 57 58 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 59 60 #define CONFIG_MISC_INIT_F 61 #define CONFIG_MISC_INIT_R 62 63 /* 64 * On-board devices 65 */ 66 67 #ifdef CONFIG_MPC8349ITX 68 /* The CF card interface on the back of the board */ 69 #define CONFIG_COMPACT_FLASH 70 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 71 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 72 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 73 #endif 74 75 #define CONFIG_PCI 76 #define CONFIG_RTC_DS1337 77 #define CONFIG_SYS_I2C 78 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 79 80 /* 81 * Device configurations 82 */ 83 84 /* I2C */ 85 #ifdef CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C_FSL 87 #define CONFIG_SYS_FSL_I2C_SPEED 400000 88 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 89 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 90 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 91 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 92 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 93 94 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 95 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 96 97 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 98 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 99 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 100 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 101 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 102 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 103 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 104 105 /* Don't probe these addresses: */ 106 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 107 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 108 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 109 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 110 /* Bit definitions for the 8574[A] I2C expander */ 111 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 112 #define I2C_8574_REVISION 0x03 113 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 114 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 115 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 116 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 117 118 #endif 119 120 /* Compact Flash */ 121 #ifdef CONFIG_COMPACT_FLASH 122 123 #define CONFIG_SYS_IDE_MAXBUS 1 124 #define CONFIG_SYS_IDE_MAXDEVICE 1 125 126 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 127 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 128 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 129 #define CONFIG_SYS_ATA_REG_OFFSET 0 130 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 131 #define CONFIG_SYS_ATA_STRIDE 2 132 133 /* If a CF card is not inserted, time out quickly */ 134 #define ATA_RESET_TIME 1 135 136 #endif 137 138 /* 139 * SATA 140 */ 141 #ifdef CONFIG_SATA_SIL3114 142 143 #define CONFIG_SYS_SATA_MAX_DEVICE 4 144 #define CONFIG_LIBATA 145 #define CONFIG_LBA48 146 147 #endif 148 149 #ifdef CONFIG_SYS_USB_HOST 150 /* 151 * Support USB 152 */ 153 #define CONFIG_CMD_USB 154 #define CONFIG_USB_STORAGE 155 #define CONFIG_USB_EHCI 156 #define CONFIG_USB_EHCI_FSL 157 158 /* Current USB implementation supports the only USB controller, 159 * so we have to choose between the MPH or the DR ones */ 160 #if 1 161 #define CONFIG_HAS_FSL_MPH_USB 162 #else 163 #define CONFIG_HAS_FSL_DR_USB 164 #endif 165 166 #endif 167 168 /* 169 * DDR Setup 170 */ 171 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 173 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 174 #define CONFIG_SYS_83XX_DDR_USES_CS0 175 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 176 #define CONFIG_SYS_MEMTEST_END 0x2000 177 178 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 179 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 180 181 #define CONFIG_VERY_BIG_RAM 182 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 183 184 #ifdef CONFIG_SYS_I2C 185 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 186 #endif 187 188 /* No SPD? Then manually set up DDR parameters */ 189 #ifndef CONFIG_SPD_EEPROM 190 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 191 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 192 | CSCONFIG_ROW_BIT_13 \ 193 | CSCONFIG_COL_BIT_10) 194 195 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 196 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 197 #endif 198 199 /* 200 *Flash on the Local Bus 201 */ 202 203 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 204 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 205 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 206 #define CONFIG_SYS_FLASH_EMPTY_INFO 207 /* 127 64KB sectors + 8 8KB sectors per device */ 208 #define CONFIG_SYS_MAX_FLASH_SECT 135 209 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 210 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 212 213 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 214 boards, we say we have two, but don't display a message if we find only one. */ 215 #define CONFIG_SYS_FLASH_QUIET_TEST 216 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 217 #define CONFIG_SYS_FLASH_BANKS_LIST \ 218 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 219 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 220 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 221 222 /* Vitesse 7385 */ 223 224 #ifdef CONFIG_VSC7385_ENET 225 226 #define CONFIG_TSEC2 227 228 /* The flash address and size of the VSC7385 firmware image */ 229 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 230 #define CONFIG_VSC7385_IMAGE_SIZE 8192 231 232 #endif 233 234 /* 235 * BRx, ORx, LBLAWBARx, and LBLAWARx 236 */ 237 238 /* Flash */ 239 240 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 241 | BR_PS_16 \ 242 | BR_MS_GPCM \ 243 | BR_V) 244 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 245 | OR_UPM_XAM \ 246 | OR_GPCM_CSNT \ 247 | OR_GPCM_ACS_DIV2 \ 248 | OR_GPCM_XACS \ 249 | OR_GPCM_SCY_15 \ 250 | OR_GPCM_TRLX_SET \ 251 | OR_GPCM_EHTR_SET \ 252 | OR_GPCM_EAD) 253 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 254 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 255 256 /* Vitesse 7385 */ 257 258 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 259 260 #ifdef CONFIG_VSC7385_ENET 261 262 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 263 | BR_PS_8 \ 264 | BR_MS_GPCM \ 265 | BR_V) 266 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 267 | OR_GPCM_CSNT \ 268 | OR_GPCM_XACS \ 269 | OR_GPCM_SCY_15 \ 270 | OR_GPCM_SETA \ 271 | OR_GPCM_TRLX_SET \ 272 | OR_GPCM_EHTR_SET \ 273 | OR_GPCM_EAD) 274 275 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 276 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 277 278 #endif 279 280 /* LED */ 281 282 #define CONFIG_SYS_LED_BASE 0xF9000000 283 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 284 | BR_PS_8 \ 285 | BR_MS_GPCM \ 286 | BR_V) 287 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 288 | OR_GPCM_CSNT \ 289 | OR_GPCM_ACS_DIV2 \ 290 | OR_GPCM_XACS \ 291 | OR_GPCM_SCY_9 \ 292 | OR_GPCM_TRLX_SET \ 293 | OR_GPCM_EHTR_SET \ 294 | OR_GPCM_EAD) 295 296 /* Compact Flash */ 297 298 #ifdef CONFIG_COMPACT_FLASH 299 300 #define CONFIG_SYS_CF_BASE 0xF0000000 301 302 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 303 | BR_PS_16 \ 304 | BR_MS_UPMA \ 305 | BR_V) 306 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 307 308 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 309 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 310 311 #endif 312 313 /* 314 * U-Boot memory configuration 315 */ 316 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 317 318 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 319 #define CONFIG_SYS_RAMBOOT 320 #else 321 #undef CONFIG_SYS_RAMBOOT 322 #endif 323 324 #define CONFIG_SYS_INIT_RAM_LOCK 325 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 326 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 327 328 #define CONFIG_SYS_GBL_DATA_OFFSET \ 329 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 330 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 331 332 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 333 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 334 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 335 336 /* 337 * Local Bus LCRR and LBCR regs 338 * LCRR: DLL bypass, Clock divider is 4 339 * External Local Bus rate is 340 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 341 */ 342 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 343 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 344 #define CONFIG_SYS_LBC_LBCR 0x00000000 345 346 /* LB sdram refresh timer, about 6us */ 347 #define CONFIG_SYS_LBC_LSRT 0x32000000 348 /* LB refresh timer prescal, 266MHz/32*/ 349 #define CONFIG_SYS_LBC_MRTPR 0x20000000 350 351 /* 352 * Serial Port 353 */ 354 #define CONFIG_CONS_INDEX 1 355 #define CONFIG_SYS_NS16550 356 #define CONFIG_SYS_NS16550_SERIAL 357 #define CONFIG_SYS_NS16550_REG_SIZE 1 358 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 359 360 #define CONFIG_SYS_BAUDRATE_TABLE \ 361 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 362 363 #define CONFIG_CONSOLE ttyS0 364 #define CONFIG_BAUDRATE 115200 365 366 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 367 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 368 369 /* pass open firmware flat tree */ 370 #define CONFIG_OF_LIBFDT 1 371 #define CONFIG_OF_BOARD_SETUP 1 372 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 373 374 /* 375 * PCI 376 */ 377 #ifdef CONFIG_PCI 378 #define CONFIG_PCI_INDIRECT_BRIDGE 379 380 #define CONFIG_MPC83XX_PCI2 381 382 /* 383 * General PCI 384 * Addresses are mapped 1-1. 385 */ 386 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 387 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 388 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 389 #define CONFIG_SYS_PCI1_MMIO_BASE \ 390 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 391 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 392 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 393 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 394 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 395 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 396 397 #ifdef CONFIG_MPC83XX_PCI2 398 #define CONFIG_SYS_PCI2_MEM_BASE \ 399 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 400 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 401 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 402 #define CONFIG_SYS_PCI2_MMIO_BASE \ 403 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 404 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 405 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 406 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 407 #define CONFIG_SYS_PCI2_IO_PHYS \ 408 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 409 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 410 #endif 411 412 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 413 414 #ifndef CONFIG_PCI_PNP 415 #define PCI_ENET0_IOADDR 0x00000000 416 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 417 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 418 #endif 419 420 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 421 422 #endif 423 424 #define CONFIG_PCI_66M 425 #ifdef CONFIG_PCI_66M 426 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 427 #else 428 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 429 #endif 430 431 /* TSEC */ 432 433 #ifdef CONFIG_TSEC_ENET 434 435 #define CONFIG_MII 436 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 437 438 #define CONFIG_TSEC1 439 440 #ifdef CONFIG_TSEC1 441 #define CONFIG_HAS_ETH0 442 #define CONFIG_TSEC1_NAME "TSEC0" 443 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 444 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 445 #define TSEC1_PHYIDX 0 446 #define TSEC1_FLAGS TSEC_GIGABIT 447 #endif 448 449 #ifdef CONFIG_TSEC2 450 #define CONFIG_HAS_ETH1 451 #define CONFIG_TSEC2_NAME "TSEC1" 452 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 453 454 #define TSEC2_PHY_ADDR 4 455 #define TSEC2_PHYIDX 0 456 #define TSEC2_FLAGS TSEC_GIGABIT 457 #endif 458 459 #define CONFIG_ETHPRIME "Freescale TSEC" 460 461 #endif 462 463 /* 464 * Environment 465 */ 466 #define CONFIG_ENV_OVERWRITE 467 468 #ifndef CONFIG_SYS_RAMBOOT 469 #define CONFIG_ENV_IS_IN_FLASH 470 #define CONFIG_ENV_ADDR \ 471 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 472 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 473 #define CONFIG_ENV_SIZE 0x2000 474 #else 475 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 476 #undef CONFIG_FLASH_CFI_DRIVER 477 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 478 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 479 #define CONFIG_ENV_SIZE 0x2000 480 #endif 481 482 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 483 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 484 485 /* 486 * BOOTP options 487 */ 488 #define CONFIG_BOOTP_BOOTFILESIZE 489 #define CONFIG_BOOTP_BOOTPATH 490 #define CONFIG_BOOTP_GATEWAY 491 #define CONFIG_BOOTP_HOSTNAME 492 493 494 /* 495 * Command line configuration. 496 */ 497 #include <config_cmd_default.h> 498 499 #define CONFIG_CMD_CACHE 500 #define CONFIG_CMD_DATE 501 #define CONFIG_CMD_IRQ 502 #define CONFIG_CMD_NET 503 #define CONFIG_CMD_PING 504 #define CONFIG_CMD_DHCP 505 #define CONFIG_CMD_SDRAM 506 507 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 508 || defined(CONFIG_USB_STORAGE) 509 #define CONFIG_DOS_PARTITION 510 #define CONFIG_CMD_FAT 511 #define CONFIG_SUPPORT_VFAT 512 #endif 513 514 #ifdef CONFIG_COMPACT_FLASH 515 #define CONFIG_CMD_IDE 516 #endif 517 518 #ifdef CONFIG_SATA_SIL3114 519 #define CONFIG_CMD_SATA 520 #endif 521 522 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 523 #define CONFIG_CMD_EXT2 524 #endif 525 526 #ifdef CONFIG_PCI 527 #define CONFIG_CMD_PCI 528 #endif 529 530 #ifdef CONFIG_SYS_I2C 531 #define CONFIG_CMD_I2C 532 #endif 533 534 /* Watchdog */ 535 #undef CONFIG_WATCHDOG /* watchdog disabled */ 536 537 /* 538 * Miscellaneous configurable options 539 */ 540 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 541 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 542 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 543 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 544 545 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 546 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 547 548 #ifdef CONFIG_MPC8349ITX 549 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 550 #else 551 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 552 #endif 553 554 #if defined(CONFIG_CMD_KGDB) 555 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 556 #else 557 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 558 #endif 559 560 /* Print Buffer Size */ 561 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 562 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 563 /* Boot Argument Buffer Size */ 564 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 565 566 /* 567 * For booting Linux, the board info and command line data 568 * have to be in the first 256 MB of memory, since this is 569 * the maximum mapped by the Linux kernel during initialization. 570 */ 571 /* Initial Memory map for Linux*/ 572 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 573 574 #define CONFIG_SYS_HRCW_LOW (\ 575 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 576 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 577 HRCWL_CSB_TO_CLKIN_4X1 |\ 578 HRCWL_VCO_1X2 |\ 579 HRCWL_CORE_TO_CSB_2X1) 580 581 #ifdef CONFIG_SYS_LOWBOOT 582 #define CONFIG_SYS_HRCW_HIGH (\ 583 HRCWH_PCI_HOST |\ 584 HRCWH_32_BIT_PCI |\ 585 HRCWH_PCI1_ARBITER_ENABLE |\ 586 HRCWH_PCI2_ARBITER_ENABLE |\ 587 HRCWH_CORE_ENABLE |\ 588 HRCWH_FROM_0X00000100 |\ 589 HRCWH_BOOTSEQ_DISABLE |\ 590 HRCWH_SW_WATCHDOG_DISABLE |\ 591 HRCWH_ROM_LOC_LOCAL_16BIT |\ 592 HRCWH_TSEC1M_IN_GMII |\ 593 HRCWH_TSEC2M_IN_GMII) 594 #else 595 #define CONFIG_SYS_HRCW_HIGH (\ 596 HRCWH_PCI_HOST |\ 597 HRCWH_32_BIT_PCI |\ 598 HRCWH_PCI1_ARBITER_ENABLE |\ 599 HRCWH_PCI2_ARBITER_ENABLE |\ 600 HRCWH_CORE_ENABLE |\ 601 HRCWH_FROM_0XFFF00100 |\ 602 HRCWH_BOOTSEQ_DISABLE |\ 603 HRCWH_SW_WATCHDOG_DISABLE |\ 604 HRCWH_ROM_LOC_LOCAL_16BIT |\ 605 HRCWH_TSEC1M_IN_GMII |\ 606 HRCWH_TSEC2M_IN_GMII) 607 #endif 608 609 /* 610 * System performance 611 */ 612 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 613 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 614 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 615 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 616 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 617 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 618 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 619 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 620 621 /* 622 * System IO Config 623 */ 624 /* Needed for gigabit to work on TSEC 1 */ 625 #define CONFIG_SYS_SICRH SICRH_TSOBI1 626 /* USB DR as device + USB MPH as host */ 627 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 628 629 #define CONFIG_SYS_HID0_INIT 0x00000000 630 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 631 632 #define CONFIG_SYS_HID2 HID2_HBE 633 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 634 635 /* DDR */ 636 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 637 | BATL_PP_RW \ 638 | BATL_MEMCOHERENCE) 639 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 640 | BATU_BL_256M \ 641 | BATU_VS \ 642 | BATU_VP) 643 644 /* PCI */ 645 #ifdef CONFIG_PCI 646 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 647 | BATL_PP_RW \ 648 | BATL_MEMCOHERENCE) 649 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 650 | BATU_BL_256M \ 651 | BATU_VS \ 652 | BATU_VP) 653 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 654 | BATL_PP_RW \ 655 | BATL_CACHEINHIBIT \ 656 | BATL_GUARDEDSTORAGE) 657 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 658 | BATU_BL_256M \ 659 | BATU_VS \ 660 | BATU_VP) 661 #else 662 #define CONFIG_SYS_IBAT1L 0 663 #define CONFIG_SYS_IBAT1U 0 664 #define CONFIG_SYS_IBAT2L 0 665 #define CONFIG_SYS_IBAT2U 0 666 #endif 667 668 #ifdef CONFIG_MPC83XX_PCI2 669 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 670 | BATL_PP_RW \ 671 | BATL_MEMCOHERENCE) 672 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 673 | BATU_BL_256M \ 674 | BATU_VS \ 675 | BATU_VP) 676 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 677 | BATL_PP_RW \ 678 | BATL_CACHEINHIBIT \ 679 | BATL_GUARDEDSTORAGE) 680 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 681 | BATU_BL_256M \ 682 | BATU_VS \ 683 | BATU_VP) 684 #else 685 #define CONFIG_SYS_IBAT3L 0 686 #define CONFIG_SYS_IBAT3U 0 687 #define CONFIG_SYS_IBAT4L 0 688 #define CONFIG_SYS_IBAT4U 0 689 #endif 690 691 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 692 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 693 | BATL_PP_RW \ 694 | BATL_CACHEINHIBIT \ 695 | BATL_GUARDEDSTORAGE) 696 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 697 | BATU_BL_256M \ 698 | BATU_VS \ 699 | BATU_VP) 700 701 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 702 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 703 | BATL_PP_RW \ 704 | BATL_MEMCOHERENCE \ 705 | BATL_GUARDEDSTORAGE) 706 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 707 | BATU_BL_256M \ 708 | BATU_VS \ 709 | BATU_VP) 710 711 #define CONFIG_SYS_IBAT7L 0 712 #define CONFIG_SYS_IBAT7U 0 713 714 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 715 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 716 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 717 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 718 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 719 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 720 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 721 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 722 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 723 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 724 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 725 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 726 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 727 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 728 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 729 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 730 731 #if defined(CONFIG_CMD_KGDB) 732 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 733 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 734 #endif 735 736 737 /* 738 * Environment Configuration 739 */ 740 #define CONFIG_ENV_OVERWRITE 741 742 #define CONFIG_NETDEV "eth0" 743 744 #ifdef CONFIG_MPC8349ITX 745 #define CONFIG_HOSTNAME "mpc8349emitx" 746 #else 747 #define CONFIG_HOSTNAME "mpc8349emitxgp" 748 #endif 749 750 /* Default path and filenames */ 751 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 752 #define CONFIG_BOOTFILE "uImage" 753 /* U-Boot image on TFTP server */ 754 #define CONFIG_UBOOTPATH "u-boot.bin" 755 756 #ifdef CONFIG_MPC8349ITX 757 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 758 #else 759 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 760 #endif 761 762 #define CONFIG_BOOTDELAY 6 763 764 #define CONFIG_BOOTARGS \ 765 "root=/dev/nfs rw" \ 766 " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ 767 " ip=" __stringify(CONFIG_IPADDR) ":" \ 768 __stringify(CONFIG_SERVERIP) ":" \ 769 __stringify(CONFIG_GATEWAYIP) ":" \ 770 __stringify(CONFIG_NETMASK) ":" \ 771 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ 772 " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) 773 774 #define CONFIG_EXTRA_ENV_SETTINGS \ 775 "console=" __stringify(CONFIG_CONSOLE) "\0" \ 776 "netdev=" CONFIG_NETDEV "\0" \ 777 "uboot=" CONFIG_UBOOTPATH "\0" \ 778 "tftpflash=tftpboot $loadaddr $uboot; " \ 779 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 780 " +$filesize; " \ 781 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 782 " +$filesize; " \ 783 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 784 " $filesize; " \ 785 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 786 " +$filesize; " \ 787 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 788 " $filesize\0" \ 789 "fdtaddr=780000\0" \ 790 "fdtfile=" CONFIG_FDTFILE "\0" 791 792 #define CONFIG_NFSBOOTCOMMAND \ 793 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 794 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 795 " console=$console,$baudrate $othbootargs; " \ 796 "tftp $loadaddr $bootfile;" \ 797 "tftp $fdtaddr $fdtfile;" \ 798 "bootm $loadaddr - $fdtaddr" 799 800 #define CONFIG_RAMBOOTCOMMAND \ 801 "setenv bootargs root=/dev/ram rw" \ 802 " console=$console,$baudrate $othbootargs; " \ 803 "tftp $ramdiskaddr $ramdiskfile;" \ 804 "tftp $loadaddr $bootfile;" \ 805 "tftp $fdtaddr $fdtfile;" \ 806 "bootm $loadaddr $ramdiskaddr $fdtaddr" 807 808 #endif 809