1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 9 10 Memory map: 11 12 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 13 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 14 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 15 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 16 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 17 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 18 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 19 0xF001_0000-0xF001_FFFF Local bus expansion slot 20 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 21 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 22 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 23 24 I2C address list: 25 Align. Board 26 Bus Addr Part No. Description Length Location 27 ---------------------------------------------------------------- 28 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 29 30 I2C1 0x20 PCF8574 I2C Expander 0 U8 31 I2C1 0x21 PCF8574 I2C Expander 0 U10 32 I2C1 0x38 PCF8574A I2C Expander 0 U8 33 I2C1 0x39 PCF8574A I2C Expander 0 U10 34 I2C1 0x51 (DDR) DDR EEPROM 1 U1 35 I2C1 0x68 DS1339 RTC 1 U68 36 37 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 38 */ 39 40 #ifndef __CONFIG_H 41 #define __CONFIG_H 42 43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) 44 #define CONFIG_SYS_LOWBOOT 45 #endif 46 47 /* 48 * High Level Configuration Options 49 */ 50 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 51 #define CONFIG_MPC8349 /* MPC8349 specific */ 52 53 #ifndef CONFIG_SYS_TEXT_BASE 54 #define CONFIG_SYS_TEXT_BASE 0xFEF00000 55 #endif 56 57 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 58 59 #define CONFIG_MISC_INIT_F 60 #define CONFIG_MISC_INIT_R 61 62 /* 63 * On-board devices 64 */ 65 66 #ifdef CONFIG_MPC8349ITX 67 /* The CF card interface on the back of the board */ 68 #define CONFIG_COMPACT_FLASH 69 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 70 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 71 #endif 72 73 #define CONFIG_RTC_DS1337 74 #define CONFIG_SYS_I2C 75 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 76 77 /* 78 * Device configurations 79 */ 80 81 /* I2C */ 82 #ifdef CONFIG_SYS_I2C 83 #define CONFIG_SYS_I2C_FSL 84 #define CONFIG_SYS_FSL_I2C_SPEED 400000 85 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 86 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 87 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 88 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 89 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 90 91 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 92 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 93 94 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 95 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 96 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 97 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 98 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 99 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 100 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 101 102 /* Don't probe these addresses: */ 103 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ 104 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 105 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 106 {1, CONFIG_SYS_I2C_8574A_ADDR2} } 107 /* Bit definitions for the 8574[A] I2C expander */ 108 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 109 #define I2C_8574_REVISION 0x03 110 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 111 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 112 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 113 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 114 115 #endif 116 117 /* Compact Flash */ 118 #ifdef CONFIG_COMPACT_FLASH 119 120 #define CONFIG_SYS_IDE_MAXBUS 1 121 #define CONFIG_SYS_IDE_MAXDEVICE 1 122 123 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 124 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 125 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 126 #define CONFIG_SYS_ATA_REG_OFFSET 0 127 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 128 #define CONFIG_SYS_ATA_STRIDE 2 129 130 /* If a CF card is not inserted, time out quickly */ 131 #define ATA_RESET_TIME 1 132 133 #endif 134 135 /* 136 * SATA 137 */ 138 #ifdef CONFIG_SATA_SIL3114 139 140 #define CONFIG_SYS_SATA_MAX_DEVICE 4 141 #define CONFIG_LBA48 142 143 #endif 144 145 #ifdef CONFIG_SYS_USB_HOST 146 /* 147 * Support USB 148 */ 149 #define CONFIG_USB_EHCI_FSL 150 151 /* Current USB implementation supports the only USB controller, 152 * so we have to choose between the MPH or the DR ones */ 153 #if 1 154 #define CONFIG_HAS_FSL_MPH_USB 155 #else 156 #define CONFIG_HAS_FSL_DR_USB 157 #endif 158 159 #endif 160 161 /* 162 * DDR Setup 163 */ 164 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 166 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 167 #define CONFIG_SYS_83XX_DDR_USES_CS0 168 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 169 #define CONFIG_SYS_MEMTEST_END 0x2000 170 171 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 172 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 173 174 #define CONFIG_VERY_BIG_RAM 175 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 176 177 #ifdef CONFIG_SYS_I2C 178 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 179 #endif 180 181 /* No SPD? Then manually set up DDR parameters */ 182 #ifndef CONFIG_SPD_EEPROM 183 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 184 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 185 | CSCONFIG_ROW_BIT_13 \ 186 | CSCONFIG_COL_BIT_10) 187 188 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 189 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 190 #endif 191 192 /* 193 *Flash on the Local Bus 194 */ 195 196 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 197 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 198 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 199 #define CONFIG_SYS_FLASH_EMPTY_INFO 200 /* 127 64KB sectors + 8 8KB sectors per device */ 201 #define CONFIG_SYS_MAX_FLASH_SECT 135 202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 204 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 205 206 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 207 boards, we say we have two, but don't display a message if we find only one. */ 208 #define CONFIG_SYS_FLASH_QUIET_TEST 209 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 210 #define CONFIG_SYS_FLASH_BANKS_LIST \ 211 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 212 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 213 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 214 215 /* Vitesse 7385 */ 216 217 #ifdef CONFIG_VSC7385_ENET 218 219 #define CONFIG_TSEC2 220 221 /* The flash address and size of the VSC7385 firmware image */ 222 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 223 #define CONFIG_VSC7385_IMAGE_SIZE 8192 224 225 #endif 226 227 /* 228 * BRx, ORx, LBLAWBARx, and LBLAWARx 229 */ 230 231 /* Flash */ 232 233 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 234 | BR_PS_16 \ 235 | BR_MS_GPCM \ 236 | BR_V) 237 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 238 | OR_UPM_XAM \ 239 | OR_GPCM_CSNT \ 240 | OR_GPCM_ACS_DIV2 \ 241 | OR_GPCM_XACS \ 242 | OR_GPCM_SCY_15 \ 243 | OR_GPCM_TRLX_SET \ 244 | OR_GPCM_EHTR_SET \ 245 | OR_GPCM_EAD) 246 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 247 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) 248 249 /* Vitesse 7385 */ 250 251 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 252 253 #ifdef CONFIG_VSC7385_ENET 254 255 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ 256 | BR_PS_8 \ 257 | BR_MS_GPCM \ 258 | BR_V) 259 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ 260 | OR_GPCM_CSNT \ 261 | OR_GPCM_XACS \ 262 | OR_GPCM_SCY_15 \ 263 | OR_GPCM_SETA \ 264 | OR_GPCM_TRLX_SET \ 265 | OR_GPCM_EHTR_SET \ 266 | OR_GPCM_EAD) 267 268 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 269 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 270 271 #endif 272 273 /* LED */ 274 275 #define CONFIG_SYS_LED_BASE 0xF9000000 276 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ 277 | BR_PS_8 \ 278 | BR_MS_GPCM \ 279 | BR_V) 280 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ 281 | OR_GPCM_CSNT \ 282 | OR_GPCM_ACS_DIV2 \ 283 | OR_GPCM_XACS \ 284 | OR_GPCM_SCY_9 \ 285 | OR_GPCM_TRLX_SET \ 286 | OR_GPCM_EHTR_SET \ 287 | OR_GPCM_EAD) 288 289 /* Compact Flash */ 290 291 #ifdef CONFIG_COMPACT_FLASH 292 293 #define CONFIG_SYS_CF_BASE 0xF0000000 294 295 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ 296 | BR_PS_16 \ 297 | BR_MS_UPMA \ 298 | BR_V) 299 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 300 301 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 302 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 303 304 #endif 305 306 /* 307 * U-Boot memory configuration 308 */ 309 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 310 311 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 312 #define CONFIG_SYS_RAMBOOT 313 #else 314 #undef CONFIG_SYS_RAMBOOT 315 #endif 316 317 #define CONFIG_SYS_INIT_RAM_LOCK 318 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ 319 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 320 321 #define CONFIG_SYS_GBL_DATA_OFFSET \ 322 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 323 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 324 325 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 326 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 327 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ 328 329 /* 330 * Local Bus LCRR and LBCR regs 331 * LCRR: DLL bypass, Clock divider is 4 332 * External Local Bus rate is 333 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 334 */ 335 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 336 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 337 #define CONFIG_SYS_LBC_LBCR 0x00000000 338 339 /* LB sdram refresh timer, about 6us */ 340 #define CONFIG_SYS_LBC_LSRT 0x32000000 341 /* LB refresh timer prescal, 266MHz/32*/ 342 #define CONFIG_SYS_LBC_MRTPR 0x20000000 343 344 /* 345 * Serial Port 346 */ 347 #define CONFIG_CONS_INDEX 1 348 #define CONFIG_SYS_NS16550_SERIAL 349 #define CONFIG_SYS_NS16550_REG_SIZE 1 350 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 351 352 #define CONFIG_SYS_BAUDRATE_TABLE \ 353 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 354 355 #define CONSOLE ttyS0 356 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 359 360 /* 361 * PCI 362 */ 363 #ifdef CONFIG_PCI 364 #define CONFIG_PCI_INDIRECT_BRIDGE 365 366 #define CONFIG_MPC83XX_PCI2 367 368 /* 369 * General PCI 370 * Addresses are mapped 1-1. 371 */ 372 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 373 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 374 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 375 #define CONFIG_SYS_PCI1_MMIO_BASE \ 376 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 377 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 378 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 379 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 380 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 381 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 382 383 #ifdef CONFIG_MPC83XX_PCI2 384 #define CONFIG_SYS_PCI2_MEM_BASE \ 385 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 386 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 387 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 388 #define CONFIG_SYS_PCI2_MMIO_BASE \ 389 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 390 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 391 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 392 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 393 #define CONFIG_SYS_PCI2_IO_PHYS \ 394 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 395 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 396 #endif 397 398 #ifndef CONFIG_PCI_PNP 399 #define PCI_ENET0_IOADDR 0x00000000 400 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 401 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 402 #endif 403 404 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 405 406 #endif 407 408 #define CONFIG_PCI_66M 409 #ifdef CONFIG_PCI_66M 410 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 411 #else 412 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 413 #endif 414 415 /* TSEC */ 416 417 #ifdef CONFIG_TSEC_ENET 418 419 #define CONFIG_MII 420 421 #define CONFIG_TSEC1 422 423 #ifdef CONFIG_TSEC1 424 #define CONFIG_HAS_ETH0 425 #define CONFIG_TSEC1_NAME "TSEC0" 426 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 427 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 428 #define TSEC1_PHYIDX 0 429 #define TSEC1_FLAGS TSEC_GIGABIT 430 #endif 431 432 #ifdef CONFIG_TSEC2 433 #define CONFIG_HAS_ETH1 434 #define CONFIG_TSEC2_NAME "TSEC1" 435 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 436 437 #define TSEC2_PHY_ADDR 4 438 #define TSEC2_PHYIDX 0 439 #define TSEC2_FLAGS TSEC_GIGABIT 440 #endif 441 442 #define CONFIG_ETHPRIME "Freescale TSEC" 443 444 #endif 445 446 /* 447 * Environment 448 */ 449 #define CONFIG_ENV_OVERWRITE 450 451 #ifndef CONFIG_SYS_RAMBOOT 452 #define CONFIG_ENV_ADDR \ 453 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 454 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 455 #define CONFIG_ENV_SIZE 0x2000 456 #else 457 #undef CONFIG_FLASH_CFI_DRIVER 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 459 #define CONFIG_ENV_SIZE 0x2000 460 #endif 461 462 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 463 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 464 465 /* 466 * BOOTP options 467 */ 468 #define CONFIG_BOOTP_BOOTFILESIZE 469 #define CONFIG_BOOTP_BOOTPATH 470 #define CONFIG_BOOTP_GATEWAY 471 #define CONFIG_BOOTP_HOSTNAME 472 473 /* Watchdog */ 474 #undef CONFIG_WATCHDOG /* watchdog disabled */ 475 476 /* 477 * Miscellaneous configurable options 478 */ 479 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 480 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 481 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 482 483 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 484 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 485 486 /* 487 * For booting Linux, the board info and command line data 488 * have to be in the first 256 MB of memory, since this is 489 * the maximum mapped by the Linux kernel during initialization. 490 */ 491 /* Initial Memory map for Linux*/ 492 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 493 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 494 495 #define CONFIG_SYS_HRCW_LOW (\ 496 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 497 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 498 HRCWL_CSB_TO_CLKIN_4X1 |\ 499 HRCWL_VCO_1X2 |\ 500 HRCWL_CORE_TO_CSB_2X1) 501 502 #ifdef CONFIG_SYS_LOWBOOT 503 #define CONFIG_SYS_HRCW_HIGH (\ 504 HRCWH_PCI_HOST |\ 505 HRCWH_32_BIT_PCI |\ 506 HRCWH_PCI1_ARBITER_ENABLE |\ 507 HRCWH_PCI2_ARBITER_ENABLE |\ 508 HRCWH_CORE_ENABLE |\ 509 HRCWH_FROM_0X00000100 |\ 510 HRCWH_BOOTSEQ_DISABLE |\ 511 HRCWH_SW_WATCHDOG_DISABLE |\ 512 HRCWH_ROM_LOC_LOCAL_16BIT |\ 513 HRCWH_TSEC1M_IN_GMII |\ 514 HRCWH_TSEC2M_IN_GMII) 515 #else 516 #define CONFIG_SYS_HRCW_HIGH (\ 517 HRCWH_PCI_HOST |\ 518 HRCWH_32_BIT_PCI |\ 519 HRCWH_PCI1_ARBITER_ENABLE |\ 520 HRCWH_PCI2_ARBITER_ENABLE |\ 521 HRCWH_CORE_ENABLE |\ 522 HRCWH_FROM_0XFFF00100 |\ 523 HRCWH_BOOTSEQ_DISABLE |\ 524 HRCWH_SW_WATCHDOG_DISABLE |\ 525 HRCWH_ROM_LOC_LOCAL_16BIT |\ 526 HRCWH_TSEC1M_IN_GMII |\ 527 HRCWH_TSEC2M_IN_GMII) 528 #endif 529 530 /* 531 * System performance 532 */ 533 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 534 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 535 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 536 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 537 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 538 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 539 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 540 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 541 542 /* 543 * System IO Config 544 */ 545 /* Needed for gigabit to work on TSEC 1 */ 546 #define CONFIG_SYS_SICRH SICRH_TSOBI1 547 /* USB DR as device + USB MPH as host */ 548 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) 549 550 #define CONFIG_SYS_HID0_INIT 0x00000000 551 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE 552 553 #define CONFIG_SYS_HID2 HID2_HBE 554 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 555 556 /* DDR */ 557 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ 558 | BATL_PP_RW \ 559 | BATL_MEMCOHERENCE) 560 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 561 | BATU_BL_256M \ 562 | BATU_VS \ 563 | BATU_VP) 564 565 /* PCI */ 566 #ifdef CONFIG_PCI 567 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ 568 | BATL_PP_RW \ 569 | BATL_MEMCOHERENCE) 570 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 571 | BATU_BL_256M \ 572 | BATU_VS \ 573 | BATU_VP) 574 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 575 | BATL_PP_RW \ 576 | BATL_CACHEINHIBIT \ 577 | BATL_GUARDEDSTORAGE) 578 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 579 | BATU_BL_256M \ 580 | BATU_VS \ 581 | BATU_VP) 582 #else 583 #define CONFIG_SYS_IBAT1L 0 584 #define CONFIG_SYS_IBAT1U 0 585 #define CONFIG_SYS_IBAT2L 0 586 #define CONFIG_SYS_IBAT2U 0 587 #endif 588 589 #ifdef CONFIG_MPC83XX_PCI2 590 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ 591 | BATL_PP_RW \ 592 | BATL_MEMCOHERENCE) 593 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ 594 | BATU_BL_256M \ 595 | BATU_VS \ 596 | BATU_VP) 597 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ 598 | BATL_PP_RW \ 599 | BATL_CACHEINHIBIT \ 600 | BATL_GUARDEDSTORAGE) 601 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ 602 | BATU_BL_256M \ 603 | BATU_VS \ 604 | BATU_VP) 605 #else 606 #define CONFIG_SYS_IBAT3L 0 607 #define CONFIG_SYS_IBAT3U 0 608 #define CONFIG_SYS_IBAT4L 0 609 #define CONFIG_SYS_IBAT4U 0 610 #endif 611 612 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 613 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 614 | BATL_PP_RW \ 615 | BATL_CACHEINHIBIT \ 616 | BATL_GUARDEDSTORAGE) 617 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 618 | BATU_BL_256M \ 619 | BATU_VS \ 620 | BATU_VP) 621 622 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 623 #define CONFIG_SYS_IBAT6L (0xF0000000 \ 624 | BATL_PP_RW \ 625 | BATL_MEMCOHERENCE \ 626 | BATL_GUARDEDSTORAGE) 627 #define CONFIG_SYS_IBAT6U (0xF0000000 \ 628 | BATU_BL_256M \ 629 | BATU_VS \ 630 | BATU_VP) 631 632 #define CONFIG_SYS_IBAT7L 0 633 #define CONFIG_SYS_IBAT7U 0 634 635 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 636 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 637 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 638 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 639 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 640 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 641 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 642 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 643 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 644 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 645 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 646 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 647 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 648 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 649 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 650 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 651 652 #if defined(CONFIG_CMD_KGDB) 653 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 654 #endif 655 656 /* 657 * Environment Configuration 658 */ 659 #define CONFIG_ENV_OVERWRITE 660 661 #define CONFIG_NETDEV "eth0" 662 663 /* Default path and filenames */ 664 #define CONFIG_ROOTPATH "/nfsroot/rootfs" 665 #define CONFIG_BOOTFILE "uImage" 666 /* U-Boot image on TFTP server */ 667 #define CONFIG_UBOOTPATH "u-boot.bin" 668 669 #ifdef CONFIG_MPC8349ITX 670 #define CONFIG_FDTFILE "mpc8349emitx.dtb" 671 #else 672 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" 673 #endif 674 675 676 #define CONFIG_EXTRA_ENV_SETTINGS \ 677 "console=" __stringify(CONSOLE) "\0" \ 678 "netdev=" CONFIG_NETDEV "\0" \ 679 "uboot=" CONFIG_UBOOTPATH "\0" \ 680 "tftpflash=tftpboot $loadaddr $uboot; " \ 681 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 682 " +$filesize; " \ 683 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 684 " +$filesize; " \ 685 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 686 " $filesize; " \ 687 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 688 " +$filesize; " \ 689 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 690 " $filesize\0" \ 691 "fdtaddr=780000\0" \ 692 "fdtfile=" CONFIG_FDTFILE "\0" 693 694 #define CONFIG_NFSBOOTCOMMAND \ 695 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 696 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ 697 " console=$console,$baudrate $othbootargs; " \ 698 "tftp $loadaddr $bootfile;" \ 699 "tftp $fdtaddr $fdtfile;" \ 700 "bootm $loadaddr - $fdtaddr" 701 702 #define CONFIG_RAMBOOTCOMMAND \ 703 "setenv bootargs root=/dev/ram rw" \ 704 " console=$console,$baudrate $othbootargs; " \ 705 "tftp $ramdiskaddr $ramdiskfile;" \ 706 "tftp $loadaddr $bootfile;" \ 707 "tftp $fdtaddr $fdtfile;" \ 708 "bootm $loadaddr $ramdiskaddr $fdtaddr" 709 710 #endif 711