1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file 25 26 Memory map: 27 28 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) 29 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) 30 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) 31 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 32 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 33 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) 34 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 35 0xF001_0000-0xF001_FFFF Local bus expansion slot 36 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) 37 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory 38 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) 39 40 I2C address list: 41 Align. Board 42 Bus Addr Part No. Description Length Location 43 ---------------------------------------------------------------- 44 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 45 46 I2C1 0x20 PCF8574 I2C Expander 0 U8 47 I2C1 0x21 PCF8574 I2C Expander 0 U10 48 I2C1 0x38 PCF8574A I2C Expander 0 U8 49 I2C1 0x39 PCF8574A I2C Expander 0 U10 50 I2C1 0x51 (DDR) DDR EEPROM 1 U1 51 I2C1 0x68 DS1339 RTC 1 U68 52 53 Note that a given board has *either* a pair of 8574s or a pair of 8574As. 54 */ 55 56 #ifndef __CONFIG_H 57 #define __CONFIG_H 58 59 #if (TEXT_BASE == 0xFE000000) 60 #define CONFIG_SYS_LOWBOOT 61 #endif 62 63 /* 64 * High Level Configuration Options 65 */ 66 #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ 67 #define CONFIG_MPC8349 /* MPC8349 specific */ 68 69 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ 70 71 #define CONFIG_MISC_INIT_F 72 #define CONFIG_MISC_INIT_R 73 74 /* 75 * On-board devices 76 */ 77 78 #ifdef CONFIG_MPC8349ITX 79 #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ 80 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ 81 #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ 82 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ 83 #endif 84 85 #define CONFIG_PCI 86 #define CONFIG_RTC_DS1337 87 #define CONFIG_HARD_I2C 88 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ 89 90 /* 91 * Device configurations 92 */ 93 94 /* I2C */ 95 #ifdef CONFIG_HARD_I2C 96 97 #define CONFIG_FSL_I2C 98 #define CONFIG_I2C_MULTI_BUS 99 #define CONFIG_SYS_I2C_OFFSET 0x3000 100 #define CONFIG_SYS_I2C2_OFFSET 0x3100 101 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ 102 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ 103 104 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ 105 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ 106 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ 107 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ 108 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ 109 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ 110 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ 111 112 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 113 #define CONFIG_SYS_I2C_SLAVE 0x7F 114 115 /* Don't probe these addresses: */ 116 #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ 117 {1, CONFIG_SYS_I2C_8574_ADDR2}, \ 118 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ 119 {1, CONFIG_SYS_I2C_8574A_ADDR2}} 120 /* Bit definitions for the 8574[A] I2C expander */ 121 #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ 122 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ 123 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ 124 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ 125 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ 126 127 #undef CONFIG_SOFT_I2C 128 129 #endif 130 131 /* Compact Flash */ 132 #ifdef CONFIG_COMPACT_FLASH 133 134 #define CONFIG_SYS_IDE_MAXBUS 1 135 #define CONFIG_SYS_IDE_MAXDEVICE 1 136 137 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 138 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE 139 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 140 #define CONFIG_SYS_ATA_REG_OFFSET 0 141 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 142 #define CONFIG_SYS_ATA_STRIDE 2 143 144 #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ 145 146 #endif 147 148 /* 149 * SATA 150 */ 151 #ifdef CONFIG_SATA_SIL3114 152 153 #define CONFIG_SYS_SATA_MAX_DEVICE 4 154 #define CONFIG_LIBATA 155 #define CONFIG_LBA48 156 157 #endif 158 159 #ifdef CONFIG_SYS_USB_HOST 160 /* 161 * Support USB 162 */ 163 #define CONFIG_CMD_USB 164 #define CONFIG_USB_STORAGE 165 #define CONFIG_USB_EHCI 166 #define CONFIG_USB_EHCI_FSL 167 168 /* Current USB implementation supports the only USB controller, 169 * so we have to choose between the MPH or the DR ones */ 170 #if 1 171 #define CONFIG_HAS_FSL_MPH_USB 172 #else 173 #define CONFIG_HAS_FSL_DR_USB 174 #endif 175 176 #endif 177 178 /* 179 * DDR Setup 180 */ 181 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 182 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 183 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 184 #define CONFIG_SYS_83XX_DDR_USES_CS0 185 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ 186 #define CONFIG_SYS_MEMTEST_END 0x2000 187 188 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 189 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 190 191 #define CONFIG_VERY_BIG_RAM 192 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) 193 194 #ifdef CONFIG_HARD_I2C 195 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ 196 #endif 197 198 #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ 199 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ 200 #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 201 202 #define CONFIG_SYS_DDR_TIMING_1 0x26242321 203 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ 204 #endif 205 206 /* 207 *Flash on the Local Bus 208 */ 209 210 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 211 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 212 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ 215 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 216 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 218 219 /* The ITX has two flash chips, but the ITX-GP has only one. To support both 220 boards, we say we have two, but don't display a message if we find only one. */ 221 #define CONFIG_SYS_FLASH_QUIET_TEST 222 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 223 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} 224 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ 225 #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ 226 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 227 228 /* Vitesse 7385 */ 229 230 #ifdef CONFIG_VSC7385_ENET 231 232 #define CONFIG_TSEC2 233 234 /* The flash address and size of the VSC7385 firmware image */ 235 #define CONFIG_VSC7385_IMAGE 0xFEFFE000 236 #define CONFIG_VSC7385_IMAGE_SIZE 8192 237 238 #endif 239 240 /* 241 * BRx, ORx, LBLAWBARx, and LBLAWARx 242 */ 243 244 /* Flash */ 245 246 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) 247 #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ 248 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ 249 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 250 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 251 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) 252 253 /* Vitesse 7385 */ 254 255 #define CONFIG_SYS_VSC7385_BASE 0xF8000000 256 257 #ifdef CONFIG_VSC7385_ENET 258 259 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) 260 #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 261 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ 262 OR_GPCM_EHTR | OR_GPCM_EAD) 263 264 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE 265 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) 266 267 #endif 268 269 /* LED */ 270 271 #define CONFIG_SYS_LED_BASE 0xF9000000 272 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) 273 #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ 274 OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ 275 OR_GPCM_EHTR | OR_GPCM_EAD) 276 277 /* Compact Flash */ 278 279 #ifdef CONFIG_COMPACT_FLASH 280 281 #define CONFIG_SYS_CF_BASE 0xF0000000 282 283 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) 284 #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) 285 286 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE 287 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) 288 289 #endif 290 291 /* 292 * U-Boot memory configuration 293 */ 294 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 295 296 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 297 #define CONFIG_SYS_RAMBOOT 298 #else 299 #undef CONFIG_SYS_RAMBOOT 300 #endif 301 302 #define CONFIG_SYS_INIT_RAM_LOCK 303 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 304 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 305 306 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 307 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 308 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 309 310 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 311 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 312 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 313 314 /* 315 * Local Bus LCRR and LBCR regs 316 * LCRR: DLL bypass, Clock divider is 4 317 * External Local Bus rate is 318 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 319 */ 320 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 321 #define CONFIG_SYS_LBC_LBCR 0x00000000 322 323 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ 324 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ 325 326 /* 327 * Serial Port 328 */ 329 #define CONFIG_CONS_INDEX 1 330 #undef CONFIG_SERIAL_SOFTWARE_FIFO 331 #define CONFIG_SYS_NS16550 332 #define CONFIG_SYS_NS16550_SERIAL 333 #define CONFIG_SYS_NS16550_REG_SIZE 1 334 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 335 336 #define CONFIG_SYS_BAUDRATE_TABLE \ 337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 338 339 #define CONFIG_CONSOLE ttyS0 340 #define CONFIG_BAUDRATE 115200 341 342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 344 345 /* pass open firmware flat tree */ 346 #define CONFIG_OF_LIBFDT 1 347 #define CONFIG_OF_BOARD_SETUP 1 348 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 349 350 /* 351 * PCI 352 */ 353 #ifdef CONFIG_PCI 354 355 #define CONFIG_MPC83XX_PCI2 356 357 /* 358 * General PCI 359 * Addresses are mapped 1-1. 360 */ 361 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 362 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 363 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 364 #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) 365 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 366 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 367 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 368 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 369 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 370 371 #ifdef CONFIG_MPC83XX_PCI2 372 #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) 373 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 374 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 375 #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) 376 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 377 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 378 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 379 #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) 380 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ 381 #endif 382 383 #define CONFIG_NET_MULTI 384 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 385 386 #ifndef CONFIG_PCI_PNP 387 #define PCI_ENET0_IOADDR 0x00000000 388 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE 389 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ 390 #endif 391 392 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 393 394 #endif 395 396 #define PCI_66M 397 #ifdef PCI_66M 398 #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ 399 #else 400 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 401 #endif 402 403 /* TSEC */ 404 405 #ifdef CONFIG_TSEC_ENET 406 407 #define CONFIG_NET_MULTI 408 #define CONFIG_MII 409 #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ 410 411 #define CONFIG_TSEC1 412 413 #ifdef CONFIG_TSEC1 414 #define CONFIG_HAS_ETH0 415 #define CONFIG_TSEC1_NAME "TSEC0" 416 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 417 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ 418 #define TSEC1_PHYIDX 0 419 #define TSEC1_FLAGS TSEC_GIGABIT 420 #endif 421 422 #ifdef CONFIG_TSEC2 423 #define CONFIG_HAS_ETH1 424 #define CONFIG_TSEC2_NAME "TSEC1" 425 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 426 427 #define TSEC2_PHY_ADDR 4 428 #define TSEC2_PHYIDX 0 429 #define TSEC2_FLAGS TSEC_GIGABIT 430 #endif 431 432 #define CONFIG_ETHPRIME "Freescale TSEC" 433 434 #endif 435 436 /* 437 * Environment 438 */ 439 #define CONFIG_ENV_OVERWRITE 440 441 #ifndef CONFIG_SYS_RAMBOOT 442 #define CONFIG_ENV_IS_IN_FLASH 443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 444 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ 445 #define CONFIG_ENV_SIZE 0x2000 446 #else 447 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 448 #undef CONFIG_FLASH_CFI_DRIVER 449 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 450 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 451 #define CONFIG_ENV_SIZE 0x2000 452 #endif 453 454 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 455 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 456 457 /* 458 * BOOTP options 459 */ 460 #define CONFIG_BOOTP_BOOTFILESIZE 461 #define CONFIG_BOOTP_BOOTPATH 462 #define CONFIG_BOOTP_GATEWAY 463 #define CONFIG_BOOTP_HOSTNAME 464 465 466 /* 467 * Command line configuration. 468 */ 469 #include <config_cmd_default.h> 470 471 #define CONFIG_CMD_CACHE 472 #define CONFIG_CMD_DATE 473 #define CONFIG_CMD_IRQ 474 #define CONFIG_CMD_NET 475 #define CONFIG_CMD_PING 476 #define CONFIG_CMD_DHCP 477 #define CONFIG_CMD_SDRAM 478 479 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ 480 || defined(CONFIG_USB_STORAGE) 481 #define CONFIG_DOS_PARTITION 482 #define CONFIG_CMD_FAT 483 #define CONFIG_SUPPORT_VFAT 484 #endif 485 486 #ifdef CONFIG_COMPACT_FLASH 487 #define CONFIG_CMD_IDE 488 #endif 489 490 #ifdef CONFIG_SATA_SIL3114 491 #define CONFIG_CMD_SATA 492 #endif 493 494 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) 495 #define CONFIG_CMD_EXT2 496 #endif 497 498 #ifdef CONFIG_PCI 499 #define CONFIG_CMD_PCI 500 #endif 501 502 #ifdef CONFIG_HARD_I2C 503 #define CONFIG_CMD_I2C 504 #endif 505 506 /* Watchdog */ 507 #undef CONFIG_WATCHDOG /* watchdog disabled */ 508 509 /* 510 * Miscellaneous configurable options 511 */ 512 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 513 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 514 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 515 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 516 517 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 518 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ 519 520 #ifdef CONFIG_MPC8349ITX 521 #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ 522 #else 523 #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ 524 #endif 525 526 #if defined(CONFIG_CMD_KGDB) 527 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 528 #else 529 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 530 #endif 531 532 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 533 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 534 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 535 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 536 537 /* 538 * For booting Linux, the board info and command line data 539 * have to be in the first 8 MB of memory, since this is 540 * the maximum mapped by the Linux kernel during initialization. 541 */ 542 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 543 544 #define CONFIG_SYS_HRCW_LOW (\ 545 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 546 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 547 HRCWL_CSB_TO_CLKIN_4X1 |\ 548 HRCWL_VCO_1X2 |\ 549 HRCWL_CORE_TO_CSB_2X1) 550 551 #ifdef CONFIG_SYS_LOWBOOT 552 #define CONFIG_SYS_HRCW_HIGH (\ 553 HRCWH_PCI_HOST |\ 554 HRCWH_32_BIT_PCI |\ 555 HRCWH_PCI1_ARBITER_ENABLE |\ 556 HRCWH_PCI2_ARBITER_ENABLE |\ 557 HRCWH_CORE_ENABLE |\ 558 HRCWH_FROM_0X00000100 |\ 559 HRCWH_BOOTSEQ_DISABLE |\ 560 HRCWH_SW_WATCHDOG_DISABLE |\ 561 HRCWH_ROM_LOC_LOCAL_16BIT |\ 562 HRCWH_TSEC1M_IN_GMII |\ 563 HRCWH_TSEC2M_IN_GMII ) 564 #else 565 #define CONFIG_SYS_HRCW_HIGH (\ 566 HRCWH_PCI_HOST |\ 567 HRCWH_32_BIT_PCI |\ 568 HRCWH_PCI1_ARBITER_ENABLE |\ 569 HRCWH_PCI2_ARBITER_ENABLE |\ 570 HRCWH_CORE_ENABLE |\ 571 HRCWH_FROM_0XFFF00100 |\ 572 HRCWH_BOOTSEQ_DISABLE |\ 573 HRCWH_SW_WATCHDOG_DISABLE |\ 574 HRCWH_ROM_LOC_LOCAL_16BIT |\ 575 HRCWH_TSEC1M_IN_GMII |\ 576 HRCWH_TSEC2M_IN_GMII ) 577 #endif 578 579 /* 580 * System performance 581 */ 582 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ 583 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ 584 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ 585 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ 586 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ 587 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ 588 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ 589 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ 590 591 /* 592 * System IO Config 593 */ 594 #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ 595 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */ 596 597 #define CONFIG_SYS_HID0_INIT 0x000000000 598 #define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT 599 600 #define CONFIG_SYS_HID2 HID2_HBE 601 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 602 603 /* DDR */ 604 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 605 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 606 607 /* PCI */ 608 #ifdef CONFIG_PCI 609 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 610 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 611 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 612 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 613 #else 614 #define CONFIG_SYS_IBAT1L 0 615 #define CONFIG_SYS_IBAT1U 0 616 #define CONFIG_SYS_IBAT2L 0 617 #define CONFIG_SYS_IBAT2U 0 618 #endif 619 620 #ifdef CONFIG_MPC83XX_PCI2 621 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 622 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 623 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 624 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 625 #else 626 #define CONFIG_SYS_IBAT3L 0 627 #define CONFIG_SYS_IBAT3U 0 628 #define CONFIG_SYS_IBAT4L 0 629 #define CONFIG_SYS_IBAT4U 0 630 #endif 631 632 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 633 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 634 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) 635 636 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 637 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ 638 BATL_GUARDEDSTORAGE) 639 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 640 641 #define CONFIG_SYS_IBAT7L 0 642 #define CONFIG_SYS_IBAT7U 0 643 644 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 645 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 646 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 647 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 648 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 649 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 650 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 651 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 652 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 653 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 654 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 655 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 656 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 657 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 658 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 659 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 660 661 /* 662 * Internal Definitions 663 * 664 * Boot Flags 665 */ 666 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 667 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 668 669 #if defined(CONFIG_CMD_KGDB) 670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 671 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 672 #endif 673 674 675 /* 676 * Environment Configuration 677 */ 678 #define CONFIG_ENV_OVERWRITE 679 680 #ifdef CONFIG_HAS_ETH0 681 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 682 #endif 683 684 #ifdef CONFIG_HAS_ETH1 685 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 686 #endif 687 688 #define CONFIG_IPADDR 192.168.1.253 689 #define CONFIG_SERVERIP 192.168.1.1 690 #define CONFIG_GATEWAYIP 192.168.1.1 691 #define CONFIG_NETMASK 255.255.252.0 692 #define CONFIG_NETDEV eth0 693 694 #ifdef CONFIG_MPC8349ITX 695 #define CONFIG_HOSTNAME mpc8349emitx 696 #else 697 #define CONFIG_HOSTNAME mpc8349emitxgp 698 #endif 699 700 /* Default path and filenames */ 701 #define CONFIG_ROOTPATH /nfsroot/rootfs 702 #define CONFIG_BOOTFILE uImage 703 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 704 705 #ifdef CONFIG_MPC8349ITX 706 #define CONFIG_FDTFILE mpc8349emitx.dtb 707 #else 708 #define CONFIG_FDTFILE mpc8349emitxgp.dtb 709 #endif 710 711 #define CONFIG_BOOTDELAY 0 712 713 #define XMK_STR(x) #x 714 #define MK_STR(x) XMK_STR(x) 715 716 #define CONFIG_BOOTARGS \ 717 "root=/dev/nfs rw" \ 718 " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ 719 " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ 720 MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ 721 MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ 722 " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) 723 724 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 "console=" MK_STR(CONFIG_CONSOLE) "\0" \ 726 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 727 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 728 "tftpflash=tftpboot $loadaddr $uboot; " \ 729 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 730 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 731 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 732 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 733 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 734 "fdtaddr=400000\0" \ 735 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" 736 737 #define CONFIG_NFSBOOTCOMMAND \ 738 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ 739 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 740 " console=$console,$baudrate $othbootargs; " \ 741 "tftp $loadaddr $bootfile;" \ 742 "tftp $fdtaddr $fdtfile;" \ 743 "bootm $loadaddr - $fdtaddr" 744 745 #define CONFIG_RAMBOOTCOMMAND \ 746 "setenv bootargs root=/dev/ram rw" \ 747 " console=$console,$baudrate $othbootargs; " \ 748 "tftp $ramdiskaddr $ramdiskfile;" \ 749 "tftp $loadaddr $bootfile;" \ 750 "tftp $fdtaddr $fdtfile;" \ 751 "bootm $loadaddr $ramdiskaddr $fdtaddr" 752 753 #undef MK_STR 754 #undef XMK_STR 755 756 #endif 757